1  /*
2   * OMAP4XXX L3 Interconnect  error handling driver header
3   *
4   * Copyright (C) 2011 Texas Corporation
5   *	Santosh Shilimkar <santosh.shilimkar@ti.com>
6   *	sricharan <r.sricharan@ti.com>
7   *
8   * This program is free software; you can redistribute it and/or modify
9   * it under the terms of the GNU General Public License as published by
10   * the Free Software Foundation; either version 2 of the License, or
11   * (at your option) any later version.
12   *
13   * This program is distributed in the hope that it will be useful,
14   * but WITHOUT ANY WARRANTY; without even the implied warranty of
15   * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16   * GNU General Public License for more details.
17   *
18   * You should have received a copy of the GNU General Public License
19   * along with this program; if not, write to the Free Software
20   * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
21   * USA
22   */
23 #ifndef __ARCH_ARM_MACH_OMAP2_L3_INTERCONNECT_3XXX_H
24 #define __ARCH_ARM_MACH_OMAP2_L3_INTERCONNECT_3XXX_H
25 
26 /*
27  * L3 register offsets
28  */
29 #define L3_MODULES			3
30 #define CLEAR_STDERR_LOG		(1 << 31)
31 #define CUSTOM_ERROR			0x2
32 #define STANDARD_ERROR			0x0
33 #define INBAND_ERROR			0x0
34 #define EMIF_KERRLOG_OFFSET		0x10
35 #define L3_SLAVE_ADDRESS_OFFSET		0x14
36 #define LOGICAL_ADDR_ERRORLOG		0x4
37 #define L3_APPLICATION_ERROR		0x0
38 #define L3_DEBUG_ERROR			0x1
39 
40 u32 l3_flagmux[L3_MODULES] = {
41 	0x50C,
42 	0x100C,
43 	0X020C
44 };
45 
46 /*
47  * L3 Target standard Error register offsets
48  */
49 u32 l3_targ_stderrlog_main_clk1[] = {
50 	0x148, /* DMM1 */
51 	0x248, /* DMM2 */
52 	0x348, /* ABE */
53 	0x448, /* L4CFG */
54 	0x648  /* CLK2 PWR DISC */
55 };
56 
57 u32 l3_targ_stderrlog_main_clk2[] = {
58 	0x548,		/* CORTEX M3 */
59 	0x348,		/* DSS */
60 	0x148,		/* GPMC */
61 	0x448,		/* ISS */
62 	0x748,		/* IVAHD */
63 	0xD48,		/* missing in TRM  corresponds to AES1*/
64 	0x948,		/* L4 PER0*/
65 	0x248,		/* OCMRAM */
66 	0x148,		/* missing in TRM corresponds to GPMC sERROR*/
67 	0x648,		/* SGX */
68 	0x848,		/* SL2 */
69 	0x1648,		/* C2C */
70 	0x1148,		/* missing in TRM corresponds PWR DISC CLK1*/
71 	0xF48,		/* missing in TRM corrsponds to SHA1*/
72 	0xE48,		/* missing in TRM corresponds to AES2*/
73 	0xC48,		/* L4 PER3 */
74 	0xA48,		/* L4 PER1*/
75 	0xB48		/* L4 PER2*/
76 };
77 
78 u32 l3_targ_stderrlog_main_clk3[] = {
79 	0x0148	/* EMUSS */
80 };
81 
82 char *l3_targ_stderrlog_main_name[L3_MODULES][18] = {
83 	{
84 	"DMM1",
85 	"DMM2",
86 	"ABE",
87 	"L4CFG",
88 	"CLK2 PWR DISC",
89 	},
90 	{
91 	"CORTEX M3" ,
92 	"DSS ",
93 	"GPMC ",
94 	"ISS ",
95 	"IVAHD ",
96 	"AES1",
97 	"L4 PER0",
98 	"OCMRAM ",
99 	"GPMC sERROR",
100 	"SGX ",
101 	"SL2 ",
102 	"C2C ",
103 	"PWR DISC CLK1",
104 	"SHA1",
105 	"AES2",
106 	"L4 PER3",
107 	"L4 PER1",
108 	"L4 PER2",
109 	},
110 	{
111 	"EMUSS",
112 	},
113 };
114 
115 u32 *l3_targ[L3_MODULES] = {
116 	l3_targ_stderrlog_main_clk1,
117 	l3_targ_stderrlog_main_clk2,
118 	l3_targ_stderrlog_main_clk3,
119 };
120 
121 struct omap4_l3 {
122 	struct device	*dev;
123 	struct clk	*ick;
124 
125 	/* memory base */
126 	void __iomem *l3_base[4];
127 
128 	int		debug_irq;
129 	int		app_irq;
130 };
131 
132 #endif
133