1 /* 2 * arch/arm/mach-omap2/control.h 3 * 4 * OMAP2/3/4 System Control Module definitions 5 * 6 * Copyright (C) 2007-2010 Texas Instruments, Inc. 7 * Copyright (C) 2007-2008, 2010 Nokia Corporation 8 * 9 * Written by Paul Walmsley 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License as published by 13 * the Free Software Foundation. 14 */ 15 16 #ifndef __ARCH_ARM_MACH_OMAP2_CONTROL_H 17 #define __ARCH_ARM_MACH_OMAP2_CONTROL_H 18 19 #include <mach/io.h> 20 #include <mach/ctrl_module_core_44xx.h> 21 #include <mach/ctrl_module_wkup_44xx.h> 22 #include <mach/ctrl_module_pad_core_44xx.h> 23 #include <mach/ctrl_module_pad_wkup_44xx.h> 24 25 #ifndef __ASSEMBLY__ 26 #define OMAP242X_CTRL_REGADDR(reg) \ 27 OMAP2_L4_IO_ADDRESS(OMAP242X_CTRL_BASE + (reg)) 28 #define OMAP243X_CTRL_REGADDR(reg) \ 29 OMAP2_L4_IO_ADDRESS(OMAP243X_CTRL_BASE + (reg)) 30 #define OMAP343X_CTRL_REGADDR(reg) \ 31 OMAP2_L4_IO_ADDRESS(OMAP343X_CTRL_BASE + (reg)) 32 #else 33 #define OMAP242X_CTRL_REGADDR(reg) \ 34 OMAP2_L4_IO_ADDRESS(OMAP242X_CTRL_BASE + (reg)) 35 #define OMAP243X_CTRL_REGADDR(reg) \ 36 OMAP2_L4_IO_ADDRESS(OMAP243X_CTRL_BASE + (reg)) 37 #define OMAP343X_CTRL_REGADDR(reg) \ 38 OMAP2_L4_IO_ADDRESS(OMAP343X_CTRL_BASE + (reg)) 39 #endif /* __ASSEMBLY__ */ 40 41 /* 42 * As elsewhere, the "OMAP2_" prefix indicates that the macro is valid for 43 * OMAP24XX and OMAP34XX. 44 */ 45 46 /* Control submodule offsets */ 47 48 #define OMAP2_CONTROL_INTERFACE 0x000 49 #define OMAP2_CONTROL_PADCONFS 0x030 50 #define OMAP2_CONTROL_GENERAL 0x270 51 #define OMAP343X_CONTROL_MEM_WKUP 0x600 52 #define OMAP343X_CONTROL_PADCONFS_WKUP 0xa00 53 #define OMAP343X_CONTROL_GENERAL_WKUP 0xa60 54 55 /* TI816X spefic control submodules */ 56 #define TI816X_CONTROL_DEVCONF 0x600 57 58 /* Control register offsets - read/write with omap_ctrl_{read,write}{bwl}() */ 59 60 #define OMAP2_CONTROL_SYSCONFIG (OMAP2_CONTROL_INTERFACE + 0x10) 61 62 /* CONTROL_GENERAL register offsets common to OMAP2 & 3 */ 63 #define OMAP2_CONTROL_DEVCONF0 (OMAP2_CONTROL_GENERAL + 0x0004) 64 #define OMAP2_CONTROL_MSUSPENDMUX_0 (OMAP2_CONTROL_GENERAL + 0x0020) 65 #define OMAP2_CONTROL_MSUSPENDMUX_1 (OMAP2_CONTROL_GENERAL + 0x0024) 66 #define OMAP2_CONTROL_MSUSPENDMUX_2 (OMAP2_CONTROL_GENERAL + 0x0028) 67 #define OMAP2_CONTROL_MSUSPENDMUX_3 (OMAP2_CONTROL_GENERAL + 0x002c) 68 #define OMAP2_CONTROL_MSUSPENDMUX_4 (OMAP2_CONTROL_GENERAL + 0x0030) 69 #define OMAP2_CONTROL_MSUSPENDMUX_5 (OMAP2_CONTROL_GENERAL + 0x0034) 70 #define OMAP2_CONTROL_SEC_CTRL (OMAP2_CONTROL_GENERAL + 0x0040) 71 #define OMAP2_CONTROL_RPUB_KEY_H_0 (OMAP2_CONTROL_GENERAL + 0x0090) 72 #define OMAP2_CONTROL_RPUB_KEY_H_1 (OMAP2_CONTROL_GENERAL + 0x0094) 73 #define OMAP2_CONTROL_RPUB_KEY_H_2 (OMAP2_CONTROL_GENERAL + 0x0098) 74 #define OMAP2_CONTROL_RPUB_KEY_H_3 (OMAP2_CONTROL_GENERAL + 0x009c) 75 76 /* 242x-only CONTROL_GENERAL register offsets */ 77 #define OMAP242X_CONTROL_DEVCONF OMAP2_CONTROL_DEVCONF0 /* match TRM */ 78 #define OMAP242X_CONTROL_OCM_RAM_PERM (OMAP2_CONTROL_GENERAL + 0x0068) 79 80 /* 243x-only CONTROL_GENERAL register offsets */ 81 /* CONTROL_IVA2_BOOT{ADDR,MOD} are at the same place on 343x - noted below */ 82 #define OMAP243X_CONTROL_DEVCONF1 (OMAP2_CONTROL_GENERAL + 0x0078) 83 #define OMAP243X_CONTROL_CSIRXFE (OMAP2_CONTROL_GENERAL + 0x007c) 84 #define OMAP243X_CONTROL_IVA2_BOOTADDR (OMAP2_CONTROL_GENERAL + 0x0190) 85 #define OMAP243X_CONTROL_IVA2_BOOTMOD (OMAP2_CONTROL_GENERAL + 0x0194) 86 #define OMAP243X_CONTROL_IVA2_GEMCFG (OMAP2_CONTROL_GENERAL + 0x0198) 87 #define OMAP243X_CONTROL_PBIAS_LITE (OMAP2_CONTROL_GENERAL + 0x0230) 88 89 /* 24xx-only CONTROL_GENERAL register offsets */ 90 #define OMAP24XX_CONTROL_DEBOBS (OMAP2_CONTROL_GENERAL + 0x0000) 91 #define OMAP24XX_CONTROL_EMU_SUPPORT (OMAP2_CONTROL_GENERAL + 0x0008) 92 #define OMAP24XX_CONTROL_SEC_TEST (OMAP2_CONTROL_GENERAL + 0x0044) 93 #define OMAP24XX_CONTROL_PSA_CTRL (OMAP2_CONTROL_GENERAL + 0x0048) 94 #define OMAP24XX_CONTROL_PSA_CMD (OMAP2_CONTROL_GENERAL + 0x004c) 95 #define OMAP24XX_CONTROL_PSA_VALUE (OMAP2_CONTROL_GENERAL + 0x0050) 96 #define OMAP24XX_CONTROL_SEC_EMU (OMAP2_CONTROL_GENERAL + 0x0060) 97 #define OMAP24XX_CONTROL_SEC_TAP (OMAP2_CONTROL_GENERAL + 0x0064) 98 #define OMAP24XX_CONTROL_OCM_PUB_RAM_ADD (OMAP2_CONTROL_GENERAL + 0x006c) 99 #define OMAP24XX_CONTROL_EXT_SEC_RAM_START_ADD (OMAP2_CONTROL_GENERAL + 0x0070) 100 #define OMAP24XX_CONTROL_EXT_SEC_RAM_STOP_ADD (OMAP2_CONTROL_GENERAL + 0x0074) 101 #define OMAP24XX_CONTROL_SEC_STATUS (OMAP2_CONTROL_GENERAL + 0x0080) 102 #define OMAP24XX_CONTROL_SEC_ERR_STATUS (OMAP2_CONTROL_GENERAL + 0x0084) 103 #define OMAP24XX_CONTROL_STATUS (OMAP2_CONTROL_GENERAL + 0x0088) 104 #define OMAP24XX_CONTROL_GENERAL_PURPOSE_STATUS (OMAP2_CONTROL_GENERAL + 0x008c) 105 #define OMAP24XX_CONTROL_RAND_KEY_0 (OMAP2_CONTROL_GENERAL + 0x00a0) 106 #define OMAP24XX_CONTROL_RAND_KEY_1 (OMAP2_CONTROL_GENERAL + 0x00a4) 107 #define OMAP24XX_CONTROL_RAND_KEY_2 (OMAP2_CONTROL_GENERAL + 0x00a8) 108 #define OMAP24XX_CONTROL_RAND_KEY_3 (OMAP2_CONTROL_GENERAL + 0x00ac) 109 #define OMAP24XX_CONTROL_CUST_KEY_0 (OMAP2_CONTROL_GENERAL + 0x00b0) 110 #define OMAP24XX_CONTROL_CUST_KEY_1 (OMAP2_CONTROL_GENERAL + 0x00b4) 111 #define OMAP24XX_CONTROL_TEST_KEY_0 (OMAP2_CONTROL_GENERAL + 0x00c0) 112 #define OMAP24XX_CONTROL_TEST_KEY_1 (OMAP2_CONTROL_GENERAL + 0x00c4) 113 #define OMAP24XX_CONTROL_TEST_KEY_2 (OMAP2_CONTROL_GENERAL + 0x00c8) 114 #define OMAP24XX_CONTROL_TEST_KEY_3 (OMAP2_CONTROL_GENERAL + 0x00cc) 115 #define OMAP24XX_CONTROL_TEST_KEY_4 (OMAP2_CONTROL_GENERAL + 0x00d0) 116 #define OMAP24XX_CONTROL_TEST_KEY_5 (OMAP2_CONTROL_GENERAL + 0x00d4) 117 #define OMAP24XX_CONTROL_TEST_KEY_6 (OMAP2_CONTROL_GENERAL + 0x00d8) 118 #define OMAP24XX_CONTROL_TEST_KEY_7 (OMAP2_CONTROL_GENERAL + 0x00dc) 119 #define OMAP24XX_CONTROL_TEST_KEY_8 (OMAP2_CONTROL_GENERAL + 0x00e0) 120 #define OMAP24XX_CONTROL_TEST_KEY_9 (OMAP2_CONTROL_GENERAL + 0x00e4) 121 122 #define OMAP343X_CONTROL_PADCONF_SYSNIRQ (OMAP2_CONTROL_INTERFACE + 0x01b0) 123 124 /* 34xx-only CONTROL_GENERAL register offsets */ 125 #define OMAP343X_CONTROL_PADCONF_OFF (OMAP2_CONTROL_GENERAL + 0x0000) 126 #define OMAP343X_CONTROL_MEM_DFTRW0 (OMAP2_CONTROL_GENERAL + 0x0008) 127 #define OMAP343X_CONTROL_MEM_DFTRW1 (OMAP2_CONTROL_GENERAL + 0x000c) 128 #define OMAP343X_CONTROL_DEVCONF1 (OMAP2_CONTROL_GENERAL + 0x0068) 129 #define OMAP343X_CONTROL_CSIRXFE (OMAP2_CONTROL_GENERAL + 0x006c) 130 #define OMAP343X_CONTROL_SEC_STATUS (OMAP2_CONTROL_GENERAL + 0x0070) 131 #define OMAP343X_CONTROL_SEC_ERR_STATUS (OMAP2_CONTROL_GENERAL + 0x0074) 132 #define OMAP343X_CONTROL_SEC_ERR_STATUS_DEBUG (OMAP2_CONTROL_GENERAL + 0x0078) 133 #define OMAP343X_CONTROL_STATUS (OMAP2_CONTROL_GENERAL + 0x0080) 134 #define OMAP343X_CONTROL_GENERAL_PURPOSE_STATUS (OMAP2_CONTROL_GENERAL + 0x0084) 135 #define OMAP343X_CONTROL_RPUB_KEY_H_4 (OMAP2_CONTROL_GENERAL + 0x00a0) 136 #define OMAP343X_CONTROL_RAND_KEY_0 (OMAP2_CONTROL_GENERAL + 0x00a8) 137 #define OMAP343X_CONTROL_RAND_KEY_1 (OMAP2_CONTROL_GENERAL + 0x00ac) 138 #define OMAP343X_CONTROL_RAND_KEY_2 (OMAP2_CONTROL_GENERAL + 0x00b0) 139 #define OMAP343X_CONTROL_RAND_KEY_3 (OMAP2_CONTROL_GENERAL + 0x00b4) 140 #define OMAP343X_CONTROL_TEST_KEY_0 (OMAP2_CONTROL_GENERAL + 0x00c8) 141 #define OMAP343X_CONTROL_TEST_KEY_1 (OMAP2_CONTROL_GENERAL + 0x00cc) 142 #define OMAP343X_CONTROL_TEST_KEY_2 (OMAP2_CONTROL_GENERAL + 0x00d0) 143 #define OMAP343X_CONTROL_TEST_KEY_3 (OMAP2_CONTROL_GENERAL + 0x00d4) 144 #define OMAP343X_CONTROL_TEST_KEY_4 (OMAP2_CONTROL_GENERAL + 0x00d8) 145 #define OMAP343X_CONTROL_TEST_KEY_5 (OMAP2_CONTROL_GENERAL + 0x00dc) 146 #define OMAP343X_CONTROL_TEST_KEY_6 (OMAP2_CONTROL_GENERAL + 0x00e0) 147 #define OMAP343X_CONTROL_TEST_KEY_7 (OMAP2_CONTROL_GENERAL + 0x00e4) 148 #define OMAP343X_CONTROL_TEST_KEY_8 (OMAP2_CONTROL_GENERAL + 0x00e8) 149 #define OMAP343X_CONTROL_TEST_KEY_9 (OMAP2_CONTROL_GENERAL + 0x00ec) 150 #define OMAP343X_CONTROL_TEST_KEY_10 (OMAP2_CONTROL_GENERAL + 0x00f0) 151 #define OMAP343X_CONTROL_TEST_KEY_11 (OMAP2_CONTROL_GENERAL + 0x00f4) 152 #define OMAP343X_CONTROL_TEST_KEY_12 (OMAP2_CONTROL_GENERAL + 0x00f8) 153 #define OMAP343X_CONTROL_TEST_KEY_13 (OMAP2_CONTROL_GENERAL + 0x00fc) 154 #define OMAP343X_CONTROL_FUSE_OPP1_VDD1 (OMAP2_CONTROL_GENERAL + 0x0110) 155 #define OMAP343X_CONTROL_FUSE_OPP2_VDD1 (OMAP2_CONTROL_GENERAL + 0x0114) 156 #define OMAP343X_CONTROL_FUSE_OPP3_VDD1 (OMAP2_CONTROL_GENERAL + 0x0118) 157 #define OMAP343X_CONTROL_FUSE_OPP4_VDD1 (OMAP2_CONTROL_GENERAL + 0x011c) 158 #define OMAP343X_CONTROL_FUSE_OPP5_VDD1 (OMAP2_CONTROL_GENERAL + 0x0120) 159 #define OMAP343X_CONTROL_FUSE_OPP1_VDD2 (OMAP2_CONTROL_GENERAL + 0x0124) 160 #define OMAP343X_CONTROL_FUSE_OPP2_VDD2 (OMAP2_CONTROL_GENERAL + 0x0128) 161 #define OMAP343X_CONTROL_FUSE_OPP3_VDD2 (OMAP2_CONTROL_GENERAL + 0x012c) 162 #define OMAP343X_CONTROL_FUSE_SR (OMAP2_CONTROL_GENERAL + 0x0130) 163 #define OMAP343X_CONTROL_IVA2_BOOTADDR (OMAP2_CONTROL_GENERAL + 0x0190) 164 #define OMAP343X_CONTROL_IVA2_BOOTMOD (OMAP2_CONTROL_GENERAL + 0x0194) 165 #define OMAP343X_CONTROL_DEBOBS(i) (OMAP2_CONTROL_GENERAL + 0x01B0 \ 166 + ((i) >> 1) * 4 + (!((i) & 1)) * 2) 167 #define OMAP343X_CONTROL_PROG_IO0 (OMAP2_CONTROL_GENERAL + 0x01D4) 168 #define OMAP343X_CONTROL_PROG_IO1 (OMAP2_CONTROL_GENERAL + 0x01D8) 169 #define OMAP343X_CONTROL_DSS_DPLL_SPREADING (OMAP2_CONTROL_GENERAL + 0x01E0) 170 #define OMAP343X_CONTROL_CORE_DPLL_SPREADING (OMAP2_CONTROL_GENERAL + 0x01E4) 171 #define OMAP343X_CONTROL_PER_DPLL_SPREADING (OMAP2_CONTROL_GENERAL + 0x01E8) 172 #define OMAP343X_CONTROL_USBHOST_DPLL_SPREADING (OMAP2_CONTROL_GENERAL + 0x01EC) 173 #define OMAP343X_CONTROL_PBIAS_LITE (OMAP2_CONTROL_GENERAL + 0x02B0) 174 #define OMAP343X_CONTROL_TEMP_SENSOR (OMAP2_CONTROL_GENERAL + 0x02B4) 175 #define OMAP343X_CONTROL_SRAMLDO4 (OMAP2_CONTROL_GENERAL + 0x02B8) 176 #define OMAP343X_CONTROL_SRAMLDO5 (OMAP2_CONTROL_GENERAL + 0x02C0) 177 #define OMAP343X_CONTROL_CSI (OMAP2_CONTROL_GENERAL + 0x02C4) 178 179 /* OMAP3630 only CONTROL_GENERAL register offsets */ 180 #define OMAP3630_CONTROL_FUSE_OPP1G_VDD1 (OMAP2_CONTROL_GENERAL + 0x0110) 181 #define OMAP3630_CONTROL_FUSE_OPP50_VDD1 (OMAP2_CONTROL_GENERAL + 0x0114) 182 #define OMAP3630_CONTROL_FUSE_OPP100_VDD1 (OMAP2_CONTROL_GENERAL + 0x0118) 183 #define OMAP3630_CONTROL_FUSE_OPP120_VDD1 (OMAP2_CONTROL_GENERAL + 0x0120) 184 #define OMAP3630_CONTROL_FUSE_OPP50_VDD2 (OMAP2_CONTROL_GENERAL + 0x0128) 185 #define OMAP3630_CONTROL_FUSE_OPP100_VDD2 (OMAP2_CONTROL_GENERAL + 0x012C) 186 187 /* OMAP44xx control efuse offsets */ 188 #define OMAP44XX_CONTROL_FUSE_IVA_OPP50 0x22C 189 #define OMAP44XX_CONTROL_FUSE_IVA_OPP100 0x22F 190 #define OMAP44XX_CONTROL_FUSE_IVA_OPPTURBO 0x232 191 #define OMAP44XX_CONTROL_FUSE_IVA_OPPNITRO 0x235 192 #define OMAP44XX_CONTROL_FUSE_MPU_OPP50 0x240 193 #define OMAP44XX_CONTROL_FUSE_MPU_OPP100 0x243 194 #define OMAP44XX_CONTROL_FUSE_MPU_OPPTURBO 0x246 195 #define OMAP44XX_CONTROL_FUSE_MPU_OPPNITRO 0x249 196 #define OMAP44XX_CONTROL_FUSE_CORE_OPP50 0x254 197 #define OMAP44XX_CONTROL_FUSE_CORE_OPP100 0x257 198 199 /* AM35XX only CONTROL_GENERAL register offsets */ 200 #define AM35XX_CONTROL_MSUSPENDMUX_6 (OMAP2_CONTROL_GENERAL + 0x0038) 201 #define AM35XX_CONTROL_DEVCONF2 (OMAP2_CONTROL_GENERAL + 0x0310) 202 #define AM35XX_CONTROL_DEVCONF3 (OMAP2_CONTROL_GENERAL + 0x0314) 203 #define AM35XX_CONTROL_CBA_PRIORITY (OMAP2_CONTROL_GENERAL + 0x0320) 204 #define AM35XX_CONTROL_LVL_INTR_CLEAR (OMAP2_CONTROL_GENERAL + 0x0324) 205 #define AM35XX_CONTROL_IP_SW_RESET (OMAP2_CONTROL_GENERAL + 0x0328) 206 #define AM35XX_CONTROL_IPSS_CLK_CTRL (OMAP2_CONTROL_GENERAL + 0x032C) 207 208 /* 34xx PADCONF register offsets */ 209 #define OMAP343X_PADCONF_ETK(i) (OMAP2_CONTROL_PADCONFS + 0x5a8 + \ 210 (i)*2) 211 #define OMAP343X_PADCONF_ETK_CLK OMAP343X_PADCONF_ETK(0) 212 #define OMAP343X_PADCONF_ETK_CTL OMAP343X_PADCONF_ETK(1) 213 #define OMAP343X_PADCONF_ETK_D0 OMAP343X_PADCONF_ETK(2) 214 #define OMAP343X_PADCONF_ETK_D1 OMAP343X_PADCONF_ETK(3) 215 #define OMAP343X_PADCONF_ETK_D2 OMAP343X_PADCONF_ETK(4) 216 #define OMAP343X_PADCONF_ETK_D3 OMAP343X_PADCONF_ETK(5) 217 #define OMAP343X_PADCONF_ETK_D4 OMAP343X_PADCONF_ETK(6) 218 #define OMAP343X_PADCONF_ETK_D5 OMAP343X_PADCONF_ETK(7) 219 #define OMAP343X_PADCONF_ETK_D6 OMAP343X_PADCONF_ETK(8) 220 #define OMAP343X_PADCONF_ETK_D7 OMAP343X_PADCONF_ETK(9) 221 #define OMAP343X_PADCONF_ETK_D8 OMAP343X_PADCONF_ETK(10) 222 #define OMAP343X_PADCONF_ETK_D9 OMAP343X_PADCONF_ETK(11) 223 #define OMAP343X_PADCONF_ETK_D10 OMAP343X_PADCONF_ETK(12) 224 #define OMAP343X_PADCONF_ETK_D11 OMAP343X_PADCONF_ETK(13) 225 #define OMAP343X_PADCONF_ETK_D12 OMAP343X_PADCONF_ETK(14) 226 #define OMAP343X_PADCONF_ETK_D13 OMAP343X_PADCONF_ETK(15) 227 #define OMAP343X_PADCONF_ETK_D14 OMAP343X_PADCONF_ETK(16) 228 #define OMAP343X_PADCONF_ETK_D15 OMAP343X_PADCONF_ETK(17) 229 230 /* 34xx GENERAL_WKUP regist offsets */ 231 #define OMAP343X_CONTROL_WKUP_DEBOBSMUX(i) (OMAP343X_CONTROL_GENERAL_WKUP + \ 232 0x008 + (i)) 233 #define OMAP343X_CONTROL_WKUP_DEBOBS0 (OMAP343X_CONTROL_GENERAL_WKUP + 0x008) 234 #define OMAP343X_CONTROL_WKUP_DEBOBS1 (OMAP343X_CONTROL_GENERAL_WKUP + 0x00C) 235 #define OMAP343X_CONTROL_WKUP_DEBOBS2 (OMAP343X_CONTROL_GENERAL_WKUP + 0x010) 236 #define OMAP343X_CONTROL_WKUP_DEBOBS3 (OMAP343X_CONTROL_GENERAL_WKUP + 0x014) 237 #define OMAP343X_CONTROL_WKUP_DEBOBS4 (OMAP343X_CONTROL_GENERAL_WKUP + 0x018) 238 239 /* 36xx-only RTA - Retention till Accesss control registers and bits */ 240 #define OMAP36XX_CONTROL_MEM_RTA_CTRL 0x40C 241 #define OMAP36XX_RTA_DISABLE 0x0 242 243 /* 34xx D2D idle-related pins, handled by PM core */ 244 #define OMAP3_PADCONF_SAD2D_MSTANDBY 0x250 245 #define OMAP3_PADCONF_SAD2D_IDLEACK 0x254 246 247 /* TI816X CONTROL_DEVCONF register offsets */ 248 #define TI816X_CONTROL_DEVICE_ID (TI816X_CONTROL_DEVCONF + 0x000) 249 250 /* 251 * REVISIT: This list of registers is not comprehensive - there are more 252 * that should be added. 253 */ 254 255 /* 256 * Control module register bit defines - these should eventually go into 257 * their own regbits file. Some of these will be complicated, depending 258 * on the device type (general-purpose, emulator, test, secure, bad, other) 259 * and the security mode (secure, non-secure, don't care) 260 */ 261 /* CONTROL_DEVCONF0 bits */ 262 #define OMAP2_MMCSDIO1ADPCLKISEL (1 << 24) /* MMC1 loop back clock */ 263 #define OMAP24XX_USBSTANDBYCTRL (1 << 15) 264 #define OMAP2_MCBSP2_CLKS_MASK (1 << 6) 265 #define OMAP2_MCBSP1_FSR_MASK (1 << 4) 266 #define OMAP2_MCBSP1_CLKR_MASK (1 << 3) 267 #define OMAP2_MCBSP1_CLKS_MASK (1 << 2) 268 269 /* CONTROL_DEVCONF1 bits */ 270 #define OMAP243X_MMC1_ACTIVE_OVERWRITE (1 << 31) 271 #define OMAP2_MMCSDIO2ADPCLKISEL (1 << 6) /* MMC2 loop back clock */ 272 #define OMAP2_MCBSP5_CLKS_MASK (1 << 4) /* > 242x */ 273 #define OMAP2_MCBSP4_CLKS_MASK (1 << 2) /* > 242x */ 274 #define OMAP2_MCBSP3_CLKS_MASK (1 << 0) /* > 242x */ 275 276 /* CONTROL_STATUS bits */ 277 #define OMAP2_DEVICETYPE_MASK (0x7 << 8) 278 #define OMAP2_SYSBOOT_5_MASK (1 << 5) 279 #define OMAP2_SYSBOOT_4_MASK (1 << 4) 280 #define OMAP2_SYSBOOT_3_MASK (1 << 3) 281 #define OMAP2_SYSBOOT_2_MASK (1 << 2) 282 #define OMAP2_SYSBOOT_1_MASK (1 << 1) 283 #define OMAP2_SYSBOOT_0_MASK (1 << 0) 284 285 /* CONTROL_PBIAS_LITE bits */ 286 #define OMAP343X_PBIASLITESUPPLY_HIGH1 (1 << 15) 287 #define OMAP343X_PBIASLITEVMODEERROR1 (1 << 11) 288 #define OMAP343X_PBIASSPEEDCTRL1 (1 << 10) 289 #define OMAP343X_PBIASLITEPWRDNZ1 (1 << 9) 290 #define OMAP343X_PBIASLITEVMODE1 (1 << 8) 291 #define OMAP343X_PBIASLITESUPPLY_HIGH0 (1 << 7) 292 #define OMAP343X_PBIASLITEVMODEERROR0 (1 << 3) 293 #define OMAP2_PBIASSPEEDCTRL0 (1 << 2) 294 #define OMAP2_PBIASLITEPWRDNZ0 (1 << 1) 295 #define OMAP2_PBIASLITEVMODE0 (1 << 0) 296 297 /* CONTROL_PROG_IO1 bits */ 298 #define OMAP3630_PRG_SDMMC1_SPEEDCTRL (1 << 20) 299 300 /* CONTROL_IVA2_BOOTMOD bits */ 301 #define OMAP3_IVA2_BOOTMOD_SHIFT 0 302 #define OMAP3_IVA2_BOOTMOD_MASK (0xf << 0) 303 #define OMAP3_IVA2_BOOTMOD_IDLE (0x1 << 0) 304 305 /* CONTROL_PADCONF_X bits */ 306 #define OMAP3_PADCONF_WAKEUPEVENT0 (1 << 15) 307 #define OMAP3_PADCONF_WAKEUPENABLE0 (1 << 14) 308 309 #define OMAP343X_SCRATCHPAD_ROM (OMAP343X_CTRL_BASE + 0x860) 310 #define OMAP343X_SCRATCHPAD (OMAP343X_CTRL_BASE + 0x910) 311 #define OMAP343X_SCRATCHPAD_ROM_OFFSET 0x19C 312 #define OMAP343X_SCRATCHPAD_REGADDR(reg) OMAP2_L4_IO_ADDRESS(\ 313 OMAP343X_SCRATCHPAD + reg) 314 315 /* AM35XX_CONTROL_IPSS_CLK_CTRL bits */ 316 #define AM35XX_USBOTG_VBUSP_CLK_SHIFT 0 317 #define AM35XX_CPGMAC_VBUSP_CLK_SHIFT 1 318 #define AM35XX_VPFE_VBUSP_CLK_SHIFT 2 319 #define AM35XX_HECC_VBUSP_CLK_SHIFT 3 320 #define AM35XX_USBOTG_FCLK_SHIFT 8 321 #define AM35XX_CPGMAC_FCLK_SHIFT 9 322 #define AM35XX_VPFE_FCLK_SHIFT 10 323 324 /*AM35XX CONTROL_LVL_INTR_CLEAR bits*/ 325 #define AM35XX_CPGMAC_C0_MISC_PULSE_CLR BIT(0) 326 #define AM35XX_CPGMAC_C0_RX_PULSE_CLR BIT(1) 327 #define AM35XX_CPGMAC_C0_RX_THRESH_CLR BIT(2) 328 #define AM35XX_CPGMAC_C0_TX_PULSE_CLR BIT(3) 329 #define AM35XX_USBOTGSS_INT_CLR BIT(4) 330 #define AM35XX_VPFE_CCDC_VD0_INT_CLR BIT(5) 331 #define AM35XX_VPFE_CCDC_VD1_INT_CLR BIT(6) 332 #define AM35XX_VPFE_CCDC_VD2_INT_CLR BIT(7) 333 334 /*AM35XX CONTROL_IP_SW_RESET bits*/ 335 #define AM35XX_USBOTGSS_SW_RST BIT(0) 336 #define AM35XX_CPGMACSS_SW_RST BIT(1) 337 #define AM35XX_VPFE_VBUSP_SW_RST BIT(2) 338 #define AM35XX_HECC_SW_RST BIT(3) 339 #define AM35XX_VPFE_PCLK_SW_RST BIT(4) 340 341 /* 342 * CONTROL OMAP STATUS register to identify OMAP3 features 343 */ 344 #define OMAP3_CONTROL_OMAP_STATUS 0x044c 345 346 #define OMAP3_SGX_SHIFT 13 347 #define OMAP3_SGX_MASK (3 << OMAP3_SGX_SHIFT) 348 #define FEAT_SGX_FULL 0 349 #define FEAT_SGX_HALF 1 350 #define FEAT_SGX_NONE 2 351 352 #define OMAP3_IVA_SHIFT 12 353 #define OMAP3_IVA_MASK (1 << OMAP3_IVA_SHIFT) 354 #define FEAT_IVA 0 355 #define FEAT_IVA_NONE 1 356 357 #define OMAP3_L2CACHE_SHIFT 10 358 #define OMAP3_L2CACHE_MASK (3 << OMAP3_L2CACHE_SHIFT) 359 #define FEAT_L2CACHE_NONE 0 360 #define FEAT_L2CACHE_64KB 1 361 #define FEAT_L2CACHE_128KB 2 362 #define FEAT_L2CACHE_256KB 3 363 364 #define OMAP3_ISP_SHIFT 5 365 #define OMAP3_ISP_MASK (1 << OMAP3_ISP_SHIFT) 366 #define FEAT_ISP 0 367 #define FEAT_ISP_NONE 1 368 369 #define OMAP3_NEON_SHIFT 4 370 #define OMAP3_NEON_MASK (1 << OMAP3_NEON_SHIFT) 371 #define FEAT_NEON 0 372 #define FEAT_NEON_NONE 1 373 374 375 #ifndef __ASSEMBLY__ 376 #ifdef CONFIG_ARCH_OMAP2PLUS 377 extern void __iomem *omap_ctrl_base_get(void); 378 extern u8 omap_ctrl_readb(u16 offset); 379 extern u16 omap_ctrl_readw(u16 offset); 380 extern u32 omap_ctrl_readl(u16 offset); 381 extern u32 omap4_ctrl_pad_readl(u16 offset); 382 extern void omap_ctrl_writeb(u8 val, u16 offset); 383 extern void omap_ctrl_writew(u16 val, u16 offset); 384 extern void omap_ctrl_writel(u32 val, u16 offset); 385 extern void omap4_ctrl_pad_writel(u32 val, u16 offset); 386 387 extern void omap3_save_scratchpad_contents(void); 388 extern void omap3_clear_scratchpad_contents(void); 389 extern u32 *get_restore_pointer(void); 390 extern u32 *get_es3_restore_pointer(void); 391 extern u32 *get_omap3630_restore_pointer(void); 392 extern u32 omap3_arm_context[128]; 393 extern void omap3_control_save_context(void); 394 extern void omap3_control_restore_context(void); 395 extern void omap3_ctrl_write_boot_mode(u8 bootmode); 396 extern void omap3630_ctrl_disable_rta(void); 397 extern int omap3_ctrl_save_padconf(void); 398 #else 399 #define omap_ctrl_base_get() 0 400 #define omap_ctrl_readb(x) 0 401 #define omap_ctrl_readw(x) 0 402 #define omap_ctrl_readl(x) 0 403 #define omap4_ctrl_pad_readl(x) 0 404 #define omap_ctrl_writeb(x, y) WARN_ON(1) 405 #define omap_ctrl_writew(x, y) WARN_ON(1) 406 #define omap_ctrl_writel(x, y) WARN_ON(1) 407 #define omap4_ctrl_pad_writel(x, y) WARN_ON(1) 408 #endif 409 #endif /* __ASSEMBLY__ */ 410 411 #endif /* __ARCH_ARM_MACH_OMAP2_CONTROL_H */ 412 413