1 /* 2 * OMAP44xx Clock Management register bits 3 * 4 * Copyright (C) 2009-2010 Texas Instruments, Inc. 5 * Copyright (C) 2009-2010 Nokia Corporation 6 * 7 * Paul Walmsley (paul@pwsan.com) 8 * Rajendra Nayak (rnayak@ti.com) 9 * Benoit Cousson (b-cousson@ti.com) 10 * 11 * This file is automatically generated from the OMAP hardware databases. 12 * We respectfully ask that any modifications to this file be coordinated 13 * with the public linux-omap@vger.kernel.org mailing list and the 14 * authors above to ensure that the autogeneration scripts are kept 15 * up-to-date with the file contents. 16 * 17 * This program is free software; you can redistribute it and/or modify 18 * it under the terms of the GNU General Public License version 2 as 19 * published by the Free Software Foundation. 20 */ 21 22 #ifndef __ARCH_ARM_MACH_OMAP2_CM_REGBITS_44XX_H 23 #define __ARCH_ARM_MACH_OMAP2_CM_REGBITS_44XX_H 24 25 /* 26 * Used by CM_L3_1_DYNAMICDEP, CM_L3_1_DYNAMICDEP_RESTORE, CM_MPU_DYNAMICDEP, 27 * CM_TESLA_DYNAMICDEP 28 */ 29 #define OMAP4430_ABE_DYNDEP_SHIFT 3 30 #define OMAP4430_ABE_DYNDEP_MASK (1 << 3) 31 32 /* 33 * Used by CM_D2D_STATICDEP, CM_D2D_STATICDEP_RESTORE, CM_DUCATI_STATICDEP, 34 * CM_L3INIT_STATICDEP, CM_MPU_STATICDEP, CM_SDMA_STATICDEP, 35 * CM_SDMA_STATICDEP_RESTORE, CM_TESLA_STATICDEP 36 */ 37 #define OMAP4430_ABE_STATDEP_SHIFT 3 38 #define OMAP4430_ABE_STATDEP_MASK (1 << 3) 39 40 /* Used by CM_L4CFG_DYNAMICDEP, CM_L4CFG_DYNAMICDEP_RESTORE */ 41 #define OMAP4430_ALWONCORE_DYNDEP_SHIFT 16 42 #define OMAP4430_ALWONCORE_DYNDEP_MASK (1 << 16) 43 44 /* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP, CM_TESLA_STATICDEP */ 45 #define OMAP4430_ALWONCORE_STATDEP_SHIFT 16 46 #define OMAP4430_ALWONCORE_STATDEP_MASK (1 << 16) 47 48 /* 49 * Used by CM_AUTOIDLE_DPLL_ABE, CM_AUTOIDLE_DPLL_CORE, 50 * CM_AUTOIDLE_DPLL_CORE_RESTORE, CM_AUTOIDLE_DPLL_DDRPHY, 51 * CM_AUTOIDLE_DPLL_IVA, CM_AUTOIDLE_DPLL_MPU, CM_AUTOIDLE_DPLL_PER, 52 * CM_AUTOIDLE_DPLL_UNIPRO, CM_AUTOIDLE_DPLL_USB 53 */ 54 #define OMAP4430_AUTO_DPLL_MODE_SHIFT 0 55 #define OMAP4430_AUTO_DPLL_MODE_MASK (0x7 << 0) 56 57 /* Used by CM_L4CFG_DYNAMICDEP, CM_L4CFG_DYNAMICDEP_RESTORE */ 58 #define OMAP4430_CEFUSE_DYNDEP_SHIFT 17 59 #define OMAP4430_CEFUSE_DYNDEP_MASK (1 << 17) 60 61 /* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP, CM_TESLA_STATICDEP */ 62 #define OMAP4430_CEFUSE_STATDEP_SHIFT 17 63 #define OMAP4430_CEFUSE_STATDEP_MASK (1 << 17) 64 65 /* Used by CM1_ABE_CLKSTCTRL */ 66 #define OMAP4430_CLKACTIVITY_ABE_24M_GFCLK_SHIFT 13 67 #define OMAP4430_CLKACTIVITY_ABE_24M_GFCLK_MASK (1 << 13) 68 69 /* Used by CM1_ABE_CLKSTCTRL */ 70 #define OMAP4430_CLKACTIVITY_ABE_ALWON_32K_CLK_SHIFT 12 71 #define OMAP4430_CLKACTIVITY_ABE_ALWON_32K_CLK_MASK (1 << 12) 72 73 /* Used by CM_WKUP_CLKSTCTRL */ 74 #define OMAP4430_CLKACTIVITY_ABE_LP_CLK_SHIFT 9 75 #define OMAP4430_CLKACTIVITY_ABE_LP_CLK_MASK (1 << 9) 76 77 /* Used by CM1_ABE_CLKSTCTRL */ 78 #define OMAP4430_CLKACTIVITY_ABE_SYSCLK_SHIFT 11 79 #define OMAP4430_CLKACTIVITY_ABE_SYSCLK_MASK (1 << 11) 80 81 /* Used by CM1_ABE_CLKSTCTRL */ 82 #define OMAP4430_CLKACTIVITY_ABE_X2_CLK_SHIFT 8 83 #define OMAP4430_CLKACTIVITY_ABE_X2_CLK_MASK (1 << 8) 84 85 /* Used by CM_MEMIF_CLKSTCTRL, CM_MEMIF_CLKSTCTRL_RESTORE */ 86 #define OMAP4430_CLKACTIVITY_ASYNC_DLL_CLK_SHIFT 11 87 #define OMAP4430_CLKACTIVITY_ASYNC_DLL_CLK_MASK (1 << 11) 88 89 /* Used by CM_MEMIF_CLKSTCTRL, CM_MEMIF_CLKSTCTRL_RESTORE */ 90 #define OMAP4430_CLKACTIVITY_ASYNC_PHY1_CLK_SHIFT 12 91 #define OMAP4430_CLKACTIVITY_ASYNC_PHY1_CLK_MASK (1 << 12) 92 93 /* Used by CM_MEMIF_CLKSTCTRL, CM_MEMIF_CLKSTCTRL_RESTORE */ 94 #define OMAP4430_CLKACTIVITY_ASYNC_PHY2_CLK_SHIFT 13 95 #define OMAP4430_CLKACTIVITY_ASYNC_PHY2_CLK_MASK (1 << 13) 96 97 /* Used by CM_CAM_CLKSTCTRL */ 98 #define OMAP4430_CLKACTIVITY_CAM_PHY_CTRL_GCLK_SHIFT 9 99 #define OMAP4430_CLKACTIVITY_CAM_PHY_CTRL_GCLK_MASK (1 << 9) 100 101 /* Used by CM_ALWON_CLKSTCTRL */ 102 #define OMAP4430_CLKACTIVITY_CORE_ALWON_32K_GFCLK_SHIFT 12 103 #define OMAP4430_CLKACTIVITY_CORE_ALWON_32K_GFCLK_MASK (1 << 12) 104 105 /* Used by CM_EMU_CLKSTCTRL */ 106 #define OMAP4430_CLKACTIVITY_CORE_DPLL_EMU_CLK_SHIFT 9 107 #define OMAP4430_CLKACTIVITY_CORE_DPLL_EMU_CLK_MASK (1 << 9) 108 109 /* Used by CM_CEFUSE_CLKSTCTRL */ 110 #define OMAP4430_CLKACTIVITY_CUST_EFUSE_SYS_CLK_SHIFT 9 111 #define OMAP4430_CLKACTIVITY_CUST_EFUSE_SYS_CLK_MASK (1 << 9) 112 113 /* Used by CM_MEMIF_CLKSTCTRL, CM_MEMIF_CLKSTCTRL_RESTORE */ 114 #define OMAP4430_CLKACTIVITY_DLL_CLK_SHIFT 9 115 #define OMAP4430_CLKACTIVITY_DLL_CLK_MASK (1 << 9) 116 117 /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ 118 #define OMAP4430_CLKACTIVITY_DMT10_GFCLK_SHIFT 9 119 #define OMAP4430_CLKACTIVITY_DMT10_GFCLK_MASK (1 << 9) 120 121 /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ 122 #define OMAP4430_CLKACTIVITY_DMT11_GFCLK_SHIFT 10 123 #define OMAP4430_CLKACTIVITY_DMT11_GFCLK_MASK (1 << 10) 124 125 /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ 126 #define OMAP4430_CLKACTIVITY_DMT2_GFCLK_SHIFT 11 127 #define OMAP4430_CLKACTIVITY_DMT2_GFCLK_MASK (1 << 11) 128 129 /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ 130 #define OMAP4430_CLKACTIVITY_DMT3_GFCLK_SHIFT 12 131 #define OMAP4430_CLKACTIVITY_DMT3_GFCLK_MASK (1 << 12) 132 133 /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ 134 #define OMAP4430_CLKACTIVITY_DMT4_GFCLK_SHIFT 13 135 #define OMAP4430_CLKACTIVITY_DMT4_GFCLK_MASK (1 << 13) 136 137 /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ 138 #define OMAP4430_CLKACTIVITY_DMT9_GFCLK_SHIFT 14 139 #define OMAP4430_CLKACTIVITY_DMT9_GFCLK_MASK (1 << 14) 140 141 /* Used by CM_DSS_CLKSTCTRL */ 142 #define OMAP4430_CLKACTIVITY_DSS_ALWON_SYS_CLK_SHIFT 10 143 #define OMAP4430_CLKACTIVITY_DSS_ALWON_SYS_CLK_MASK (1 << 10) 144 145 /* Used by CM_DSS_CLKSTCTRL */ 146 #define OMAP4430_CLKACTIVITY_DSS_FCLK_SHIFT 9 147 #define OMAP4430_CLKACTIVITY_DSS_FCLK_MASK (1 << 9) 148 149 /* Used by CM_DUCATI_CLKSTCTRL */ 150 #define OMAP4430_CLKACTIVITY_DUCATI_GCLK_SHIFT 8 151 #define OMAP4430_CLKACTIVITY_DUCATI_GCLK_MASK (1 << 8) 152 153 /* Used by CM_EMU_CLKSTCTRL */ 154 #define OMAP4430_CLKACTIVITY_EMU_SYS_CLK_SHIFT 8 155 #define OMAP4430_CLKACTIVITY_EMU_SYS_CLK_MASK (1 << 8) 156 157 /* Used by CM_CAM_CLKSTCTRL */ 158 #define OMAP4430_CLKACTIVITY_FDIF_GFCLK_SHIFT 10 159 #define OMAP4430_CLKACTIVITY_FDIF_GFCLK_MASK (1 << 10) 160 161 /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ 162 #define OMAP4430_CLKACTIVITY_FUNC_12M_GFCLK_SHIFT 15 163 #define OMAP4430_CLKACTIVITY_FUNC_12M_GFCLK_MASK (1 << 15) 164 165 /* Used by CM1_ABE_CLKSTCTRL */ 166 #define OMAP4430_CLKACTIVITY_FUNC_24M_GFCLK_SHIFT 10 167 #define OMAP4430_CLKACTIVITY_FUNC_24M_GFCLK_MASK (1 << 10) 168 169 /* Used by CM_DSS_CLKSTCTRL */ 170 #define OMAP4430_CLKACTIVITY_HDMI_PHY_48MHZ_GFCLK_SHIFT 11 171 #define OMAP4430_CLKACTIVITY_HDMI_PHY_48MHZ_GFCLK_MASK (1 << 11) 172 173 /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ 174 #define OMAP4430_CLKACTIVITY_HSIC_P1_480M_GFCLK_SHIFT 20 175 #define OMAP4430_CLKACTIVITY_HSIC_P1_480M_GFCLK_MASK (1 << 20) 176 177 /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ 178 #define OMAP4430_CLKACTIVITY_HSIC_P1_GFCLK_SHIFT 26 179 #define OMAP4430_CLKACTIVITY_HSIC_P1_GFCLK_MASK (1 << 26) 180 181 /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ 182 #define OMAP4430_CLKACTIVITY_HSIC_P2_480M_GFCLK_SHIFT 21 183 #define OMAP4430_CLKACTIVITY_HSIC_P2_480M_GFCLK_MASK (1 << 21) 184 185 /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ 186 #define OMAP4430_CLKACTIVITY_HSIC_P2_GFCLK_SHIFT 27 187 #define OMAP4430_CLKACTIVITY_HSIC_P2_GFCLK_MASK (1 << 27) 188 189 /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ 190 #define OMAP4430_CLKACTIVITY_INIT_48MC_GFCLK_SHIFT 13 191 #define OMAP4430_CLKACTIVITY_INIT_48MC_GFCLK_MASK (1 << 13) 192 193 /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ 194 #define OMAP4430_CLKACTIVITY_INIT_48M_GFCLK_SHIFT 12 195 #define OMAP4430_CLKACTIVITY_INIT_48M_GFCLK_MASK (1 << 12) 196 197 /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ 198 #define OMAP4430_CLKACTIVITY_INIT_60M_P1_GFCLK_SHIFT 28 199 #define OMAP4430_CLKACTIVITY_INIT_60M_P1_GFCLK_MASK (1 << 28) 200 201 /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ 202 #define OMAP4430_CLKACTIVITY_INIT_60M_P2_GFCLK_SHIFT 29 203 #define OMAP4430_CLKACTIVITY_INIT_60M_P2_GFCLK_MASK (1 << 29) 204 205 /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ 206 #define OMAP4430_CLKACTIVITY_INIT_96M_GFCLK_SHIFT 11 207 #define OMAP4430_CLKACTIVITY_INIT_96M_GFCLK_MASK (1 << 11) 208 209 /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ 210 #define OMAP4430_CLKACTIVITY_INIT_HSI_GFCLK_SHIFT 16 211 #define OMAP4430_CLKACTIVITY_INIT_HSI_GFCLK_MASK (1 << 16) 212 213 /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ 214 #define OMAP4430_CLKACTIVITY_INIT_HSMMC1_GFCLK_SHIFT 17 215 #define OMAP4430_CLKACTIVITY_INIT_HSMMC1_GFCLK_MASK (1 << 17) 216 217 /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ 218 #define OMAP4430_CLKACTIVITY_INIT_HSMMC2_GFCLK_SHIFT 18 219 #define OMAP4430_CLKACTIVITY_INIT_HSMMC2_GFCLK_MASK (1 << 18) 220 221 /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ 222 #define OMAP4430_CLKACTIVITY_INIT_HSMMC6_GFCLK_SHIFT 19 223 #define OMAP4430_CLKACTIVITY_INIT_HSMMC6_GFCLK_MASK (1 << 19) 224 225 /* Used by CM_CAM_CLKSTCTRL */ 226 #define OMAP4430_CLKACTIVITY_ISS_GCLK_SHIFT 8 227 #define OMAP4430_CLKACTIVITY_ISS_GCLK_MASK (1 << 8) 228 229 /* Used by CM_IVAHD_CLKSTCTRL */ 230 #define OMAP4430_CLKACTIVITY_IVAHD_ROOT_CLK_SHIFT 8 231 #define OMAP4430_CLKACTIVITY_IVAHD_ROOT_CLK_MASK (1 << 8) 232 233 /* Used by CM_D2D_CLKSTCTRL */ 234 #define OMAP4430_CLKACTIVITY_L3X2_D2D_GICLK_SHIFT 10 235 #define OMAP4430_CLKACTIVITY_L3X2_D2D_GICLK_MASK (1 << 10) 236 237 /* Used by CM_L3_1_CLKSTCTRL, CM_L3_1_CLKSTCTRL_RESTORE */ 238 #define OMAP4430_CLKACTIVITY_L3_1_GICLK_SHIFT 8 239 #define OMAP4430_CLKACTIVITY_L3_1_GICLK_MASK (1 << 8) 240 241 /* Used by CM_L3_2_CLKSTCTRL, CM_L3_2_CLKSTCTRL_RESTORE */ 242 #define OMAP4430_CLKACTIVITY_L3_2_GICLK_SHIFT 8 243 #define OMAP4430_CLKACTIVITY_L3_2_GICLK_MASK (1 << 8) 244 245 /* Used by CM_D2D_CLKSTCTRL */ 246 #define OMAP4430_CLKACTIVITY_L3_D2D_GICLK_SHIFT 8 247 #define OMAP4430_CLKACTIVITY_L3_D2D_GICLK_MASK (1 << 8) 248 249 /* Used by CM_SDMA_CLKSTCTRL */ 250 #define OMAP4430_CLKACTIVITY_L3_DMA_GICLK_SHIFT 8 251 #define OMAP4430_CLKACTIVITY_L3_DMA_GICLK_MASK (1 << 8) 252 253 /* Used by CM_DSS_CLKSTCTRL */ 254 #define OMAP4430_CLKACTIVITY_L3_DSS_GICLK_SHIFT 8 255 #define OMAP4430_CLKACTIVITY_L3_DSS_GICLK_MASK (1 << 8) 256 257 /* Used by CM_MEMIF_CLKSTCTRL, CM_MEMIF_CLKSTCTRL_RESTORE */ 258 #define OMAP4430_CLKACTIVITY_L3_EMIF_GICLK_SHIFT 8 259 #define OMAP4430_CLKACTIVITY_L3_EMIF_GICLK_MASK (1 << 8) 260 261 /* Used by CM_GFX_CLKSTCTRL */ 262 #define OMAP4430_CLKACTIVITY_L3_GFX_GICLK_SHIFT 8 263 #define OMAP4430_CLKACTIVITY_L3_GFX_GICLK_MASK (1 << 8) 264 265 /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ 266 #define OMAP4430_CLKACTIVITY_L3_INIT_GICLK_SHIFT 8 267 #define OMAP4430_CLKACTIVITY_L3_INIT_GICLK_MASK (1 << 8) 268 269 /* Used by CM_L3INSTR_CLKSTCTRL */ 270 #define OMAP4430_CLKACTIVITY_L3_INSTR_GICLK_SHIFT 8 271 #define OMAP4430_CLKACTIVITY_L3_INSTR_GICLK_MASK (1 << 8) 272 273 /* Used by CM_L4SEC_CLKSTCTRL */ 274 #define OMAP4430_CLKACTIVITY_L3_SECURE_GICLK_SHIFT 8 275 #define OMAP4430_CLKACTIVITY_L3_SECURE_GICLK_MASK (1 << 8) 276 277 /* Used by CM_ALWON_CLKSTCTRL */ 278 #define OMAP4430_CLKACTIVITY_L4_AO_ICLK_SHIFT 8 279 #define OMAP4430_CLKACTIVITY_L4_AO_ICLK_MASK (1 << 8) 280 281 /* Used by CM_CEFUSE_CLKSTCTRL */ 282 #define OMAP4430_CLKACTIVITY_L4_CEFUSE_GICLK_SHIFT 8 283 #define OMAP4430_CLKACTIVITY_L4_CEFUSE_GICLK_MASK (1 << 8) 284 285 /* Used by CM_L4CFG_CLKSTCTRL, CM_L4CFG_CLKSTCTRL_RESTORE */ 286 #define OMAP4430_CLKACTIVITY_L4_CFG_GICLK_SHIFT 8 287 #define OMAP4430_CLKACTIVITY_L4_CFG_GICLK_MASK (1 << 8) 288 289 /* Used by CM_D2D_CLKSTCTRL */ 290 #define OMAP4430_CLKACTIVITY_L4_D2D_GICLK_SHIFT 9 291 #define OMAP4430_CLKACTIVITY_L4_D2D_GICLK_MASK (1 << 9) 292 293 /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ 294 #define OMAP4430_CLKACTIVITY_L4_INIT_GICLK_SHIFT 9 295 #define OMAP4430_CLKACTIVITY_L4_INIT_GICLK_MASK (1 << 9) 296 297 /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ 298 #define OMAP4430_CLKACTIVITY_L4_PER_GICLK_SHIFT 8 299 #define OMAP4430_CLKACTIVITY_L4_PER_GICLK_MASK (1 << 8) 300 301 /* Used by CM_L4SEC_CLKSTCTRL */ 302 #define OMAP4430_CLKACTIVITY_L4_SECURE_GICLK_SHIFT 9 303 #define OMAP4430_CLKACTIVITY_L4_SECURE_GICLK_MASK (1 << 9) 304 305 /* Used by CM_WKUP_CLKSTCTRL */ 306 #define OMAP4430_CLKACTIVITY_L4_WKUP_GICLK_SHIFT 12 307 #define OMAP4430_CLKACTIVITY_L4_WKUP_GICLK_MASK (1 << 12) 308 309 /* Used by CM_MPU_CLKSTCTRL, CM_MPU_CLKSTCTRL_RESTORE */ 310 #define OMAP4430_CLKACTIVITY_MPU_DPLL_CLK_SHIFT 8 311 #define OMAP4430_CLKACTIVITY_MPU_DPLL_CLK_MASK (1 << 8) 312 313 /* Used by CM1_ABE_CLKSTCTRL */ 314 #define OMAP4430_CLKACTIVITY_OCP_ABE_GICLK_SHIFT 9 315 #define OMAP4430_CLKACTIVITY_OCP_ABE_GICLK_MASK (1 << 9) 316 317 /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ 318 #define OMAP4430_CLKACTIVITY_PER_24MC_GFCLK_SHIFT 16 319 #define OMAP4430_CLKACTIVITY_PER_24MC_GFCLK_MASK (1 << 16) 320 321 /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ 322 #define OMAP4430_CLKACTIVITY_PER_32K_GFCLK_SHIFT 17 323 #define OMAP4430_CLKACTIVITY_PER_32K_GFCLK_MASK (1 << 17) 324 325 /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ 326 #define OMAP4430_CLKACTIVITY_PER_48M_GFCLK_SHIFT 18 327 #define OMAP4430_CLKACTIVITY_PER_48M_GFCLK_MASK (1 << 18) 328 329 /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ 330 #define OMAP4430_CLKACTIVITY_PER_96M_GFCLK_SHIFT 19 331 #define OMAP4430_CLKACTIVITY_PER_96M_GFCLK_MASK (1 << 19) 332 333 /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ 334 #define OMAP4430_CLKACTIVITY_PER_ABE_24M_GFCLK_SHIFT 25 335 #define OMAP4430_CLKACTIVITY_PER_ABE_24M_GFCLK_MASK (1 << 25) 336 337 /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ 338 #define OMAP4430_CLKACTIVITY_PER_MCASP2_GFCLK_SHIFT 20 339 #define OMAP4430_CLKACTIVITY_PER_MCASP2_GFCLK_MASK (1 << 20) 340 341 /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ 342 #define OMAP4430_CLKACTIVITY_PER_MCASP3_GFCLK_SHIFT 21 343 #define OMAP4430_CLKACTIVITY_PER_MCASP3_GFCLK_MASK (1 << 21) 344 345 /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ 346 #define OMAP4430_CLKACTIVITY_PER_MCBSP4_GFCLK_SHIFT 22 347 #define OMAP4430_CLKACTIVITY_PER_MCBSP4_GFCLK_MASK (1 << 22) 348 349 /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ 350 #define OMAP4430_CLKACTIVITY_PER_SYS_GFCLK_SHIFT 24 351 #define OMAP4430_CLKACTIVITY_PER_SYS_GFCLK_MASK (1 << 24) 352 353 /* Used by CM_MEMIF_CLKSTCTRL, CM_MEMIF_CLKSTCTRL_RESTORE */ 354 #define OMAP4430_CLKACTIVITY_PHY_ROOT_CLK_SHIFT 10 355 #define OMAP4430_CLKACTIVITY_PHY_ROOT_CLK_MASK (1 << 10) 356 357 /* Used by CM_GFX_CLKSTCTRL */ 358 #define OMAP4430_CLKACTIVITY_SGX_GFCLK_SHIFT 9 359 #define OMAP4430_CLKACTIVITY_SGX_GFCLK_MASK (1 << 9) 360 361 /* Used by CM_ALWON_CLKSTCTRL */ 362 #define OMAP4430_CLKACTIVITY_SR_CORE_SYSCLK_SHIFT 11 363 #define OMAP4430_CLKACTIVITY_SR_CORE_SYSCLK_MASK (1 << 11) 364 365 /* Used by CM_ALWON_CLKSTCTRL */ 366 #define OMAP4430_CLKACTIVITY_SR_IVA_SYSCLK_SHIFT 10 367 #define OMAP4430_CLKACTIVITY_SR_IVA_SYSCLK_MASK (1 << 10) 368 369 /* Used by CM_ALWON_CLKSTCTRL */ 370 #define OMAP4430_CLKACTIVITY_SR_MPU_SYSCLK_SHIFT 9 371 #define OMAP4430_CLKACTIVITY_SR_MPU_SYSCLK_MASK (1 << 9) 372 373 /* Used by CM_WKUP_CLKSTCTRL */ 374 #define OMAP4430_CLKACTIVITY_SYS_CLK_SHIFT 8 375 #define OMAP4430_CLKACTIVITY_SYS_CLK_MASK (1 << 8) 376 377 /* Used by CM_TESLA_CLKSTCTRL */ 378 #define OMAP4430_CLKACTIVITY_TESLA_ROOT_CLK_SHIFT 8 379 #define OMAP4430_CLKACTIVITY_TESLA_ROOT_CLK_MASK (1 << 8) 380 381 /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ 382 #define OMAP4430_CLKACTIVITY_TLL_CH0_GFCLK_SHIFT 22 383 #define OMAP4430_CLKACTIVITY_TLL_CH0_GFCLK_MASK (1 << 22) 384 385 /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ 386 #define OMAP4430_CLKACTIVITY_TLL_CH1_GFCLK_SHIFT 23 387 #define OMAP4430_CLKACTIVITY_TLL_CH1_GFCLK_MASK (1 << 23) 388 389 /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ 390 #define OMAP4430_CLKACTIVITY_TLL_CH2_GFCLK_SHIFT 24 391 #define OMAP4430_CLKACTIVITY_TLL_CH2_GFCLK_MASK (1 << 24) 392 393 /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ 394 #define OMAP4430_CLKACTIVITY_UNIPRO_DPLL_CLK_SHIFT 10 395 #define OMAP4430_CLKACTIVITY_UNIPRO_DPLL_CLK_MASK (1 << 10) 396 397 /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ 398 #define OMAP4430_CLKACTIVITY_USB_DPLL_CLK_SHIFT 14 399 #define OMAP4430_CLKACTIVITY_USB_DPLL_CLK_MASK (1 << 14) 400 401 /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ 402 #define OMAP4430_CLKACTIVITY_USB_DPLL_HS_CLK_SHIFT 15 403 #define OMAP4430_CLKACTIVITY_USB_DPLL_HS_CLK_MASK (1 << 15) 404 405 /* Used by CM_WKUP_CLKSTCTRL */ 406 #define OMAP4430_CLKACTIVITY_USIM_GFCLK_SHIFT 10 407 #define OMAP4430_CLKACTIVITY_USIM_GFCLK_MASK (1 << 10) 408 409 /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ 410 #define OMAP4430_CLKACTIVITY_UTMI_P3_GFCLK_SHIFT 30 411 #define OMAP4430_CLKACTIVITY_UTMI_P3_GFCLK_MASK (1 << 30) 412 413 /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ 414 #define OMAP4430_CLKACTIVITY_UTMI_ROOT_GFCLK_SHIFT 25 415 #define OMAP4430_CLKACTIVITY_UTMI_ROOT_GFCLK_MASK (1 << 25) 416 417 /* Used by CM_WKUP_CLKSTCTRL */ 418 #define OMAP4430_CLKACTIVITY_WKUP_32K_GFCLK_SHIFT 11 419 #define OMAP4430_CLKACTIVITY_WKUP_32K_GFCLK_MASK (1 << 11) 420 421 /* 422 * Used by CM1_ABE_TIMER5_CLKCTRL, CM1_ABE_TIMER6_CLKCTRL, 423 * CM1_ABE_TIMER7_CLKCTRL, CM1_ABE_TIMER8_CLKCTRL, CM_L3INIT_MMC1_CLKCTRL, 424 * CM_L3INIT_MMC2_CLKCTRL, CM_L3INIT_MMC6_CLKCTRL, CM_L4PER_DMTIMER10_CLKCTRL, 425 * CM_L4PER_DMTIMER11_CLKCTRL, CM_L4PER_DMTIMER2_CLKCTRL, 426 * CM_L4PER_DMTIMER3_CLKCTRL, CM_L4PER_DMTIMER4_CLKCTRL, 427 * CM_L4PER_DMTIMER9_CLKCTRL, CM_L4PER_MCASP2_CLKCTRL, CM_L4PER_MCASP3_CLKCTRL, 428 * CM_WKUP_TIMER1_CLKCTRL 429 */ 430 #define OMAP4430_CLKSEL_SHIFT 24 431 #define OMAP4430_CLKSEL_MASK (1 << 24) 432 433 /* 434 * Renamed from CLKSEL Used by CM_ABE_DSS_SYS_CLKSEL, CM_ABE_PLL_REF_CLKSEL, 435 * CM_L4_WKUP_CLKSEL, CM_CLKSEL_DUCATI_ISS_ROOT, CM_CLKSEL_USB_60MHZ 436 */ 437 #define OMAP4430_CLKSEL_0_0_SHIFT 0 438 #define OMAP4430_CLKSEL_0_0_MASK (1 << 0) 439 440 /* Renamed from CLKSEL Used by CM_BYPCLK_DPLL_IVA, CM_BYPCLK_DPLL_MPU */ 441 #define OMAP4430_CLKSEL_0_1_SHIFT 0 442 #define OMAP4430_CLKSEL_0_1_MASK (0x3 << 0) 443 444 /* Renamed from CLKSEL Used by CM_L3INIT_HSI_CLKCTRL */ 445 #define OMAP4430_CLKSEL_24_25_SHIFT 24 446 #define OMAP4430_CLKSEL_24_25_MASK (0x3 << 24) 447 448 /* Used by CM_L3INIT_USB_OTG_CLKCTRL */ 449 #define OMAP4430_CLKSEL_60M_SHIFT 24 450 #define OMAP4430_CLKSEL_60M_MASK (1 << 24) 451 452 /* Used by CM1_ABE_AESS_CLKCTRL */ 453 #define OMAP4430_CLKSEL_AESS_FCLK_SHIFT 24 454 #define OMAP4430_CLKSEL_AESS_FCLK_MASK (1 << 24) 455 456 /* Used by CM_CLKSEL_CORE, CM_CLKSEL_CORE_RESTORE */ 457 #define OMAP4430_CLKSEL_CORE_SHIFT 0 458 #define OMAP4430_CLKSEL_CORE_MASK (1 << 0) 459 460 /* 461 * Renamed from CLKSEL_CORE Used by CM_SHADOW_FREQ_CONFIG2_RESTORE, 462 * CM_SHADOW_FREQ_CONFIG2 463 */ 464 #define OMAP4430_CLKSEL_CORE_1_1_SHIFT 1 465 #define OMAP4430_CLKSEL_CORE_1_1_MASK (1 << 1) 466 467 /* Used by CM_WKUP_USIM_CLKCTRL */ 468 #define OMAP4430_CLKSEL_DIV_SHIFT 24 469 #define OMAP4430_CLKSEL_DIV_MASK (1 << 24) 470 471 /* Used by CM_CAM_FDIF_CLKCTRL */ 472 #define OMAP4430_CLKSEL_FCLK_SHIFT 24 473 #define OMAP4430_CLKSEL_FCLK_MASK (0x3 << 24) 474 475 /* Used by CM_L4PER_MCBSP4_CLKCTRL */ 476 #define OMAP4430_CLKSEL_INTERNAL_SOURCE_SHIFT 25 477 #define OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK (1 << 25) 478 479 /* 480 * Renamed from CLKSEL_INTERNAL_SOURCE Used by CM1_ABE_DMIC_CLKCTRL, 481 * CM1_ABE_MCASP_CLKCTRL, CM1_ABE_MCBSP1_CLKCTRL, CM1_ABE_MCBSP2_CLKCTRL, 482 * CM1_ABE_MCBSP3_CLKCTRL 483 */ 484 #define OMAP4430_CLKSEL_INTERNAL_SOURCE_CM1_ABE_DMIC_SHIFT 26 485 #define OMAP4430_CLKSEL_INTERNAL_SOURCE_CM1_ABE_DMIC_MASK (0x3 << 26) 486 487 /* Used by CM_CLKSEL_CORE, CM_CLKSEL_CORE_RESTORE */ 488 #define OMAP4430_CLKSEL_L3_SHIFT 4 489 #define OMAP4430_CLKSEL_L3_MASK (1 << 4) 490 491 /* 492 * Renamed from CLKSEL_L3 Used by CM_SHADOW_FREQ_CONFIG2_RESTORE, 493 * CM_SHADOW_FREQ_CONFIG2 494 */ 495 #define OMAP4430_CLKSEL_L3_SHADOW_SHIFT 2 496 #define OMAP4430_CLKSEL_L3_SHADOW_MASK (1 << 2) 497 498 /* Used by CM_CLKSEL_CORE, CM_CLKSEL_CORE_RESTORE */ 499 #define OMAP4430_CLKSEL_L4_SHIFT 8 500 #define OMAP4430_CLKSEL_L4_MASK (1 << 8) 501 502 /* Used by CM_CLKSEL_ABE */ 503 #define OMAP4430_CLKSEL_OPP_SHIFT 0 504 #define OMAP4430_CLKSEL_OPP_MASK (0x3 << 0) 505 506 /* Used by CM_EMU_DEBUGSS_CLKCTRL */ 507 #define OMAP4430_CLKSEL_PMD_STM_CLK_SHIFT 27 508 #define OMAP4430_CLKSEL_PMD_STM_CLK_MASK (0x7 << 27) 509 510 /* Used by CM_EMU_DEBUGSS_CLKCTRL */ 511 #define OMAP4430_CLKSEL_PMD_TRACE_CLK_SHIFT 24 512 #define OMAP4430_CLKSEL_PMD_TRACE_CLK_MASK (0x7 << 24) 513 514 /* Used by CM_GFX_GFX_CLKCTRL */ 515 #define OMAP4430_CLKSEL_SGX_FCLK_SHIFT 24 516 #define OMAP4430_CLKSEL_SGX_FCLK_MASK (1 << 24) 517 518 /* 519 * Used by CM1_ABE_DMIC_CLKCTRL, CM1_ABE_MCASP_CLKCTRL, CM1_ABE_MCBSP1_CLKCTRL, 520 * CM1_ABE_MCBSP2_CLKCTRL, CM1_ABE_MCBSP3_CLKCTRL 521 */ 522 #define OMAP4430_CLKSEL_SOURCE_SHIFT 24 523 #define OMAP4430_CLKSEL_SOURCE_MASK (0x3 << 24) 524 525 /* Renamed from CLKSEL_SOURCE Used by CM_L4PER_MCBSP4_CLKCTRL */ 526 #define OMAP4430_CLKSEL_SOURCE_24_24_SHIFT 24 527 #define OMAP4430_CLKSEL_SOURCE_24_24_MASK (1 << 24) 528 529 /* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */ 530 #define OMAP4430_CLKSEL_UTMI_P1_SHIFT 24 531 #define OMAP4430_CLKSEL_UTMI_P1_MASK (1 << 24) 532 533 /* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */ 534 #define OMAP4430_CLKSEL_UTMI_P2_SHIFT 25 535 #define OMAP4430_CLKSEL_UTMI_P2_MASK (1 << 25) 536 537 /* 538 * Used by CM1_ABE_CLKSTCTRL, CM_ALWON_CLKSTCTRL, CM_CAM_CLKSTCTRL, 539 * CM_CEFUSE_CLKSTCTRL, CM_D2D_CLKSTCTRL, CM_DSS_CLKSTCTRL, 540 * CM_DUCATI_CLKSTCTRL, CM_EMU_CLKSTCTRL, CM_GFX_CLKSTCTRL, CM_IVAHD_CLKSTCTRL, 541 * CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE, CM_L3INSTR_CLKSTCTRL, 542 * CM_L3_1_CLKSTCTRL, CM_L3_1_CLKSTCTRL_RESTORE, CM_L3_2_CLKSTCTRL, 543 * CM_L3_2_CLKSTCTRL_RESTORE, CM_L4CFG_CLKSTCTRL, CM_L4CFG_CLKSTCTRL_RESTORE, 544 * CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE, CM_L4SEC_CLKSTCTRL, 545 * CM_MEMIF_CLKSTCTRL, CM_MEMIF_CLKSTCTRL_RESTORE, CM_MPU_CLKSTCTRL, 546 * CM_MPU_CLKSTCTRL_RESTORE, CM_SDMA_CLKSTCTRL, CM_TESLA_CLKSTCTRL, 547 * CM_WKUP_CLKSTCTRL 548 */ 549 #define OMAP4430_CLKTRCTRL_SHIFT 0 550 #define OMAP4430_CLKTRCTRL_MASK (0x3 << 0) 551 552 /* Used by CM_EMU_OVERRIDE_DPLL_CORE */ 553 #define OMAP4430_CORE_DPLL_EMU_DIV_SHIFT 0 554 #define OMAP4430_CORE_DPLL_EMU_DIV_MASK (0x7f << 0) 555 556 /* Used by CM_EMU_OVERRIDE_DPLL_CORE */ 557 #define OMAP4430_CORE_DPLL_EMU_MULT_SHIFT 8 558 #define OMAP4430_CORE_DPLL_EMU_MULT_MASK (0x7ff << 8) 559 560 /* Used by REVISION_CM1, REVISION_CM2 */ 561 #define OMAP4430_CUSTOM_SHIFT 6 562 #define OMAP4430_CUSTOM_MASK (0x3 << 6) 563 564 /* 565 * Used by CM_L3_2_DYNAMICDEP, CM_L3_2_DYNAMICDEP_RESTORE, CM_L4CFG_DYNAMICDEP, 566 * CM_L4CFG_DYNAMICDEP_RESTORE 567 */ 568 #define OMAP4430_D2D_DYNDEP_SHIFT 18 569 #define OMAP4430_D2D_DYNDEP_MASK (1 << 18) 570 571 /* Used by CM_MPU_STATICDEP */ 572 #define OMAP4430_D2D_STATDEP_SHIFT 18 573 #define OMAP4430_D2D_STATDEP_MASK (1 << 18) 574 575 /* 576 * Used by CM_SSC_DELTAMSTEP_DPLL_ABE, CM_SSC_DELTAMSTEP_DPLL_CORE, 577 * CM_SSC_DELTAMSTEP_DPLL_CORE_RESTORE, CM_SSC_DELTAMSTEP_DPLL_DDRPHY, 578 * CM_SSC_DELTAMSTEP_DPLL_IVA, CM_SSC_DELTAMSTEP_DPLL_MPU, 579 * CM_SSC_DELTAMSTEP_DPLL_PER, CM_SSC_DELTAMSTEP_DPLL_UNIPRO, 580 * CM_SSC_DELTAMSTEP_DPLL_USB 581 */ 582 #define OMAP4430_DELTAMSTEP_SHIFT 0 583 #define OMAP4430_DELTAMSTEP_MASK (0xfffff << 0) 584 585 /* Used by CM_SHADOW_FREQ_CONFIG1, CM_SHADOW_FREQ_CONFIG1_RESTORE */ 586 #define OMAP4430_DLL_OVERRIDE_SHIFT 2 587 #define OMAP4430_DLL_OVERRIDE_MASK (1 << 2) 588 589 /* Renamed from DLL_OVERRIDE Used by CM_DLL_CTRL */ 590 #define OMAP4430_DLL_OVERRIDE_0_0_SHIFT 0 591 #define OMAP4430_DLL_OVERRIDE_0_0_MASK (1 << 0) 592 593 /* Used by CM_SHADOW_FREQ_CONFIG1, CM_SHADOW_FREQ_CONFIG1_RESTORE */ 594 #define OMAP4430_DLL_RESET_SHIFT 3 595 #define OMAP4430_DLL_RESET_MASK (1 << 3) 596 597 /* 598 * Used by CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE, 599 * CM_CLKSEL_DPLL_CORE_RESTORE, CM_CLKSEL_DPLL_DDRPHY, CM_CLKSEL_DPLL_IVA, 600 * CM_CLKSEL_DPLL_MPU, CM_CLKSEL_DPLL_PER, CM_CLKSEL_DPLL_UNIPRO, 601 * CM_CLKSEL_DPLL_USB 602 */ 603 #define OMAP4430_DPLL_BYP_CLKSEL_SHIFT 23 604 #define OMAP4430_DPLL_BYP_CLKSEL_MASK (1 << 23) 605 606 /* Used by CM_CLKDCOLDO_DPLL_USB */ 607 #define OMAP4430_DPLL_CLKDCOLDO_GATE_CTRL_SHIFT 8 608 #define OMAP4430_DPLL_CLKDCOLDO_GATE_CTRL_MASK (1 << 8) 609 610 /* Used by CM_CLKSEL_DPLL_CORE, CM_CLKSEL_DPLL_CORE_RESTORE */ 611 #define OMAP4430_DPLL_CLKOUTHIF_CLKSEL_SHIFT 20 612 #define OMAP4430_DPLL_CLKOUTHIF_CLKSEL_MASK (1 << 20) 613 614 /* 615 * Used by CM_DIV_M3_DPLL_ABE, CM_DIV_M3_DPLL_CORE, 616 * CM_DIV_M3_DPLL_CORE_RESTORE, CM_DIV_M3_DPLL_PER 617 */ 618 #define OMAP4430_DPLL_CLKOUTHIF_DIV_SHIFT 0 619 #define OMAP4430_DPLL_CLKOUTHIF_DIV_MASK (0x1f << 0) 620 621 /* 622 * Used by CM_DIV_M3_DPLL_ABE, CM_DIV_M3_DPLL_CORE, 623 * CM_DIV_M3_DPLL_CORE_RESTORE, CM_DIV_M3_DPLL_PER 624 */ 625 #define OMAP4430_DPLL_CLKOUTHIF_DIVCHACK_SHIFT 5 626 #define OMAP4430_DPLL_CLKOUTHIF_DIVCHACK_MASK (1 << 5) 627 628 /* 629 * Used by CM_DIV_M3_DPLL_ABE, CM_DIV_M3_DPLL_CORE, 630 * CM_DIV_M3_DPLL_CORE_RESTORE, CM_DIV_M3_DPLL_PER 631 */ 632 #define OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT 8 633 #define OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_MASK (1 << 8) 634 635 /* Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_UNIPRO */ 636 #define OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_SHIFT 10 637 #define OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK (1 << 10) 638 639 /* 640 * Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE, 641 * CM_DIV_M2_DPLL_CORE_RESTORE, CM_DIV_M2_DPLL_DDRPHY, CM_DIV_M2_DPLL_MPU, 642 * CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_UNIPRO 643 */ 644 #define OMAP4430_DPLL_CLKOUT_DIV_SHIFT 0 645 #define OMAP4430_DPLL_CLKOUT_DIV_MASK (0x1f << 0) 646 647 /* Renamed from DPLL_CLKOUT_DIV Used by CM_DIV_M2_DPLL_USB */ 648 #define OMAP4430_DPLL_CLKOUT_DIV_0_6_SHIFT 0 649 #define OMAP4430_DPLL_CLKOUT_DIV_0_6_MASK (0x7f << 0) 650 651 /* 652 * Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE, 653 * CM_DIV_M2_DPLL_CORE_RESTORE, CM_DIV_M2_DPLL_DDRPHY, CM_DIV_M2_DPLL_MPU, 654 * CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_UNIPRO 655 */ 656 #define OMAP4430_DPLL_CLKOUT_DIVCHACK_SHIFT 5 657 #define OMAP4430_DPLL_CLKOUT_DIVCHACK_MASK (1 << 5) 658 659 /* Renamed from DPLL_CLKOUT_DIVCHACK Used by CM_DIV_M2_DPLL_USB */ 660 #define OMAP4430_DPLL_CLKOUT_DIVCHACK_M2_USB_SHIFT 7 661 #define OMAP4430_DPLL_CLKOUT_DIVCHACK_M2_USB_MASK (1 << 7) 662 663 /* 664 * Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE, 665 * CM_DIV_M2_DPLL_CORE_RESTORE, CM_DIV_M2_DPLL_DDRPHY, CM_DIV_M2_DPLL_MPU, 666 * CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_USB 667 */ 668 #define OMAP4430_DPLL_CLKOUT_GATE_CTRL_SHIFT 8 669 #define OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK (1 << 8) 670 671 /* Used by CM_SHADOW_FREQ_CONFIG1, CM_SHADOW_FREQ_CONFIG1_RESTORE */ 672 #define OMAP4430_DPLL_CORE_DPLL_EN_SHIFT 8 673 #define OMAP4430_DPLL_CORE_DPLL_EN_MASK (0x7 << 8) 674 675 /* Used by CM_SHADOW_FREQ_CONFIG1, CM_SHADOW_FREQ_CONFIG1_RESTORE */ 676 #define OMAP4430_DPLL_CORE_M2_DIV_SHIFT 11 677 #define OMAP4430_DPLL_CORE_M2_DIV_MASK (0x1f << 11) 678 679 /* Used by CM_SHADOW_FREQ_CONFIG2, CM_SHADOW_FREQ_CONFIG2_RESTORE */ 680 #define OMAP4430_DPLL_CORE_M5_DIV_SHIFT 3 681 #define OMAP4430_DPLL_CORE_M5_DIV_MASK (0x1f << 3) 682 683 /* 684 * Used by CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE, 685 * CM_CLKSEL_DPLL_CORE_RESTORE, CM_CLKSEL_DPLL_DDRPHY, CM_CLKSEL_DPLL_IVA, 686 * CM_CLKSEL_DPLL_MPU, CM_CLKSEL_DPLL_PER, CM_CLKSEL_DPLL_UNIPRO 687 */ 688 #define OMAP4430_DPLL_DIV_SHIFT 0 689 #define OMAP4430_DPLL_DIV_MASK (0x7f << 0) 690 691 /* Renamed from DPLL_DIV Used by CM_CLKSEL_DPLL_USB */ 692 #define OMAP4430_DPLL_DIV_0_7_SHIFT 0 693 #define OMAP4430_DPLL_DIV_0_7_MASK (0xff << 0) 694 695 /* 696 * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, 697 * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA, 698 * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER 699 */ 700 #define OMAP4430_DPLL_DRIFTGUARD_EN_SHIFT 8 701 #define OMAP4430_DPLL_DRIFTGUARD_EN_MASK (1 << 8) 702 703 /* Renamed from DPLL_DRIFTGUARD_EN Used by CM_CLKMODE_DPLL_UNIPRO */ 704 #define OMAP4430_DPLL_DRIFTGUARD_EN_3_3_SHIFT 3 705 #define OMAP4430_DPLL_DRIFTGUARD_EN_3_3_MASK (1 << 3) 706 707 /* 708 * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, 709 * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA, 710 * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO, 711 * CM_CLKMODE_DPLL_USB 712 */ 713 #define OMAP4430_DPLL_EN_SHIFT 0 714 #define OMAP4430_DPLL_EN_MASK (0x7 << 0) 715 716 /* 717 * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, 718 * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA, 719 * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO 720 */ 721 #define OMAP4430_DPLL_LPMODE_EN_SHIFT 10 722 #define OMAP4430_DPLL_LPMODE_EN_MASK (1 << 10) 723 724 /* 725 * Used by CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE, 726 * CM_CLKSEL_DPLL_CORE_RESTORE, CM_CLKSEL_DPLL_DDRPHY, CM_CLKSEL_DPLL_IVA, 727 * CM_CLKSEL_DPLL_MPU, CM_CLKSEL_DPLL_PER, CM_CLKSEL_DPLL_UNIPRO 728 */ 729 #define OMAP4430_DPLL_MULT_SHIFT 8 730 #define OMAP4430_DPLL_MULT_MASK (0x7ff << 8) 731 732 /* Renamed from DPLL_MULT Used by CM_CLKSEL_DPLL_USB */ 733 #define OMAP4430_DPLL_MULT_USB_SHIFT 8 734 #define OMAP4430_DPLL_MULT_USB_MASK (0xfff << 8) 735 736 /* 737 * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, 738 * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA, 739 * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO 740 */ 741 #define OMAP4430_DPLL_REGM4XEN_SHIFT 11 742 #define OMAP4430_DPLL_REGM4XEN_MASK (1 << 11) 743 744 /* Used by CM_CLKSEL_DPLL_USB */ 745 #define OMAP4430_DPLL_SD_DIV_SHIFT 24 746 #define OMAP4430_DPLL_SD_DIV_MASK (0xff << 24) 747 748 /* 749 * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, 750 * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA, 751 * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO, 752 * CM_CLKMODE_DPLL_USB 753 */ 754 #define OMAP4430_DPLL_SSC_ACK_SHIFT 13 755 #define OMAP4430_DPLL_SSC_ACK_MASK (1 << 13) 756 757 /* 758 * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, 759 * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA, 760 * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO, 761 * CM_CLKMODE_DPLL_USB 762 */ 763 #define OMAP4430_DPLL_SSC_DOWNSPREAD_SHIFT 14 764 #define OMAP4430_DPLL_SSC_DOWNSPREAD_MASK (1 << 14) 765 766 /* 767 * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, 768 * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA, 769 * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO, 770 * CM_CLKMODE_DPLL_USB 771 */ 772 #define OMAP4430_DPLL_SSC_EN_SHIFT 12 773 #define OMAP4430_DPLL_SSC_EN_MASK (1 << 12) 774 775 /* 776 * Used by CM_L3_2_DYNAMICDEP, CM_L3_2_DYNAMICDEP_RESTORE, CM_L4CFG_DYNAMICDEP, 777 * CM_L4CFG_DYNAMICDEP_RESTORE, CM_L4PER_DYNAMICDEP, CM_L4PER_DYNAMICDEP_RESTORE 778 */ 779 #define OMAP4430_DSS_DYNDEP_SHIFT 8 780 #define OMAP4430_DSS_DYNDEP_MASK (1 << 8) 781 782 /* 783 * Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP, CM_SDMA_STATICDEP, 784 * CM_SDMA_STATICDEP_RESTORE 785 */ 786 #define OMAP4430_DSS_STATDEP_SHIFT 8 787 #define OMAP4430_DSS_STATDEP_MASK (1 << 8) 788 789 /* Used by CM_L3_2_DYNAMICDEP, CM_L3_2_DYNAMICDEP_RESTORE */ 790 #define OMAP4430_DUCATI_DYNDEP_SHIFT 0 791 #define OMAP4430_DUCATI_DYNDEP_MASK (1 << 0) 792 793 /* Used by CM_MPU_STATICDEP, CM_SDMA_STATICDEP, CM_SDMA_STATICDEP_RESTORE */ 794 #define OMAP4430_DUCATI_STATDEP_SHIFT 0 795 #define OMAP4430_DUCATI_STATDEP_MASK (1 << 0) 796 797 /* Used by CM_SHADOW_FREQ_CONFIG1, CM_SHADOW_FREQ_CONFIG1_RESTORE */ 798 #define OMAP4430_FREQ_UPDATE_SHIFT 0 799 #define OMAP4430_FREQ_UPDATE_MASK (1 << 0) 800 801 /* Used by REVISION_CM1, REVISION_CM2 */ 802 #define OMAP4430_FUNC_SHIFT 16 803 #define OMAP4430_FUNC_MASK (0xfff << 16) 804 805 /* Used by CM_L3_2_DYNAMICDEP, CM_L3_2_DYNAMICDEP_RESTORE */ 806 #define OMAP4430_GFX_DYNDEP_SHIFT 10 807 #define OMAP4430_GFX_DYNDEP_MASK (1 << 10) 808 809 /* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP */ 810 #define OMAP4430_GFX_STATDEP_SHIFT 10 811 #define OMAP4430_GFX_STATDEP_MASK (1 << 10) 812 813 /* Used by CM_SHADOW_FREQ_CONFIG2, CM_SHADOW_FREQ_CONFIG2_RESTORE */ 814 #define OMAP4430_GPMC_FREQ_UPDATE_SHIFT 0 815 #define OMAP4430_GPMC_FREQ_UPDATE_MASK (1 << 0) 816 817 /* 818 * Used by CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_CORE_RESTORE, 819 * CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA, CM_DIV_M4_DPLL_PER 820 */ 821 #define OMAP4430_HSDIVIDER_CLKOUT1_DIV_SHIFT 0 822 #define OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK (0x1f << 0) 823 824 /* 825 * Used by CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_CORE_RESTORE, 826 * CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA, CM_DIV_M4_DPLL_PER 827 */ 828 #define OMAP4430_HSDIVIDER_CLKOUT1_DIVCHACK_SHIFT 5 829 #define OMAP4430_HSDIVIDER_CLKOUT1_DIVCHACK_MASK (1 << 5) 830 831 /* 832 * Used by CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_CORE_RESTORE, 833 * CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA, CM_DIV_M4_DPLL_PER 834 */ 835 #define OMAP4430_HSDIVIDER_CLKOUT1_GATE_CTRL_SHIFT 8 836 #define OMAP4430_HSDIVIDER_CLKOUT1_GATE_CTRL_MASK (1 << 8) 837 838 /* 839 * Used by CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_CORE_RESTORE, 840 * CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA, CM_DIV_M4_DPLL_PER 841 */ 842 #define OMAP4430_HSDIVIDER_CLKOUT1_PWDN_SHIFT 12 843 #define OMAP4430_HSDIVIDER_CLKOUT1_PWDN_MASK (1 << 12) 844 845 /* 846 * Used by CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_CORE_RESTORE, 847 * CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA, CM_DIV_M5_DPLL_PER 848 */ 849 #define OMAP4430_HSDIVIDER_CLKOUT2_DIV_SHIFT 0 850 #define OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK (0x1f << 0) 851 852 /* 853 * Used by CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_CORE_RESTORE, 854 * CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA, CM_DIV_M5_DPLL_PER 855 */ 856 #define OMAP4430_HSDIVIDER_CLKOUT2_DIVCHACK_SHIFT 5 857 #define OMAP4430_HSDIVIDER_CLKOUT2_DIVCHACK_MASK (1 << 5) 858 859 /* 860 * Used by CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_CORE_RESTORE, 861 * CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA, CM_DIV_M5_DPLL_PER 862 */ 863 #define OMAP4430_HSDIVIDER_CLKOUT2_GATE_CTRL_SHIFT 8 864 #define OMAP4430_HSDIVIDER_CLKOUT2_GATE_CTRL_MASK (1 << 8) 865 866 /* 867 * Used by CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_CORE_RESTORE, 868 * CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA, CM_DIV_M5_DPLL_PER 869 */ 870 #define OMAP4430_HSDIVIDER_CLKOUT2_PWDN_SHIFT 12 871 #define OMAP4430_HSDIVIDER_CLKOUT2_PWDN_MASK (1 << 12) 872 873 /* 874 * Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_CORE_RESTORE, 875 * CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER 876 */ 877 #define OMAP4430_HSDIVIDER_CLKOUT3_DIV_SHIFT 0 878 #define OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK (0x1f << 0) 879 880 /* 881 * Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_CORE_RESTORE, 882 * CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER 883 */ 884 #define OMAP4430_HSDIVIDER_CLKOUT3_DIVCHACK_SHIFT 5 885 #define OMAP4430_HSDIVIDER_CLKOUT3_DIVCHACK_MASK (1 << 5) 886 887 /* 888 * Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_CORE_RESTORE, 889 * CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER 890 */ 891 #define OMAP4430_HSDIVIDER_CLKOUT3_GATE_CTRL_SHIFT 8 892 #define OMAP4430_HSDIVIDER_CLKOUT3_GATE_CTRL_MASK (1 << 8) 893 894 /* 895 * Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_CORE_RESTORE, 896 * CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER 897 */ 898 #define OMAP4430_HSDIVIDER_CLKOUT3_PWDN_SHIFT 12 899 #define OMAP4430_HSDIVIDER_CLKOUT3_PWDN_MASK (1 << 12) 900 901 /* 902 * Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_CORE_RESTORE, 903 * CM_DIV_M7_DPLL_PER 904 */ 905 #define OMAP4430_HSDIVIDER_CLKOUT4_DIV_SHIFT 0 906 #define OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK (0x1f << 0) 907 908 /* 909 * Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_CORE_RESTORE, 910 * CM_DIV_M7_DPLL_PER 911 */ 912 #define OMAP4430_HSDIVIDER_CLKOUT4_DIVCHACK_SHIFT 5 913 #define OMAP4430_HSDIVIDER_CLKOUT4_DIVCHACK_MASK (1 << 5) 914 915 /* 916 * Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_CORE_RESTORE, 917 * CM_DIV_M7_DPLL_PER 918 */ 919 #define OMAP4430_HSDIVIDER_CLKOUT4_GATE_CTRL_SHIFT 8 920 #define OMAP4430_HSDIVIDER_CLKOUT4_GATE_CTRL_MASK (1 << 8) 921 922 /* 923 * Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_CORE_RESTORE, 924 * CM_DIV_M7_DPLL_PER 925 */ 926 #define OMAP4430_HSDIVIDER_CLKOUT4_PWDN_SHIFT 12 927 #define OMAP4430_HSDIVIDER_CLKOUT4_PWDN_MASK (1 << 12) 928 929 /* 930 * Used by CM1_ABE_AESS_CLKCTRL, CM1_ABE_DMIC_CLKCTRL, CM1_ABE_L4ABE_CLKCTRL, 931 * CM1_ABE_MCASP_CLKCTRL, CM1_ABE_MCBSP1_CLKCTRL, CM1_ABE_MCBSP2_CLKCTRL, 932 * CM1_ABE_MCBSP3_CLKCTRL, CM1_ABE_PDM_CLKCTRL, CM1_ABE_SLIMBUS_CLKCTRL, 933 * CM1_ABE_TIMER5_CLKCTRL, CM1_ABE_TIMER6_CLKCTRL, CM1_ABE_TIMER7_CLKCTRL, 934 * CM1_ABE_TIMER8_CLKCTRL, CM1_ABE_WDT3_CLKCTRL, CM_ALWON_MDMINTC_CLKCTRL, 935 * CM_ALWON_SR_CORE_CLKCTRL, CM_ALWON_SR_IVA_CLKCTRL, CM_ALWON_SR_MPU_CLKCTRL, 936 * CM_CAM_FDIF_CLKCTRL, CM_CAM_ISS_CLKCTRL, CM_CEFUSE_CEFUSE_CLKCTRL, 937 * CM_CM1_PROFILING_CLKCTRL, CM_CM1_PROFILING_CLKCTRL_RESTORE, 938 * CM_CM2_PROFILING_CLKCTRL, CM_CM2_PROFILING_CLKCTRL_RESTORE, 939 * CM_D2D_MODEM_ICR_CLKCTRL, CM_D2D_SAD2D_CLKCTRL, CM_D2D_SAD2D_FW_CLKCTRL, 940 * CM_DSS_DEISS_CLKCTRL, CM_DSS_DSS_CLKCTRL, CM_DUCATI_DUCATI_CLKCTRL, 941 * CM_EMU_DEBUGSS_CLKCTRL, CM_GFX_GFX_CLKCTRL, CM_IVAHD_IVAHD_CLKCTRL, 942 * CM_IVAHD_SL2_CLKCTRL, CM_L3INIT_CCPTX_CLKCTRL, CM_L3INIT_EMAC_CLKCTRL, 943 * CM_L3INIT_HSI_CLKCTRL, CM_L3INIT_MMC1_CLKCTRL, CM_L3INIT_MMC2_CLKCTRL, 944 * CM_L3INIT_MMC6_CLKCTRL, CM_L3INIT_P1500_CLKCTRL, CM_L3INIT_PCIESS_CLKCTRL, 945 * CM_L3INIT_SATA_CLKCTRL, CM_L3INIT_TPPSS_CLKCTRL, CM_L3INIT_UNIPRO1_CLKCTRL, 946 * CM_L3INIT_USBPHYOCP2SCP_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL, 947 * CM_L3INIT_USB_HOST_CLKCTRL_RESTORE, CM_L3INIT_USB_HOST_FS_CLKCTRL, 948 * CM_L3INIT_USB_OTG_CLKCTRL, CM_L3INIT_USB_TLL_CLKCTRL, 949 * CM_L3INIT_USB_TLL_CLKCTRL_RESTORE, CM_L3INIT_XHPI_CLKCTRL, 950 * CM_L3INSTR_L3_3_CLKCTRL, CM_L3INSTR_L3_3_CLKCTRL_RESTORE, 951 * CM_L3INSTR_L3_INSTR_CLKCTRL, CM_L3INSTR_L3_INSTR_CLKCTRL_RESTORE, 952 * CM_L3INSTR_OCP_WP1_CLKCTRL, CM_L3INSTR_OCP_WP1_CLKCTRL_RESTORE, 953 * CM_L3_1_L3_1_CLKCTRL, CM_L3_2_GPMC_CLKCTRL, CM_L3_2_L3_2_CLKCTRL, 954 * CM_L3_2_OCMC_RAM_CLKCTRL, CM_L4CFG_HW_SEM_CLKCTRL, CM_L4CFG_L4_CFG_CLKCTRL, 955 * CM_L4CFG_MAILBOX_CLKCTRL, CM_L4CFG_SAR_ROM_CLKCTRL, CM_L4PER_ADC_CLKCTRL, 956 * CM_L4PER_DMTIMER10_CLKCTRL, CM_L4PER_DMTIMER11_CLKCTRL, 957 * CM_L4PER_DMTIMER2_CLKCTRL, CM_L4PER_DMTIMER3_CLKCTRL, 958 * CM_L4PER_DMTIMER4_CLKCTRL, CM_L4PER_DMTIMER9_CLKCTRL, CM_L4PER_ELM_CLKCTRL, 959 * CM_L4PER_GPIO2_CLKCTRL, CM_L4PER_GPIO2_CLKCTRL_RESTORE, 960 * CM_L4PER_GPIO3_CLKCTRL, CM_L4PER_GPIO3_CLKCTRL_RESTORE, 961 * CM_L4PER_GPIO4_CLKCTRL, CM_L4PER_GPIO4_CLKCTRL_RESTORE, 962 * CM_L4PER_GPIO5_CLKCTRL, CM_L4PER_GPIO5_CLKCTRL_RESTORE, 963 * CM_L4PER_GPIO6_CLKCTRL, CM_L4PER_GPIO6_CLKCTRL_RESTORE, 964 * CM_L4PER_HDQ1W_CLKCTRL, CM_L4PER_HECC1_CLKCTRL, CM_L4PER_HECC2_CLKCTRL, 965 * CM_L4PER_I2C1_CLKCTRL, CM_L4PER_I2C2_CLKCTRL, CM_L4PER_I2C3_CLKCTRL, 966 * CM_L4PER_I2C4_CLKCTRL, CM_L4PER_I2C5_CLKCTRL, CM_L4PER_L4PER_CLKCTRL, 967 * CM_L4PER_MCASP2_CLKCTRL, CM_L4PER_MCASP3_CLKCTRL, CM_L4PER_MCBSP4_CLKCTRL, 968 * CM_L4PER_MCSPI1_CLKCTRL, CM_L4PER_MCSPI2_CLKCTRL, CM_L4PER_MCSPI3_CLKCTRL, 969 * CM_L4PER_MCSPI4_CLKCTRL, CM_L4PER_MGATE_CLKCTRL, CM_L4PER_MMCSD3_CLKCTRL, 970 * CM_L4PER_MMCSD4_CLKCTRL, CM_L4PER_MMCSD5_CLKCTRL, CM_L4PER_MSPROHG_CLKCTRL, 971 * CM_L4PER_SLIMBUS2_CLKCTRL, CM_L4PER_UART1_CLKCTRL, CM_L4PER_UART2_CLKCTRL, 972 * CM_L4PER_UART3_CLKCTRL, CM_L4PER_UART4_CLKCTRL, CM_L4SEC_AES1_CLKCTRL, 973 * CM_L4SEC_AES2_CLKCTRL, CM_L4SEC_CRYPTODMA_CLKCTRL, CM_L4SEC_DES3DES_CLKCTRL, 974 * CM_L4SEC_PKAEIP29_CLKCTRL, CM_L4SEC_RNG_CLKCTRL, CM_L4SEC_SHA2MD51_CLKCTRL, 975 * CM_MEMIF_DMM_CLKCTRL, CM_MEMIF_EMIF_1_CLKCTRL, CM_MEMIF_EMIF_2_CLKCTRL, 976 * CM_MEMIF_EMIF_FW_CLKCTRL, CM_MEMIF_EMIF_H1_CLKCTRL, 977 * CM_MEMIF_EMIF_H2_CLKCTRL, CM_MPU_MPU_CLKCTRL, CM_SDMA_SDMA_CLKCTRL, 978 * CM_TESLA_TESLA_CLKCTRL, CM_WKUP_GPIO1_CLKCTRL, CM_WKUP_KEYBOARD_CLKCTRL, 979 * CM_WKUP_L4WKUP_CLKCTRL, CM_WKUP_RTC_CLKCTRL, CM_WKUP_SARRAM_CLKCTRL, 980 * CM_WKUP_SYNCTIMER_CLKCTRL, CM_WKUP_TIMER12_CLKCTRL, CM_WKUP_TIMER1_CLKCTRL, 981 * CM_WKUP_USIM_CLKCTRL, CM_WKUP_WDT1_CLKCTRL, CM_WKUP_WDT2_CLKCTRL 982 */ 983 #define OMAP4430_IDLEST_SHIFT 16 984 #define OMAP4430_IDLEST_MASK (0x3 << 16) 985 986 /* 987 * Used by CM_DUCATI_DYNAMICDEP, CM_L3_2_DYNAMICDEP, 988 * CM_L3_2_DYNAMICDEP_RESTORE, CM_L4CFG_DYNAMICDEP, CM_L4CFG_DYNAMICDEP_RESTORE 989 */ 990 #define OMAP4430_ISS_DYNDEP_SHIFT 9 991 #define OMAP4430_ISS_DYNDEP_MASK (1 << 9) 992 993 /* 994 * Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP, CM_SDMA_STATICDEP, 995 * CM_SDMA_STATICDEP_RESTORE, CM_TESLA_STATICDEP 996 */ 997 #define OMAP4430_ISS_STATDEP_SHIFT 9 998 #define OMAP4430_ISS_STATDEP_MASK (1 << 9) 999 1000 /* Used by CM_L3_2_DYNAMICDEP, CM_L3_2_DYNAMICDEP_RESTORE, CM_TESLA_DYNAMICDEP */ 1001 #define OMAP4430_IVAHD_DYNDEP_SHIFT 2 1002 #define OMAP4430_IVAHD_DYNDEP_MASK (1 << 2) 1003 1004 /* 1005 * Used by CM_CAM_STATICDEP, CM_D2D_STATICDEP, CM_D2D_STATICDEP_RESTORE, 1006 * CM_DSS_STATICDEP, CM_DUCATI_STATICDEP, CM_GFX_STATICDEP, 1007 * CM_L3INIT_STATICDEP, CM_MPU_STATICDEP, CM_SDMA_STATICDEP, 1008 * CM_SDMA_STATICDEP_RESTORE, CM_TESLA_STATICDEP 1009 */ 1010 #define OMAP4430_IVAHD_STATDEP_SHIFT 2 1011 #define OMAP4430_IVAHD_STATDEP_MASK (1 << 2) 1012 1013 /* 1014 * Used by CM_L3_2_DYNAMICDEP, CM_L3_2_DYNAMICDEP_RESTORE, CM_L4CFG_DYNAMICDEP, 1015 * CM_L4CFG_DYNAMICDEP_RESTORE, CM_L4PER_DYNAMICDEP, CM_L4PER_DYNAMICDEP_RESTORE 1016 */ 1017 #define OMAP4430_L3INIT_DYNDEP_SHIFT 7 1018 #define OMAP4430_L3INIT_DYNDEP_MASK (1 << 7) 1019 1020 /* 1021 * Used by CM_D2D_STATICDEP, CM_D2D_STATICDEP_RESTORE, CM_DUCATI_STATICDEP, 1022 * CM_MPU_STATICDEP, CM_SDMA_STATICDEP, CM_SDMA_STATICDEP_RESTORE, 1023 * CM_TESLA_STATICDEP 1024 */ 1025 #define OMAP4430_L3INIT_STATDEP_SHIFT 7 1026 #define OMAP4430_L3INIT_STATDEP_MASK (1 << 7) 1027 1028 /* 1029 * Used by CM_DSS_DYNAMICDEP, CM_L3INIT_DYNAMICDEP, CM_L3_2_DYNAMICDEP, 1030 * CM_L3_2_DYNAMICDEP_RESTORE, CM_L4CFG_DYNAMICDEP, 1031 * CM_L4CFG_DYNAMICDEP_RESTORE, CM_MPU_DYNAMICDEP, CM_TESLA_DYNAMICDEP 1032 */ 1033 #define OMAP4430_L3_1_DYNDEP_SHIFT 5 1034 #define OMAP4430_L3_1_DYNDEP_MASK (1 << 5) 1035 1036 /* 1037 * Used by CM_CAM_STATICDEP, CM_D2D_STATICDEP, CM_D2D_STATICDEP_RESTORE, 1038 * CM_DSS_STATICDEP, CM_DUCATI_STATICDEP, CM_GFX_STATICDEP, CM_IVAHD_STATICDEP, 1039 * CM_L3INIT_STATICDEP, CM_L4SEC_STATICDEP, CM_MPU_STATICDEP, 1040 * CM_SDMA_STATICDEP, CM_SDMA_STATICDEP_RESTORE, CM_TESLA_STATICDEP 1041 */ 1042 #define OMAP4430_L3_1_STATDEP_SHIFT 5 1043 #define OMAP4430_L3_1_STATDEP_MASK (1 << 5) 1044 1045 /* 1046 * Used by CM_CAM_DYNAMICDEP, CM_D2D_DYNAMICDEP, CM_D2D_DYNAMICDEP_RESTORE, 1047 * CM_DUCATI_DYNAMICDEP, CM_EMU_DYNAMICDEP, CM_GFX_DYNAMICDEP, 1048 * CM_IVAHD_DYNAMICDEP, CM_L3INIT_DYNAMICDEP, CM_L3_1_DYNAMICDEP, 1049 * CM_L3_1_DYNAMICDEP_RESTORE, CM_L4CFG_DYNAMICDEP, 1050 * CM_L4CFG_DYNAMICDEP_RESTORE, CM_L4SEC_DYNAMICDEP, CM_SDMA_DYNAMICDEP 1051 */ 1052 #define OMAP4430_L3_2_DYNDEP_SHIFT 6 1053 #define OMAP4430_L3_2_DYNDEP_MASK (1 << 6) 1054 1055 /* 1056 * Used by CM_CAM_STATICDEP, CM_D2D_STATICDEP, CM_D2D_STATICDEP_RESTORE, 1057 * CM_DSS_STATICDEP, CM_DUCATI_STATICDEP, CM_GFX_STATICDEP, CM_IVAHD_STATICDEP, 1058 * CM_L3INIT_STATICDEP, CM_L4SEC_STATICDEP, CM_MPU_STATICDEP, 1059 * CM_SDMA_STATICDEP, CM_SDMA_STATICDEP_RESTORE, CM_TESLA_STATICDEP 1060 */ 1061 #define OMAP4430_L3_2_STATDEP_SHIFT 6 1062 #define OMAP4430_L3_2_STATDEP_MASK (1 << 6) 1063 1064 /* Used by CM_L3_1_DYNAMICDEP, CM_L3_1_DYNAMICDEP_RESTORE */ 1065 #define OMAP4430_L4CFG_DYNDEP_SHIFT 12 1066 #define OMAP4430_L4CFG_DYNDEP_MASK (1 << 12) 1067 1068 /* 1069 * Used by CM_D2D_STATICDEP, CM_D2D_STATICDEP_RESTORE, CM_DUCATI_STATICDEP, 1070 * CM_L3INIT_STATICDEP, CM_MPU_STATICDEP, CM_SDMA_STATICDEP, 1071 * CM_SDMA_STATICDEP_RESTORE, CM_TESLA_STATICDEP 1072 */ 1073 #define OMAP4430_L4CFG_STATDEP_SHIFT 12 1074 #define OMAP4430_L4CFG_STATDEP_MASK (1 << 12) 1075 1076 /* Used by CM_L3_2_DYNAMICDEP, CM_L3_2_DYNAMICDEP_RESTORE */ 1077 #define OMAP4430_L4PER_DYNDEP_SHIFT 13 1078 #define OMAP4430_L4PER_DYNDEP_MASK (1 << 13) 1079 1080 /* 1081 * Used by CM_D2D_STATICDEP, CM_D2D_STATICDEP_RESTORE, CM_DUCATI_STATICDEP, 1082 * CM_L3INIT_STATICDEP, CM_L4SEC_STATICDEP, CM_MPU_STATICDEP, 1083 * CM_SDMA_STATICDEP, CM_SDMA_STATICDEP_RESTORE, CM_TESLA_STATICDEP 1084 */ 1085 #define OMAP4430_L4PER_STATDEP_SHIFT 13 1086 #define OMAP4430_L4PER_STATDEP_MASK (1 << 13) 1087 1088 /* 1089 * Used by CM_L3_2_DYNAMICDEP, CM_L3_2_DYNAMICDEP_RESTORE, CM_L4PER_DYNAMICDEP, 1090 * CM_L4PER_DYNAMICDEP_RESTORE 1091 */ 1092 #define OMAP4430_L4SEC_DYNDEP_SHIFT 14 1093 #define OMAP4430_L4SEC_DYNDEP_MASK (1 << 14) 1094 1095 /* 1096 * Used by CM_DUCATI_STATICDEP, CM_L3INIT_STATICDEP, CM_MPU_STATICDEP, 1097 * CM_SDMA_STATICDEP, CM_SDMA_STATICDEP_RESTORE 1098 */ 1099 #define OMAP4430_L4SEC_STATDEP_SHIFT 14 1100 #define OMAP4430_L4SEC_STATDEP_MASK (1 << 14) 1101 1102 /* Used by CM_L4CFG_DYNAMICDEP, CM_L4CFG_DYNAMICDEP_RESTORE */ 1103 #define OMAP4430_L4WKUP_DYNDEP_SHIFT 15 1104 #define OMAP4430_L4WKUP_DYNDEP_MASK (1 << 15) 1105 1106 /* 1107 * Used by CM_DUCATI_STATICDEP, CM_L3INIT_STATICDEP, CM_MPU_STATICDEP, 1108 * CM_SDMA_STATICDEP, CM_SDMA_STATICDEP_RESTORE, CM_TESLA_STATICDEP 1109 */ 1110 #define OMAP4430_L4WKUP_STATDEP_SHIFT 15 1111 #define OMAP4430_L4WKUP_STATDEP_MASK (1 << 15) 1112 1113 /* 1114 * Used by CM_D2D_DYNAMICDEP, CM_D2D_DYNAMICDEP_RESTORE, CM_L3_1_DYNAMICDEP, 1115 * CM_L3_1_DYNAMICDEP_RESTORE, CM_L4CFG_DYNAMICDEP, 1116 * CM_L4CFG_DYNAMICDEP_RESTORE, CM_MPU_DYNAMICDEP 1117 */ 1118 #define OMAP4430_MEMIF_DYNDEP_SHIFT 4 1119 #define OMAP4430_MEMIF_DYNDEP_MASK (1 << 4) 1120 1121 /* 1122 * Used by CM_CAM_STATICDEP, CM_D2D_STATICDEP, CM_D2D_STATICDEP_RESTORE, 1123 * CM_DSS_STATICDEP, CM_DUCATI_STATICDEP, CM_GFX_STATICDEP, CM_IVAHD_STATICDEP, 1124 * CM_L3INIT_STATICDEP, CM_L4SEC_STATICDEP, CM_MPU_STATICDEP, 1125 * CM_SDMA_STATICDEP, CM_SDMA_STATICDEP_RESTORE, CM_TESLA_STATICDEP 1126 */ 1127 #define OMAP4430_MEMIF_STATDEP_SHIFT 4 1128 #define OMAP4430_MEMIF_STATDEP_MASK (1 << 4) 1129 1130 /* 1131 * Used by CM_SSC_MODFREQDIV_DPLL_ABE, CM_SSC_MODFREQDIV_DPLL_CORE, 1132 * CM_SSC_MODFREQDIV_DPLL_CORE_RESTORE, CM_SSC_MODFREQDIV_DPLL_DDRPHY, 1133 * CM_SSC_MODFREQDIV_DPLL_IVA, CM_SSC_MODFREQDIV_DPLL_MPU, 1134 * CM_SSC_MODFREQDIV_DPLL_PER, CM_SSC_MODFREQDIV_DPLL_UNIPRO, 1135 * CM_SSC_MODFREQDIV_DPLL_USB 1136 */ 1137 #define OMAP4430_MODFREQDIV_EXPONENT_SHIFT 8 1138 #define OMAP4430_MODFREQDIV_EXPONENT_MASK (0x7 << 8) 1139 1140 /* 1141 * Used by CM_SSC_MODFREQDIV_DPLL_ABE, CM_SSC_MODFREQDIV_DPLL_CORE, 1142 * CM_SSC_MODFREQDIV_DPLL_CORE_RESTORE, CM_SSC_MODFREQDIV_DPLL_DDRPHY, 1143 * CM_SSC_MODFREQDIV_DPLL_IVA, CM_SSC_MODFREQDIV_DPLL_MPU, 1144 * CM_SSC_MODFREQDIV_DPLL_PER, CM_SSC_MODFREQDIV_DPLL_UNIPRO, 1145 * CM_SSC_MODFREQDIV_DPLL_USB 1146 */ 1147 #define OMAP4430_MODFREQDIV_MANTISSA_SHIFT 0 1148 #define OMAP4430_MODFREQDIV_MANTISSA_MASK (0x7f << 0) 1149 1150 /* 1151 * Used by CM1_ABE_AESS_CLKCTRL, CM1_ABE_DMIC_CLKCTRL, CM1_ABE_L4ABE_CLKCTRL, 1152 * CM1_ABE_MCASP_CLKCTRL, CM1_ABE_MCBSP1_CLKCTRL, CM1_ABE_MCBSP2_CLKCTRL, 1153 * CM1_ABE_MCBSP3_CLKCTRL, CM1_ABE_PDM_CLKCTRL, CM1_ABE_SLIMBUS_CLKCTRL, 1154 * CM1_ABE_TIMER5_CLKCTRL, CM1_ABE_TIMER6_CLKCTRL, CM1_ABE_TIMER7_CLKCTRL, 1155 * CM1_ABE_TIMER8_CLKCTRL, CM1_ABE_WDT3_CLKCTRL, CM_ALWON_MDMINTC_CLKCTRL, 1156 * CM_ALWON_SR_CORE_CLKCTRL, CM_ALWON_SR_IVA_CLKCTRL, CM_ALWON_SR_MPU_CLKCTRL, 1157 * CM_CAM_FDIF_CLKCTRL, CM_CAM_ISS_CLKCTRL, CM_CEFUSE_CEFUSE_CLKCTRL, 1158 * CM_CM1_PROFILING_CLKCTRL, CM_CM1_PROFILING_CLKCTRL_RESTORE, 1159 * CM_CM2_PROFILING_CLKCTRL, CM_CM2_PROFILING_CLKCTRL_RESTORE, 1160 * CM_D2D_MODEM_ICR_CLKCTRL, CM_D2D_SAD2D_CLKCTRL, CM_D2D_SAD2D_FW_CLKCTRL, 1161 * CM_DSS_DEISS_CLKCTRL, CM_DSS_DSS_CLKCTRL, CM_DUCATI_DUCATI_CLKCTRL, 1162 * CM_EMU_DEBUGSS_CLKCTRL, CM_GFX_GFX_CLKCTRL, CM_IVAHD_IVAHD_CLKCTRL, 1163 * CM_IVAHD_SL2_CLKCTRL, CM_L3INIT_CCPTX_CLKCTRL, CM_L3INIT_EMAC_CLKCTRL, 1164 * CM_L3INIT_HSI_CLKCTRL, CM_L3INIT_MMC1_CLKCTRL, CM_L3INIT_MMC2_CLKCTRL, 1165 * CM_L3INIT_MMC6_CLKCTRL, CM_L3INIT_P1500_CLKCTRL, CM_L3INIT_PCIESS_CLKCTRL, 1166 * CM_L3INIT_SATA_CLKCTRL, CM_L3INIT_TPPSS_CLKCTRL, CM_L3INIT_UNIPRO1_CLKCTRL, 1167 * CM_L3INIT_USBPHYOCP2SCP_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL, 1168 * CM_L3INIT_USB_HOST_CLKCTRL_RESTORE, CM_L3INIT_USB_HOST_FS_CLKCTRL, 1169 * CM_L3INIT_USB_OTG_CLKCTRL, CM_L3INIT_USB_TLL_CLKCTRL, 1170 * CM_L3INIT_USB_TLL_CLKCTRL_RESTORE, CM_L3INIT_XHPI_CLKCTRL, 1171 * CM_L3INSTR_L3_3_CLKCTRL, CM_L3INSTR_L3_3_CLKCTRL_RESTORE, 1172 * CM_L3INSTR_L3_INSTR_CLKCTRL, CM_L3INSTR_L3_INSTR_CLKCTRL_RESTORE, 1173 * CM_L3INSTR_OCP_WP1_CLKCTRL, CM_L3INSTR_OCP_WP1_CLKCTRL_RESTORE, 1174 * CM_L3_1_L3_1_CLKCTRL, CM_L3_2_GPMC_CLKCTRL, CM_L3_2_L3_2_CLKCTRL, 1175 * CM_L3_2_OCMC_RAM_CLKCTRL, CM_L4CFG_HW_SEM_CLKCTRL, CM_L4CFG_L4_CFG_CLKCTRL, 1176 * CM_L4CFG_MAILBOX_CLKCTRL, CM_L4CFG_SAR_ROM_CLKCTRL, CM_L4PER_ADC_CLKCTRL, 1177 * CM_L4PER_DMTIMER10_CLKCTRL, CM_L4PER_DMTIMER11_CLKCTRL, 1178 * CM_L4PER_DMTIMER2_CLKCTRL, CM_L4PER_DMTIMER3_CLKCTRL, 1179 * CM_L4PER_DMTIMER4_CLKCTRL, CM_L4PER_DMTIMER9_CLKCTRL, CM_L4PER_ELM_CLKCTRL, 1180 * CM_L4PER_GPIO2_CLKCTRL, CM_L4PER_GPIO2_CLKCTRL_RESTORE, 1181 * CM_L4PER_GPIO3_CLKCTRL, CM_L4PER_GPIO3_CLKCTRL_RESTORE, 1182 * CM_L4PER_GPIO4_CLKCTRL, CM_L4PER_GPIO4_CLKCTRL_RESTORE, 1183 * CM_L4PER_GPIO5_CLKCTRL, CM_L4PER_GPIO5_CLKCTRL_RESTORE, 1184 * CM_L4PER_GPIO6_CLKCTRL, CM_L4PER_GPIO6_CLKCTRL_RESTORE, 1185 * CM_L4PER_HDQ1W_CLKCTRL, CM_L4PER_HECC1_CLKCTRL, CM_L4PER_HECC2_CLKCTRL, 1186 * CM_L4PER_I2C1_CLKCTRL, CM_L4PER_I2C2_CLKCTRL, CM_L4PER_I2C3_CLKCTRL, 1187 * CM_L4PER_I2C4_CLKCTRL, CM_L4PER_I2C5_CLKCTRL, CM_L4PER_L4PER_CLKCTRL, 1188 * CM_L4PER_MCASP2_CLKCTRL, CM_L4PER_MCASP3_CLKCTRL, CM_L4PER_MCBSP4_CLKCTRL, 1189 * CM_L4PER_MCSPI1_CLKCTRL, CM_L4PER_MCSPI2_CLKCTRL, CM_L4PER_MCSPI3_CLKCTRL, 1190 * CM_L4PER_MCSPI4_CLKCTRL, CM_L4PER_MGATE_CLKCTRL, CM_L4PER_MMCSD3_CLKCTRL, 1191 * CM_L4PER_MMCSD4_CLKCTRL, CM_L4PER_MMCSD5_CLKCTRL, CM_L4PER_MSPROHG_CLKCTRL, 1192 * CM_L4PER_SLIMBUS2_CLKCTRL, CM_L4PER_UART1_CLKCTRL, CM_L4PER_UART2_CLKCTRL, 1193 * CM_L4PER_UART3_CLKCTRL, CM_L4PER_UART4_CLKCTRL, CM_L4SEC_AES1_CLKCTRL, 1194 * CM_L4SEC_AES2_CLKCTRL, CM_L4SEC_CRYPTODMA_CLKCTRL, CM_L4SEC_DES3DES_CLKCTRL, 1195 * CM_L4SEC_PKAEIP29_CLKCTRL, CM_L4SEC_RNG_CLKCTRL, CM_L4SEC_SHA2MD51_CLKCTRL, 1196 * CM_MEMIF_DMM_CLKCTRL, CM_MEMIF_EMIF_1_CLKCTRL, CM_MEMIF_EMIF_2_CLKCTRL, 1197 * CM_MEMIF_EMIF_FW_CLKCTRL, CM_MEMIF_EMIF_H1_CLKCTRL, 1198 * CM_MEMIF_EMIF_H2_CLKCTRL, CM_MPU_MPU_CLKCTRL, CM_SDMA_SDMA_CLKCTRL, 1199 * CM_TESLA_TESLA_CLKCTRL, CM_WKUP_GPIO1_CLKCTRL, CM_WKUP_KEYBOARD_CLKCTRL, 1200 * CM_WKUP_L4WKUP_CLKCTRL, CM_WKUP_RTC_CLKCTRL, CM_WKUP_SARRAM_CLKCTRL, 1201 * CM_WKUP_SYNCTIMER_CLKCTRL, CM_WKUP_TIMER12_CLKCTRL, CM_WKUP_TIMER1_CLKCTRL, 1202 * CM_WKUP_USIM_CLKCTRL, CM_WKUP_WDT1_CLKCTRL, CM_WKUP_WDT2_CLKCTRL 1203 */ 1204 #define OMAP4430_MODULEMODE_SHIFT 0 1205 #define OMAP4430_MODULEMODE_MASK (0x3 << 0) 1206 1207 /* Used by CM_DSS_DSS_CLKCTRL */ 1208 #define OMAP4430_OPTFCLKEN_48MHZ_CLK_SHIFT 9 1209 #define OMAP4430_OPTFCLKEN_48MHZ_CLK_MASK (1 << 9) 1210 1211 /* Used by CM_WKUP_BANDGAP_CLKCTRL */ 1212 #define OMAP4430_OPTFCLKEN_BGAP_32K_SHIFT 8 1213 #define OMAP4430_OPTFCLKEN_BGAP_32K_MASK (1 << 8) 1214 1215 /* Used by CM_ALWON_USBPHY_CLKCTRL */ 1216 #define OMAP4430_OPTFCLKEN_CLK32K_SHIFT 8 1217 #define OMAP4430_OPTFCLKEN_CLK32K_MASK (1 << 8) 1218 1219 /* Used by CM_CAM_ISS_CLKCTRL */ 1220 #define OMAP4430_OPTFCLKEN_CTRLCLK_SHIFT 8 1221 #define OMAP4430_OPTFCLKEN_CTRLCLK_MASK (1 << 8) 1222 1223 /* 1224 * Used by CM_L4PER_GPIO2_CLKCTRL, CM_L4PER_GPIO2_CLKCTRL_RESTORE, 1225 * CM_L4PER_GPIO3_CLKCTRL, CM_L4PER_GPIO3_CLKCTRL_RESTORE, 1226 * CM_L4PER_GPIO4_CLKCTRL, CM_L4PER_GPIO4_CLKCTRL_RESTORE, 1227 * CM_L4PER_GPIO5_CLKCTRL, CM_L4PER_GPIO5_CLKCTRL_RESTORE, 1228 * CM_L4PER_GPIO6_CLKCTRL, CM_L4PER_GPIO6_CLKCTRL_RESTORE, CM_WKUP_GPIO1_CLKCTRL 1229 */ 1230 #define OMAP4430_OPTFCLKEN_DBCLK_SHIFT 8 1231 #define OMAP4430_OPTFCLKEN_DBCLK_MASK (1 << 8) 1232 1233 /* Used by CM_MEMIF_DLL_CLKCTRL, CM_MEMIF_DLL_H_CLKCTRL */ 1234 #define OMAP4430_OPTFCLKEN_DLL_CLK_SHIFT 8 1235 #define OMAP4430_OPTFCLKEN_DLL_CLK_MASK (1 << 8) 1236 1237 /* Used by CM_DSS_DSS_CLKCTRL */ 1238 #define OMAP4430_OPTFCLKEN_DSSCLK_SHIFT 8 1239 #define OMAP4430_OPTFCLKEN_DSSCLK_MASK (1 << 8) 1240 1241 /* Used by CM_WKUP_USIM_CLKCTRL */ 1242 #define OMAP4430_OPTFCLKEN_FCLK_SHIFT 8 1243 #define OMAP4430_OPTFCLKEN_FCLK_MASK (1 << 8) 1244 1245 /* Used by CM1_ABE_SLIMBUS_CLKCTRL */ 1246 #define OMAP4430_OPTFCLKEN_FCLK0_SHIFT 8 1247 #define OMAP4430_OPTFCLKEN_FCLK0_MASK (1 << 8) 1248 1249 /* Used by CM1_ABE_SLIMBUS_CLKCTRL */ 1250 #define OMAP4430_OPTFCLKEN_FCLK1_SHIFT 9 1251 #define OMAP4430_OPTFCLKEN_FCLK1_MASK (1 << 9) 1252 1253 /* Used by CM1_ABE_SLIMBUS_CLKCTRL */ 1254 #define OMAP4430_OPTFCLKEN_FCLK2_SHIFT 10 1255 #define OMAP4430_OPTFCLKEN_FCLK2_MASK (1 << 10) 1256 1257 /* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */ 1258 #define OMAP4430_OPTFCLKEN_FUNC48MCLK_SHIFT 15 1259 #define OMAP4430_OPTFCLKEN_FUNC48MCLK_MASK (1 << 15) 1260 1261 /* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */ 1262 #define OMAP4430_OPTFCLKEN_HSIC480M_P1_CLK_SHIFT 13 1263 #define OMAP4430_OPTFCLKEN_HSIC480M_P1_CLK_MASK (1 << 13) 1264 1265 /* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */ 1266 #define OMAP4430_OPTFCLKEN_HSIC480M_P2_CLK_SHIFT 14 1267 #define OMAP4430_OPTFCLKEN_HSIC480M_P2_CLK_MASK (1 << 14) 1268 1269 /* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */ 1270 #define OMAP4430_OPTFCLKEN_HSIC60M_P1_CLK_SHIFT 11 1271 #define OMAP4430_OPTFCLKEN_HSIC60M_P1_CLK_MASK (1 << 11) 1272 1273 /* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */ 1274 #define OMAP4430_OPTFCLKEN_HSIC60M_P2_CLK_SHIFT 12 1275 #define OMAP4430_OPTFCLKEN_HSIC60M_P2_CLK_MASK (1 << 12) 1276 1277 /* Used by CM_L4PER_SLIMBUS2_CLKCTRL */ 1278 #define OMAP4430_OPTFCLKEN_PER24MC_GFCLK_SHIFT 8 1279 #define OMAP4430_OPTFCLKEN_PER24MC_GFCLK_MASK (1 << 8) 1280 1281 /* Used by CM_L4PER_SLIMBUS2_CLKCTRL */ 1282 #define OMAP4430_OPTFCLKEN_PERABE24M_GFCLK_SHIFT 9 1283 #define OMAP4430_OPTFCLKEN_PERABE24M_GFCLK_MASK (1 << 9) 1284 1285 /* Used by CM_L3INIT_USBPHYOCP2SCP_CLKCTRL */ 1286 #define OMAP4430_OPTFCLKEN_PHY_48M_SHIFT 8 1287 #define OMAP4430_OPTFCLKEN_PHY_48M_MASK (1 << 8) 1288 1289 /* Used by CM_L4PER_SLIMBUS2_CLKCTRL */ 1290 #define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_SHIFT 10 1291 #define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_MASK (1 << 10) 1292 1293 /* Renamed from OPTFCLKEN_SLIMBUS_CLK Used by CM1_ABE_SLIMBUS_CLKCTRL */ 1294 #define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_11_11_SHIFT 11 1295 #define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_11_11_MASK (1 << 11) 1296 1297 /* Used by CM_DSS_DSS_CLKCTRL */ 1298 #define OMAP4430_OPTFCLKEN_SYS_CLK_SHIFT 10 1299 #define OMAP4430_OPTFCLKEN_SYS_CLK_MASK (1 << 10) 1300 1301 /* Used by CM_DSS_DSS_CLKCTRL */ 1302 #define OMAP4430_OPTFCLKEN_TV_CLK_SHIFT 11 1303 #define OMAP4430_OPTFCLKEN_TV_CLK_MASK (1 << 11) 1304 1305 /* Used by CM_L3INIT_UNIPRO1_CLKCTRL */ 1306 #define OMAP4430_OPTFCLKEN_TXPHYCLK_SHIFT 8 1307 #define OMAP4430_OPTFCLKEN_TXPHYCLK_MASK (1 << 8) 1308 1309 /* Used by CM_L3INIT_USB_TLL_CLKCTRL, CM_L3INIT_USB_TLL_CLKCTRL_RESTORE */ 1310 #define OMAP4430_OPTFCLKEN_USB_CH0_CLK_SHIFT 8 1311 #define OMAP4430_OPTFCLKEN_USB_CH0_CLK_MASK (1 << 8) 1312 1313 /* Used by CM_L3INIT_USB_TLL_CLKCTRL, CM_L3INIT_USB_TLL_CLKCTRL_RESTORE */ 1314 #define OMAP4430_OPTFCLKEN_USB_CH1_CLK_SHIFT 9 1315 #define OMAP4430_OPTFCLKEN_USB_CH1_CLK_MASK (1 << 9) 1316 1317 /* Used by CM_L3INIT_USB_TLL_CLKCTRL, CM_L3INIT_USB_TLL_CLKCTRL_RESTORE */ 1318 #define OMAP4430_OPTFCLKEN_USB_CH2_CLK_SHIFT 10 1319 #define OMAP4430_OPTFCLKEN_USB_CH2_CLK_MASK (1 << 10) 1320 1321 /* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */ 1322 #define OMAP4430_OPTFCLKEN_UTMI_P1_CLK_SHIFT 8 1323 #define OMAP4430_OPTFCLKEN_UTMI_P1_CLK_MASK (1 << 8) 1324 1325 /* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */ 1326 #define OMAP4430_OPTFCLKEN_UTMI_P2_CLK_SHIFT 9 1327 #define OMAP4430_OPTFCLKEN_UTMI_P2_CLK_MASK (1 << 9) 1328 1329 /* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */ 1330 #define OMAP4430_OPTFCLKEN_UTMI_P3_CLK_SHIFT 10 1331 #define OMAP4430_OPTFCLKEN_UTMI_P3_CLK_MASK (1 << 10) 1332 1333 /* Used by CM_L3INIT_USB_OTG_CLKCTRL */ 1334 #define OMAP4430_OPTFCLKEN_XCLK_SHIFT 8 1335 #define OMAP4430_OPTFCLKEN_XCLK_MASK (1 << 8) 1336 1337 /* Used by CM_EMU_OVERRIDE_DPLL_CORE */ 1338 #define OMAP4430_OVERRIDE_ENABLE_SHIFT 19 1339 #define OMAP4430_OVERRIDE_ENABLE_MASK (1 << 19) 1340 1341 /* Used by CM_CLKSEL_ABE */ 1342 #define OMAP4430_PAD_CLKS_GATE_SHIFT 8 1343 #define OMAP4430_PAD_CLKS_GATE_MASK (1 << 8) 1344 1345 /* Used by CM_CORE_DVFS_CURRENT, CM_IVA_DVFS_CURRENT */ 1346 #define OMAP4430_PERF_CURRENT_SHIFT 0 1347 #define OMAP4430_PERF_CURRENT_MASK (0xff << 0) 1348 1349 /* 1350 * Used by CM_CORE_DVFS_PERF1, CM_CORE_DVFS_PERF2, CM_CORE_DVFS_PERF3, 1351 * CM_CORE_DVFS_PERF4, CM_IVA_DVFS_PERF_ABE, CM_IVA_DVFS_PERF_IVAHD, 1352 * CM_IVA_DVFS_PERF_TESLA 1353 */ 1354 #define OMAP4430_PERF_REQ_SHIFT 0 1355 #define OMAP4430_PERF_REQ_MASK (0xff << 0) 1356 1357 /* Used by CM_RESTORE_ST */ 1358 #define OMAP4430_PHASE1_COMPLETED_SHIFT 0 1359 #define OMAP4430_PHASE1_COMPLETED_MASK (1 << 0) 1360 1361 /* Used by CM_RESTORE_ST */ 1362 #define OMAP4430_PHASE2A_COMPLETED_SHIFT 1 1363 #define OMAP4430_PHASE2A_COMPLETED_MASK (1 << 1) 1364 1365 /* Used by CM_RESTORE_ST */ 1366 #define OMAP4430_PHASE2B_COMPLETED_SHIFT 2 1367 #define OMAP4430_PHASE2B_COMPLETED_MASK (1 << 2) 1368 1369 /* Used by CM_EMU_DEBUGSS_CLKCTRL */ 1370 #define OMAP4430_PMD_STM_MUX_CTRL_SHIFT 20 1371 #define OMAP4430_PMD_STM_MUX_CTRL_MASK (0x3 << 20) 1372 1373 /* Used by CM_EMU_DEBUGSS_CLKCTRL */ 1374 #define OMAP4430_PMD_TRACE_MUX_CTRL_SHIFT 22 1375 #define OMAP4430_PMD_TRACE_MUX_CTRL_MASK (0x3 << 22) 1376 1377 /* Used by CM_DYN_DEP_PRESCAL, CM_DYN_DEP_PRESCAL_RESTORE */ 1378 #define OMAP4430_PRESCAL_SHIFT 0 1379 #define OMAP4430_PRESCAL_MASK (0x3f << 0) 1380 1381 /* Used by REVISION_CM1, REVISION_CM2 */ 1382 #define OMAP4430_R_RTL_SHIFT 11 1383 #define OMAP4430_R_RTL_MASK (0x1f << 11) 1384 1385 /* 1386 * Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE, 1387 * CM_L3INIT_USB_TLL_CLKCTRL, CM_L3INIT_USB_TLL_CLKCTRL_RESTORE 1388 */ 1389 #define OMAP4430_SAR_MODE_SHIFT 4 1390 #define OMAP4430_SAR_MODE_MASK (1 << 4) 1391 1392 /* Used by CM_SCALE_FCLK */ 1393 #define OMAP4430_SCALE_FCLK_SHIFT 0 1394 #define OMAP4430_SCALE_FCLK_MASK (1 << 0) 1395 1396 /* Used by REVISION_CM1, REVISION_CM2 */ 1397 #define OMAP4430_SCHEME_SHIFT 30 1398 #define OMAP4430_SCHEME_MASK (0x3 << 30) 1399 1400 /* Used by CM_L4CFG_DYNAMICDEP, CM_L4CFG_DYNAMICDEP_RESTORE */ 1401 #define OMAP4430_SDMA_DYNDEP_SHIFT 11 1402 #define OMAP4430_SDMA_DYNDEP_MASK (1 << 11) 1403 1404 /* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP */ 1405 #define OMAP4430_SDMA_STATDEP_SHIFT 11 1406 #define OMAP4430_SDMA_STATDEP_MASK (1 << 11) 1407 1408 /* Used by CM_CLKSEL_ABE */ 1409 #define OMAP4430_SLIMBUS_CLK_GATE_SHIFT 10 1410 #define OMAP4430_SLIMBUS_CLK_GATE_MASK (1 << 10) 1411 1412 /* 1413 * Used by CM1_ABE_AESS_CLKCTRL, CM_CAM_FDIF_CLKCTRL, CM_CAM_ISS_CLKCTRL, 1414 * CM_D2D_SAD2D_CLKCTRL, CM_DSS_DEISS_CLKCTRL, CM_DSS_DSS_CLKCTRL, 1415 * CM_DUCATI_DUCATI_CLKCTRL, CM_EMU_DEBUGSS_CLKCTRL, CM_GFX_GFX_CLKCTRL, 1416 * CM_IVAHD_IVAHD_CLKCTRL, CM_L3INIT_CCPTX_CLKCTRL, CM_L3INIT_EMAC_CLKCTRL, 1417 * CM_L3INIT_HSI_CLKCTRL, CM_L3INIT_MMC1_CLKCTRL, CM_L3INIT_MMC2_CLKCTRL, 1418 * CM_L3INIT_MMC6_CLKCTRL, CM_L3INIT_P1500_CLKCTRL, CM_L3INIT_PCIESS_CLKCTRL, 1419 * CM_L3INIT_SATA_CLKCTRL, CM_L3INIT_TPPSS_CLKCTRL, CM_L3INIT_UNIPRO1_CLKCTRL, 1420 * CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE, 1421 * CM_L3INIT_USB_HOST_FS_CLKCTRL, CM_L3INIT_USB_OTG_CLKCTRL, 1422 * CM_L3INIT_XHPI_CLKCTRL, CM_L4SEC_CRYPTODMA_CLKCTRL, CM_MPU_MPU_CLKCTRL, 1423 * CM_SDMA_SDMA_CLKCTRL, CM_TESLA_TESLA_CLKCTRL 1424 */ 1425 #define OMAP4430_STBYST_SHIFT 18 1426 #define OMAP4430_STBYST_MASK (1 << 18) 1427 1428 /* 1429 * Used by CM_IDLEST_DPLL_ABE, CM_IDLEST_DPLL_CORE, CM_IDLEST_DPLL_DDRPHY, 1430 * CM_IDLEST_DPLL_IVA, CM_IDLEST_DPLL_MPU, CM_IDLEST_DPLL_PER, 1431 * CM_IDLEST_DPLL_UNIPRO, CM_IDLEST_DPLL_USB 1432 */ 1433 #define OMAP4430_ST_DPLL_CLK_SHIFT 0 1434 #define OMAP4430_ST_DPLL_CLK_MASK (1 << 0) 1435 1436 /* Used by CM_CLKDCOLDO_DPLL_USB */ 1437 #define OMAP4430_ST_DPLL_CLKDCOLDO_SHIFT 9 1438 #define OMAP4430_ST_DPLL_CLKDCOLDO_MASK (1 << 9) 1439 1440 /* 1441 * Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE, 1442 * CM_DIV_M2_DPLL_CORE_RESTORE, CM_DIV_M2_DPLL_DDRPHY, CM_DIV_M2_DPLL_MPU, 1443 * CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_USB 1444 */ 1445 #define OMAP4430_ST_DPLL_CLKOUT_SHIFT 9 1446 #define OMAP4430_ST_DPLL_CLKOUT_MASK (1 << 9) 1447 1448 /* 1449 * Used by CM_DIV_M3_DPLL_ABE, CM_DIV_M3_DPLL_CORE, 1450 * CM_DIV_M3_DPLL_CORE_RESTORE, CM_DIV_M3_DPLL_PER 1451 */ 1452 #define OMAP4430_ST_DPLL_CLKOUTHIF_SHIFT 9 1453 #define OMAP4430_ST_DPLL_CLKOUTHIF_MASK (1 << 9) 1454 1455 /* Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_UNIPRO */ 1456 #define OMAP4430_ST_DPLL_CLKOUTX2_SHIFT 11 1457 #define OMAP4430_ST_DPLL_CLKOUTX2_MASK (1 << 11) 1458 1459 /* 1460 * Used by CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_CORE_RESTORE, 1461 * CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA, CM_DIV_M4_DPLL_PER 1462 */ 1463 #define OMAP4430_ST_HSDIVIDER_CLKOUT1_SHIFT 9 1464 #define OMAP4430_ST_HSDIVIDER_CLKOUT1_MASK (1 << 9) 1465 1466 /* 1467 * Used by CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_CORE_RESTORE, 1468 * CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA, CM_DIV_M5_DPLL_PER 1469 */ 1470 #define OMAP4430_ST_HSDIVIDER_CLKOUT2_SHIFT 9 1471 #define OMAP4430_ST_HSDIVIDER_CLKOUT2_MASK (1 << 9) 1472 1473 /* 1474 * Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_CORE_RESTORE, 1475 * CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER 1476 */ 1477 #define OMAP4430_ST_HSDIVIDER_CLKOUT3_SHIFT 9 1478 #define OMAP4430_ST_HSDIVIDER_CLKOUT3_MASK (1 << 9) 1479 1480 /* 1481 * Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_CORE_RESTORE, 1482 * CM_DIV_M7_DPLL_PER 1483 */ 1484 #define OMAP4430_ST_HSDIVIDER_CLKOUT4_SHIFT 9 1485 #define OMAP4430_ST_HSDIVIDER_CLKOUT4_MASK (1 << 9) 1486 1487 /* 1488 * Used by CM_IDLEST_DPLL_ABE, CM_IDLEST_DPLL_CORE, CM_IDLEST_DPLL_DDRPHY, 1489 * CM_IDLEST_DPLL_IVA, CM_IDLEST_DPLL_MPU, CM_IDLEST_DPLL_PER, 1490 * CM_IDLEST_DPLL_UNIPRO, CM_IDLEST_DPLL_USB 1491 */ 1492 #define OMAP4430_ST_MN_BYPASS_SHIFT 8 1493 #define OMAP4430_ST_MN_BYPASS_MASK (1 << 8) 1494 1495 /* Used by CM_SYS_CLKSEL */ 1496 #define OMAP4430_SYS_CLKSEL_SHIFT 0 1497 #define OMAP4430_SYS_CLKSEL_MASK (0x7 << 0) 1498 1499 /* Used by CM_L4CFG_DYNAMICDEP, CM_L4CFG_DYNAMICDEP_RESTORE */ 1500 #define OMAP4430_TESLA_DYNDEP_SHIFT 1 1501 #define OMAP4430_TESLA_DYNDEP_MASK (1 << 1) 1502 1503 /* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP */ 1504 #define OMAP4430_TESLA_STATDEP_SHIFT 1 1505 #define OMAP4430_TESLA_STATDEP_MASK (1 << 1) 1506 1507 /* 1508 * Used by CM_D2D_DYNAMICDEP, CM_D2D_DYNAMICDEP_RESTORE, CM_DUCATI_DYNAMICDEP, 1509 * CM_EMU_DYNAMICDEP, CM_L3_1_DYNAMICDEP, CM_L3_1_DYNAMICDEP_RESTORE, 1510 * CM_L3_2_DYNAMICDEP, CM_L3_2_DYNAMICDEP_RESTORE, CM_L4CFG_DYNAMICDEP, 1511 * CM_L4CFG_DYNAMICDEP_RESTORE, CM_L4PER_DYNAMICDEP, 1512 * CM_L4PER_DYNAMICDEP_RESTORE, CM_MPU_DYNAMICDEP, CM_TESLA_DYNAMICDEP 1513 */ 1514 #define OMAP4430_WINDOWSIZE_SHIFT 24 1515 #define OMAP4430_WINDOWSIZE_MASK (0xf << 24) 1516 1517 /* Used by REVISION_CM1, REVISION_CM2 */ 1518 #define OMAP4430_X_MAJOR_SHIFT 8 1519 #define OMAP4430_X_MAJOR_MASK (0x7 << 8) 1520 1521 /* Used by REVISION_CM1, REVISION_CM2 */ 1522 #define OMAP4430_Y_MINOR_SHIFT 0 1523 #define OMAP4430_Y_MINOR_MASK (0x3f << 0) 1524 #endif 1525