1 /*
2 * linux/arch/arm/mach-omap2/clock.h
3 *
4 * Copyright (C) 2005-2009 Texas Instruments, Inc.
5 * Copyright (C) 2004-2011 Nokia Corporation
6 *
7 * Contacts:
8 * Richard Woodruff <r-woodruff2@ti.com>
9 * Paul Walmsley
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
14 */
15
16 #ifndef __ARCH_ARM_MACH_OMAP2_CLOCK_H
17 #define __ARCH_ARM_MACH_OMAP2_CLOCK_H
18
19 #include <plat/clock.h>
20
21 /* CM_CLKSEL2_PLL.CORE_CLK_SRC bits (2XXX) */
22 #define CORE_CLK_SRC_32K 0x0
23 #define CORE_CLK_SRC_DPLL 0x1
24 #define CORE_CLK_SRC_DPLL_X2 0x2
25
26 /* OMAP2xxx CM_CLKEN_PLL.EN_DPLL bits - for omap2_get_dpll_rate() */
27 #define OMAP2XXX_EN_DPLL_LPBYPASS 0x1
28 #define OMAP2XXX_EN_DPLL_FRBYPASS 0x2
29 #define OMAP2XXX_EN_DPLL_LOCKED 0x3
30
31 /* OMAP3xxx CM_CLKEN_PLL*.EN_*_DPLL bits - for omap2_get_dpll_rate() */
32 #define OMAP3XXX_EN_DPLL_LPBYPASS 0x5
33 #define OMAP3XXX_EN_DPLL_FRBYPASS 0x6
34 #define OMAP3XXX_EN_DPLL_LOCKED 0x7
35
36 /* OMAP4xxx CM_CLKMODE_DPLL*.EN_*_DPLL bits - for omap2_get_dpll_rate() */
37 #define OMAP4XXX_EN_DPLL_MNBYPASS 0x4
38 #define OMAP4XXX_EN_DPLL_LPBYPASS 0x5
39 #define OMAP4XXX_EN_DPLL_FRBYPASS 0x6
40 #define OMAP4XXX_EN_DPLL_LOCKED 0x7
41
42 /* CM_CLKEN_PLL*.EN* bit values - not all are available for every DPLL */
43 #define DPLL_LOW_POWER_STOP 0x1
44 #define DPLL_LOW_POWER_BYPASS 0x5
45 #define DPLL_LOCKED 0x7
46
47 /* DPLL Type and DCO Selection Flags */
48 #define DPLL_J_TYPE 0x1
49
50 int omap2_clk_enable(struct clk *clk);
51 void omap2_clk_disable(struct clk *clk);
52 long omap2_clk_round_rate(struct clk *clk, unsigned long rate);
53 int omap2_clk_set_rate(struct clk *clk, unsigned long rate);
54 int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent);
55 long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate);
56 unsigned long omap3_dpll_recalc(struct clk *clk);
57 unsigned long omap3_clkoutx2_recalc(struct clk *clk);
58 void omap3_dpll_allow_idle(struct clk *clk);
59 void omap3_dpll_deny_idle(struct clk *clk);
60 u32 omap3_dpll_autoidle_read(struct clk *clk);
61 int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate);
62 int omap3_noncore_dpll_enable(struct clk *clk);
63 void omap3_noncore_dpll_disable(struct clk *clk);
64 int omap4_dpllmx_gatectrl_read(struct clk *clk);
65 void omap4_dpllmx_allow_gatectrl(struct clk *clk);
66 void omap4_dpllmx_deny_gatectrl(struct clk *clk);
67
68 #ifdef CONFIG_OMAP_RESET_CLOCKS
69 void omap2_clk_disable_unused(struct clk *clk);
70 #else
71 #define omap2_clk_disable_unused NULL
72 #endif
73
74 void omap2_init_clk_clkdm(struct clk *clk);
75
76 /* clkt_clksel.c public functions */
77 u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate,
78 u32 *new_div);
79 void omap2_init_clksel_parent(struct clk *clk);
80 unsigned long omap2_clksel_recalc(struct clk *clk);
81 long omap2_clksel_round_rate(struct clk *clk, unsigned long target_rate);
82 int omap2_clksel_set_rate(struct clk *clk, unsigned long rate);
83 int omap2_clksel_set_parent(struct clk *clk, struct clk *new_parent);
84
85 /* clkt_iclk.c public functions */
86 extern void omap2_clkt_iclk_allow_idle(struct clk *clk);
87 extern void omap2_clkt_iclk_deny_idle(struct clk *clk);
88
89 u32 omap2_get_dpll_rate(struct clk *clk);
90 void omap2_init_dpll_parent(struct clk *clk);
91
92 int omap2_wait_clock_ready(void __iomem *reg, u32 cval, const char *name);
93
94
95 #ifdef CONFIG_ARCH_OMAP2
96 void omap2xxx_clk_prepare_for_reboot(void);
97 #else
omap2xxx_clk_prepare_for_reboot(void)98 static inline void omap2xxx_clk_prepare_for_reboot(void)
99 {
100 }
101 #endif
102
103 #ifdef CONFIG_ARCH_OMAP3
104 void omap3_clk_prepare_for_reboot(void);
105 #else
omap3_clk_prepare_for_reboot(void)106 static inline void omap3_clk_prepare_for_reboot(void)
107 {
108 }
109 #endif
110
111 #ifdef CONFIG_ARCH_OMAP4
112 void omap4_clk_prepare_for_reboot(void);
113 #else
omap4_clk_prepare_for_reboot(void)114 static inline void omap4_clk_prepare_for_reboot(void)
115 {
116 }
117 #endif
118
119 int omap2_dflt_clk_enable(struct clk *clk);
120 void omap2_dflt_clk_disable(struct clk *clk);
121 void omap2_clk_dflt_find_companion(struct clk *clk, void __iomem **other_reg,
122 u8 *other_bit);
123 void omap2_clk_dflt_find_idlest(struct clk *clk, void __iomem **idlest_reg,
124 u8 *idlest_bit, u8 *idlest_val);
125 int omap2_clk_switch_mpurate_at_boot(const char *mpurate_ck_name);
126 void omap2_clk_print_new_rates(const char *hfclkin_ck_name,
127 const char *core_ck_name,
128 const char *mpu_ck_name);
129
130 extern u8 cpu_mask;
131
132 extern const struct clkops clkops_omap2_dflt_wait;
133 extern const struct clkops clkops_dummy;
134 extern const struct clkops clkops_omap2_dflt;
135
136 extern struct clk_functions omap2_clk_functions;
137 extern struct clk *vclk, *sclk;
138
139 extern const struct clksel_rate gpt_32k_rates[];
140 extern const struct clksel_rate gpt_sys_rates[];
141 extern const struct clksel_rate gfx_l3_rates[];
142 extern const struct clksel_rate dsp_ick_rates[];
143
144 #if defined(CONFIG_ARCH_OMAP2) && defined(CONFIG_CPU_FREQ)
145 extern void omap2_clk_init_cpufreq_table(struct cpufreq_frequency_table **table);
146 extern void omap2_clk_exit_cpufreq_table(struct cpufreq_frequency_table **table);
147 #else
148 #define omap2_clk_init_cpufreq_table 0
149 #define omap2_clk_exit_cpufreq_table 0
150 #endif
151
152 extern const struct clkops clkops_omap2_iclk_dflt_wait;
153 extern const struct clkops clkops_omap2_iclk_dflt;
154 extern const struct clkops clkops_omap2_iclk_idle_only;
155 extern const struct clkops clkops_omap2_mdmclk_dflt_wait;
156 extern const struct clkops clkops_omap2xxx_dpll_ops;
157 extern const struct clkops clkops_omap3_noncore_dpll_ops;
158 extern const struct clkops clkops_omap3_core_dpll_ops;
159 extern const struct clkops clkops_omap4_dpllmx_ops;
160
161 #endif
162