1 /* linux/arch/arm/mach-msm/timer.c
2 *
3 * Copyright (C) 2007 Google, Inc.
4 *
5 * This software is licensed under the terms of the GNU General Public
6 * License version 2, as published by the Free Software Foundation, and
7 * may be copied, distributed, and modified under those terms.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 */
15
16 #include <linux/init.h>
17 #include <linux/time.h>
18 #include <linux/interrupt.h>
19 #include <linux/irq.h>
20 #include <linux/clk.h>
21 #include <linux/clockchips.h>
22 #include <linux/delay.h>
23 #include <linux/io.h>
24
25 #include <asm/mach/time.h>
26 #include <mach/msm_iomap.h>
27 #include <mach/cpu.h>
28
29 #define TIMER_MATCH_VAL 0x0000
30 #define TIMER_COUNT_VAL 0x0004
31 #define TIMER_ENABLE 0x0008
32 #define TIMER_ENABLE_CLR_ON_MATCH_EN 2
33 #define TIMER_ENABLE_EN 1
34 #define TIMER_CLEAR 0x000C
35 #define DGT_CLK_CTL 0x0034
36 enum {
37 DGT_CLK_CTL_DIV_1 = 0,
38 DGT_CLK_CTL_DIV_2 = 1,
39 DGT_CLK_CTL_DIV_3 = 2,
40 DGT_CLK_CTL_DIV_4 = 3,
41 };
42 #define CSR_PROTECTION 0x0020
43 #define CSR_PROTECTION_EN 1
44
45 #define GPT_HZ 32768
46
47 enum timer_location {
48 LOCAL_TIMER = 0,
49 GLOBAL_TIMER = 1,
50 };
51
52 #define MSM_GLOBAL_TIMER MSM_CLOCK_DGT
53
54 /* TODO: Remove these ifdefs */
55 #if defined(CONFIG_ARCH_QSD8X50)
56 #define DGT_HZ (19200000 / 4) /* 19.2 MHz / 4 by default */
57 #define MSM_DGT_SHIFT (0)
58 #elif defined(CONFIG_ARCH_MSM7X30) || defined(CONFIG_ARCH_MSM8X60) || \
59 defined(CONFIG_ARCH_MSM8960)
60 #define DGT_HZ (24576000 / 4) /* 24.576 MHz (LPXO) / 4 by default */
61 #define MSM_DGT_SHIFT (0)
62 #else
63 #define DGT_HZ 19200000 /* 19.2 MHz or 600 KHz after shift */
64 #define MSM_DGT_SHIFT (5)
65 #endif
66
67 struct msm_clock {
68 struct clock_event_device clockevent;
69 struct clocksource clocksource;
70 struct irqaction irq;
71 void __iomem *regbase;
72 uint32_t freq;
73 uint32_t shift;
74 void __iomem *global_counter;
75 void __iomem *local_counter;
76 };
77
78 enum {
79 MSM_CLOCK_GPT,
80 MSM_CLOCK_DGT,
81 NR_TIMERS,
82 };
83
84
85 static struct msm_clock msm_clocks[];
86 static struct clock_event_device *local_clock_event;
87
msm_timer_interrupt(int irq,void * dev_id)88 static irqreturn_t msm_timer_interrupt(int irq, void *dev_id)
89 {
90 struct clock_event_device *evt = dev_id;
91 if (smp_processor_id() != 0)
92 evt = local_clock_event;
93 if (evt->event_handler == NULL)
94 return IRQ_HANDLED;
95 evt->event_handler(evt);
96 return IRQ_HANDLED;
97 }
98
msm_read_timer_count(struct clocksource * cs)99 static cycle_t msm_read_timer_count(struct clocksource *cs)
100 {
101 struct msm_clock *clk = container_of(cs, struct msm_clock, clocksource);
102
103 return readl(clk->global_counter);
104 }
105
clockevent_to_clock(struct clock_event_device * evt)106 static struct msm_clock *clockevent_to_clock(struct clock_event_device *evt)
107 {
108 #ifdef CONFIG_SMP
109 int i;
110 for (i = 0; i < NR_TIMERS; i++)
111 if (evt == &(msm_clocks[i].clockevent))
112 return &msm_clocks[i];
113 return &msm_clocks[MSM_GLOBAL_TIMER];
114 #else
115 return container_of(evt, struct msm_clock, clockevent);
116 #endif
117 }
118
msm_timer_set_next_event(unsigned long cycles,struct clock_event_device * evt)119 static int msm_timer_set_next_event(unsigned long cycles,
120 struct clock_event_device *evt)
121 {
122 struct msm_clock *clock = clockevent_to_clock(evt);
123 uint32_t now = readl(clock->local_counter);
124 uint32_t alarm = now + (cycles << clock->shift);
125
126 writel(alarm, clock->regbase + TIMER_MATCH_VAL);
127 return 0;
128 }
129
msm_timer_set_mode(enum clock_event_mode mode,struct clock_event_device * evt)130 static void msm_timer_set_mode(enum clock_event_mode mode,
131 struct clock_event_device *evt)
132 {
133 struct msm_clock *clock = clockevent_to_clock(evt);
134
135 switch (mode) {
136 case CLOCK_EVT_MODE_RESUME:
137 case CLOCK_EVT_MODE_PERIODIC:
138 break;
139 case CLOCK_EVT_MODE_ONESHOT:
140 writel(TIMER_ENABLE_EN, clock->regbase + TIMER_ENABLE);
141 break;
142 case CLOCK_EVT_MODE_UNUSED:
143 case CLOCK_EVT_MODE_SHUTDOWN:
144 writel(0, clock->regbase + TIMER_ENABLE);
145 break;
146 }
147 }
148
149 static struct msm_clock msm_clocks[] = {
150 [MSM_CLOCK_GPT] = {
151 .clockevent = {
152 .name = "gp_timer",
153 .features = CLOCK_EVT_FEAT_ONESHOT,
154 .shift = 32,
155 .rating = 200,
156 .set_next_event = msm_timer_set_next_event,
157 .set_mode = msm_timer_set_mode,
158 },
159 .clocksource = {
160 .name = "gp_timer",
161 .rating = 200,
162 .read = msm_read_timer_count,
163 .mask = CLOCKSOURCE_MASK(32),
164 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
165 },
166 .irq = {
167 .name = "gp_timer",
168 .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_TRIGGER_RISING,
169 .handler = msm_timer_interrupt,
170 .dev_id = &msm_clocks[0].clockevent,
171 .irq = INT_GP_TIMER_EXP
172 },
173 .freq = GPT_HZ,
174 },
175 [MSM_CLOCK_DGT] = {
176 .clockevent = {
177 .name = "dg_timer",
178 .features = CLOCK_EVT_FEAT_ONESHOT,
179 .shift = 32 + MSM_DGT_SHIFT,
180 .rating = 300,
181 .set_next_event = msm_timer_set_next_event,
182 .set_mode = msm_timer_set_mode,
183 },
184 .clocksource = {
185 .name = "dg_timer",
186 .rating = 300,
187 .read = msm_read_timer_count,
188 .mask = CLOCKSOURCE_MASK((32 - MSM_DGT_SHIFT)),
189 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
190 },
191 .irq = {
192 .name = "dg_timer",
193 .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_TRIGGER_RISING,
194 .handler = msm_timer_interrupt,
195 .dev_id = &msm_clocks[1].clockevent,
196 .irq = INT_DEBUG_TIMER_EXP
197 },
198 .freq = DGT_HZ >> MSM_DGT_SHIFT,
199 .shift = MSM_DGT_SHIFT,
200 }
201 };
202
msm_timer_init(void)203 static void __init msm_timer_init(void)
204 {
205 int i;
206 int res;
207 int global_offset = 0;
208
209 if (cpu_is_msm7x01()) {
210 msm_clocks[MSM_CLOCK_GPT].regbase = MSM_CSR_BASE;
211 msm_clocks[MSM_CLOCK_DGT].regbase = MSM_CSR_BASE + 0x10;
212 } else if (cpu_is_msm7x30()) {
213 msm_clocks[MSM_CLOCK_GPT].regbase = MSM_CSR_BASE + 0x04;
214 msm_clocks[MSM_CLOCK_DGT].regbase = MSM_CSR_BASE + 0x24;
215 } else if (cpu_is_qsd8x50()) {
216 msm_clocks[MSM_CLOCK_GPT].regbase = MSM_CSR_BASE;
217 msm_clocks[MSM_CLOCK_DGT].regbase = MSM_CSR_BASE + 0x10;
218 } else if (cpu_is_msm8x60() || cpu_is_msm8960()) {
219 msm_clocks[MSM_CLOCK_GPT].regbase = MSM_TMR_BASE + 0x04;
220 msm_clocks[MSM_CLOCK_DGT].regbase = MSM_TMR_BASE + 0x24;
221
222 /* Use CPU0's timer as the global timer. */
223 global_offset = MSM_TMR0_BASE - MSM_TMR_BASE;
224 } else
225 BUG();
226
227 #ifdef CONFIG_ARCH_MSM_SCORPIONMP
228 writel(DGT_CLK_CTL_DIV_4, MSM_TMR_BASE + DGT_CLK_CTL);
229 #endif
230
231 for (i = 0; i < ARRAY_SIZE(msm_clocks); i++) {
232 struct msm_clock *clock = &msm_clocks[i];
233 struct clock_event_device *ce = &clock->clockevent;
234 struct clocksource *cs = &clock->clocksource;
235
236 clock->local_counter = clock->regbase + TIMER_COUNT_VAL;
237 clock->global_counter = clock->local_counter + global_offset;
238
239 writel(0, clock->regbase + TIMER_ENABLE);
240 writel(0, clock->regbase + TIMER_CLEAR);
241 writel(~0, clock->regbase + TIMER_MATCH_VAL);
242
243 ce->mult = div_sc(clock->freq, NSEC_PER_SEC, ce->shift);
244 /* allow at least 10 seconds to notice that the timer wrapped */
245 ce->max_delta_ns =
246 clockevent_delta2ns(0xf0000000 >> clock->shift, ce);
247 /* 4 gets rounded down to 3 */
248 ce->min_delta_ns = clockevent_delta2ns(4, ce);
249 ce->cpumask = cpumask_of(0);
250
251 res = clocksource_register_hz(cs, clock->freq);
252 if (res)
253 printk(KERN_ERR "msm_timer_init: clocksource_register "
254 "failed for %s\n", cs->name);
255
256 res = setup_irq(clock->irq.irq, &clock->irq);
257 if (res)
258 printk(KERN_ERR "msm_timer_init: setup_irq "
259 "failed for %s\n", cs->name);
260
261 clockevents_register_device(ce);
262 }
263 }
264
265 #ifdef CONFIG_SMP
local_timer_setup(struct clock_event_device * evt)266 int __cpuinit local_timer_setup(struct clock_event_device *evt)
267 {
268 struct msm_clock *clock = &msm_clocks[MSM_GLOBAL_TIMER];
269
270 /* Use existing clock_event for cpu 0 */
271 if (!smp_processor_id())
272 return 0;
273
274 writel(DGT_CLK_CTL_DIV_4, MSM_TMR_BASE + DGT_CLK_CTL);
275
276 if (!local_clock_event) {
277 writel(0, clock->regbase + TIMER_ENABLE);
278 writel(0, clock->regbase + TIMER_CLEAR);
279 writel(~0, clock->regbase + TIMER_MATCH_VAL);
280 }
281 evt->irq = clock->irq.irq;
282 evt->name = "local_timer";
283 evt->features = CLOCK_EVT_FEAT_ONESHOT;
284 evt->rating = clock->clockevent.rating;
285 evt->set_mode = msm_timer_set_mode;
286 evt->set_next_event = msm_timer_set_next_event;
287 evt->shift = clock->clockevent.shift;
288 evt->mult = div_sc(clock->freq, NSEC_PER_SEC, evt->shift);
289 evt->max_delta_ns =
290 clockevent_delta2ns(0xf0000000 >> clock->shift, evt);
291 evt->min_delta_ns = clockevent_delta2ns(4, evt);
292
293 local_clock_event = evt;
294
295 gic_enable_ppi(clock->irq.irq);
296
297 clockevents_register_device(evt);
298 return 0;
299 }
300
local_timer_ack(void)301 inline int local_timer_ack(void)
302 {
303 return 1;
304 }
305
306 #endif
307
308 struct sys_timer msm_timer = {
309 .init = msm_timer_init
310 };
311