1 /* 2 * arch/arm/mach-h720x/include/mach/hardware.h 3 * 4 * Copyright (C) 2000 Jungjun Kim, Hynix Semiconductor Inc. 5 * (C) 2003 Thomas Gleixner <tglx@linutronix.de> 6 * (C) 2003 Robert Schwebel <r.schwebel@pengutronix.de> 7 * 8 * This file contains the hardware definitions of the h720x processors 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License version 2 as 12 * published by the Free Software Foundation. 13 * 14 * Do not add implementations specific defines here. This files contains 15 * only defines of the onchip peripherals. Add those defines to boards.h, 16 * which is included by this file. 17 */ 18 19 #ifndef __ASM_ARCH_HARDWARE_H 20 #define __ASM_ARCH_HARDWARE_H 21 22 #define IOCLK (3686400L) 23 24 /* Onchip peripherals */ 25 26 #define IO_VIRT 0xf0000000 /* IO peripherals */ 27 #define IO_PHYS 0x80000000 28 #define IO_SIZE 0x00050000 29 30 #ifdef CONFIG_CPU_H7202 31 #include "h7202-regs.h" 32 #elif defined CONFIG_CPU_H7201 33 #include "h7201-regs.h" 34 #else 35 #error machine definition mismatch 36 #endif 37 38 /* Macro to access the CPU IO */ 39 #define CPU_IO(x) (*(volatile u32*)(x)) 40 41 /* Macro to access general purpose regs (base, offset) */ 42 #define CPU_REG(x,y) CPU_IO(x+y) 43 44 /* Macro to access irq related regs */ 45 #define IRQ_REG(x) CPU_REG(IRQC_VIRT,x) 46 47 /* CPU registers */ 48 /* general purpose I/O */ 49 #define GPIO_VIRT(x) (IO_VIRT + 0x23000 + ((x)<<5)) 50 #define GPIO_A_VIRT (GPIO_VIRT(0)) 51 #define GPIO_B_VIRT (GPIO_VIRT(1)) 52 #define GPIO_C_VIRT (GPIO_VIRT(2)) 53 #define GPIO_D_VIRT (GPIO_VIRT(3)) 54 #define GPIO_E_VIRT (GPIO_VIRT(4)) 55 #define GPIO_AMULSEL (GPIO_VIRT(0) + 0xA4) 56 57 #define AMULSEL_USIN2 (1<<5) 58 #define AMULSEL_USOUT2 (1<<6) 59 #define AMULSEL_USIN3 (1<<13) 60 #define AMULSEL_USOUT3 (1<<14) 61 #define AMULSEL_IRDIN (1<<15) 62 #define AMULSEL_IRDOUT (1<<7) 63 64 /* Register offsets general purpose I/O */ 65 #define GPIO_DATA 0x00 66 #define GPIO_DIR 0x04 67 #define GPIO_MASK 0x08 68 #define GPIO_STAT 0x0C 69 #define GPIO_EDGE 0x10 70 #define GPIO_CLR 0x14 71 #define GPIO_POL 0x18 72 #define GPIO_EN 0x1C 73 74 /*interrupt controller */ 75 #define IRQC_VIRT (IO_VIRT + 0x24000) 76 /* register offset interrupt controller */ 77 #define IRQC_IER 0x00 78 #define IRQC_ISR 0x04 79 80 /* timer unit */ 81 #define TIMER_VIRT (IO_VIRT + 0x25000) 82 /* Register offsets timer unit */ 83 #define TM0_PERIOD 0x00 84 #define TM0_COUNT 0x08 85 #define TM0_CTRL 0x10 86 #define TM1_PERIOD 0x20 87 #define TM1_COUNT 0x28 88 #define TM1_CTRL 0x30 89 #define TM2_PERIOD 0x40 90 #define TM2_COUNT 0x48 91 #define TM2_CTRL 0x50 92 #define TIMER_TOPCTRL 0x60 93 #define TIMER_TOPSTAT 0x64 94 #define T64_COUNTL 0x80 95 #define T64_COUNTH 0x84 96 #define T64_CTRL 0x88 97 #define T64_BASEL 0x94 98 #define T64_BASEH 0x98 99 /* Bitmaks timer unit TOPSTAT reg */ 100 #define TSTAT_T0INT 0x1 101 #define TSTAT_T1INT 0x2 102 #define TSTAT_T2INT 0x4 103 #define TSTAT_T3INT 0x8 104 /* Bit description of TMx_CTRL register */ 105 #define TM_START 0x1 106 #define TM_REPEAT 0x2 107 #define TM_RESET 0x4 108 /* Bit description of TIMER_CTRL register */ 109 #define ENABLE_TM0_INTR 0x1 110 #define ENABLE_TM1_INTR 0x2 111 #define ENABLE_TM2_INTR 0x4 112 #define TIMER_ENABLE_BIT 0x8 113 #define ENABLE_TIMER64 0x10 114 #define ENABLE_TIMER64_INT 0x20 115 116 /* PMU & PLL */ 117 #define PMU_BASE (IO_VIRT + 0x1000) 118 #define PMU_MODE 0x00 119 #define PMU_STAT 0x20 120 #define PMU_PLL_CTRL 0x28 121 122 /* PMU Mode bits */ 123 #define PMU_MODE_SLOW 0x00 124 #define PMU_MODE_RUN 0x01 125 #define PMU_MODE_IDLE 0x02 126 #define PMU_MODE_SLEEP 0x03 127 #define PMU_MODE_INIT 0x04 128 #define PMU_MODE_DEEPSLEEP 0x07 129 #define PMU_MODE_WAKEUP 0x08 130 131 /* PMU ... */ 132 #define PLL_2_EN 0x8000 133 #define PLL_1_EN 0x4000 134 #define PLL_3_MUTE 0x0080 135 136 /* Control bits for PMU/ PLL */ 137 #define PMU_WARMRESET 0x00010000 138 #define PLL_CTRL_MASK23 0x000080ff 139 140 /* LCD Controller */ 141 #define LCD_BASE (IO_VIRT + 0x10000) 142 #define LCD_CTRL 0x00 143 #define LCD_STATUS 0x04 144 #define LCD_STATUS_M 0x08 145 #define LCD_INTERRUPT 0x0C 146 #define LCD_DBAR 0x10 147 #define LCD_DCAR 0x14 148 #define LCD_TIMING0 0x20 149 #define LCD_TIMING1 0x24 150 #define LCD_TIMING2 0x28 151 #define LCD_TEST 0x40 152 153 /* LCD Control Bits */ 154 #define LCD_CTRL_LCD_ENABLE 0x00000001 155 /* Bits per pixel */ 156 #define LCD_CTRL_LCD_BPP_MASK 0x00000006 157 #define LCD_CTRL_LCD_4BPP 0x00000000 158 #define LCD_CTRL_LCD_8BPP 0x00000002 159 #define LCD_CTRL_LCD_16BPP 0x00000004 160 #define LCD_CTRL_LCD_BW 0x00000008 161 #define LCD_CTRL_LCD_TFT 0x00000010 162 #define LCD_CTRL_BGR 0x00001000 163 #define LCD_CTRL_LCD_VCOMP 0x00080000 164 #define LCD_CTRL_LCD_MONO8 0x00200000 165 #define LCD_CTRL_LCD_PWR 0x00400000 166 #define LCD_CTRL_LCD_BLE 0x00800000 167 #define LCD_CTRL_LDBUSEN 0x01000000 168 169 /* Palette */ 170 #define LCD_PALETTE_BASE (IO_VIRT + 0x10400) 171 172 /* Serial ports */ 173 #define SERIAL0_OFS 0x20000 174 #define SERIAL0_VIRT (IO_VIRT + SERIAL0_OFS) 175 #define SERIAL0_BASE (IO_PHYS + SERIAL0_OFS) 176 177 #define SERIAL1_OFS 0x21000 178 #define SERIAL1_VIRT (IO_VIRT + SERIAL1_OFS) 179 #define SERIAL1_BASE (IO_PHYS + SERIAL1_OFS) 180 181 #define SERIAL_ENABLE 0x30 182 #define SERIAL_ENABLE_EN (1<<0) 183 184 /* General defines to pacify gcc */ 185 186 #define __ASM_ARCH_HARDWARE_INCMACH_H 187 #include "boards.h" 188 #undef __ASM_ARCH_HARDWARE_INCMACH_H 189 190 #endif /* __ASM_ARCH_HARDWARE_H */ 191