1 #ifndef X86_64_MSR_H 2 #define X86_64_MSR_H 1 3 4 #ifndef __ASSEMBLY__ 5 /* 6 * Access to machine-specific registers (available on 586 and better only) 7 * Note: the rd* operations modify the parameters directly (without using 8 * pointer indirection), this allows gcc to optimize better 9 */ 10 11 #define rdmsr(msr,val1,val2) \ 12 __asm__ __volatile__("rdmsr" \ 13 : "=a" (val1), "=d" (val2) \ 14 : "c" (msr)) 15 16 17 #define rdmsrl(msr,val) do { unsigned long a__,b__; \ 18 __asm__ __volatile__("rdmsr" \ 19 : "=a" (a__), "=d" (b__) \ 20 : "c" (msr)); \ 21 val = a__ | (b__<<32); \ 22 } while(0); 23 24 #define wrmsr(msr,val1,val2) \ 25 __asm__ __volatile__("wrmsr" \ 26 : /* no outputs */ \ 27 : "c" (msr), "a" (val1), "d" (val2)) 28 29 #define wrmsrl(msr,val) wrmsr(msr,(__u32)((__u64)(val)),((__u64)(val))>>32) 30 31 /* wrmsrl with exception handling */ 32 #define checking_wrmsrl(msr,val) ({ int ret__; \ 33 asm volatile("2: wrmsr ; xorl %0,%0\n" \ 34 "1:\n\t" \ 35 ".section .fixup,\"ax\"\n\t" \ 36 "3: movl %4,%0 ; jmp 1b\n\t" \ 37 ".previous\n\t" \ 38 ".section __ex_table,\"a\"\n" \ 39 " .align 8\n\t" \ 40 " .quad 2b,3b\n\t" \ 41 ".previous" \ 42 : "=a" (ret__) \ 43 : "c" (msr), "0" ((__u32)val), "d" ((val)>>32), "i" (-EFAULT));\ 44 ret__; }) 45 46 #define rdtsc(low,high) \ 47 __asm__ __volatile__("rdtsc" : "=a" (low), "=d" (high)) 48 49 #define rdtscl(low) \ 50 __asm__ __volatile__ ("rdtsc" : "=a" (low) : : "edx") 51 52 #define rdtscll(val) do { \ 53 unsigned int a,d; \ 54 asm volatile("rdtsc" : "=a" (a), "=d" (d)); \ 55 (val) = ((unsigned long)a) | (((unsigned long)d)<<32); \ 56 } while(0) 57 58 #define rdpmc(counter,low,high) \ 59 __asm__ __volatile__("rdpmc" \ 60 : "=a" (low), "=d" (high) \ 61 : "c" (counter)) 62 63 #define write_tsc(val1,val2) wrmsr(0x10, val1, val2) 64 65 #define rdpmc(counter,low,high) \ 66 __asm__ __volatile__("rdpmc" \ 67 : "=a" (low), "=d" (high) \ 68 : "c" (counter)) 69 70 #endif 71 72 /* AMD/K8 specific MSRs */ 73 #define MSR_EFER 0xc0000080 /* extended feature register */ 74 #define MSR_STAR 0xc0000081 /* legacy mode SYSCALL target */ 75 #define MSR_LSTAR 0xc0000082 /* long mode SYSCALL target */ 76 #define MSR_CSTAR 0xc0000083 /* compatibility mode SYSCALL target */ 77 #define MSR_SYSCALL_MASK 0xc0000084 /* EFLAGS mask for syscall */ 78 #define MSR_FS_BASE 0xc0000100 /* 64bit GS base */ 79 #define MSR_GS_BASE 0xc0000101 /* 64bit FS base */ 80 #define MSR_KERNEL_GS_BASE 0xc0000102 /* SwapGS GS shadow (or USER_GS from kernel) */ 81 /* EFER bits: */ 82 #define _EFER_SCE 0 /* SYSCALL/SYSRET */ 83 #define _EFER_LME 8 /* Long mode enable */ 84 #define _EFER_LMA 10 /* Long mode active (read-only) */ 85 #define _EFER_NX 11 /* No execute enable */ 86 87 #define EFER_SCE (1<<_EFER_SCE) 88 #define EFER_LME (1<<EFER_LME) 89 #define EFER_LMA (1<<EFER_LMA) 90 #define EFER_NX (1<<_EFER_NX) 91 92 /* Intel MSRs. Some also available on other CPUs */ 93 #define MSR_IA32_PLATFORM_ID 0x17 94 95 #define MSR_IA32_PERFCTR0 0xc1 96 #define MSR_IA32_PERFCTR1 0xc2 97 98 #define MSR_MTRRcap 0x0fe 99 #define MSR_IA32_BBL_CR_CTL 0x119 100 101 #define MSR_IA32_MCG_CAP 0x179 102 #define MSR_IA32_MCG_STATUS 0x17a 103 #define MSR_IA32_MCG_CTL 0x17b 104 105 #define MSR_IA32_EVNTSEL0 0x186 106 #define MSR_IA32_EVNTSEL1 0x187 107 108 #define MSR_IA32_DEBUGCTLMSR 0x1d9 109 #define MSR_IA32_LASTBRANCHFROMIP 0x1db 110 #define MSR_IA32_LASTBRANCHTOIP 0x1dc 111 #define MSR_IA32_LASTINTFROMIP 0x1dd 112 #define MSR_IA32_LASTINTTOIP 0x1de 113 114 #define MSR_MTRRfix64K_00000 0x250 115 #define MSR_MTRRfix16K_80000 0x258 116 #define MSR_MTRRfix16K_A0000 0x259 117 #define MSR_MTRRfix4K_C0000 0x268 118 #define MSR_MTRRfix4K_C8000 0x269 119 #define MSR_MTRRfix4K_D0000 0x26a 120 #define MSR_MTRRfix4K_D8000 0x26b 121 #define MSR_MTRRfix4K_E0000 0x26c 122 #define MSR_MTRRfix4K_E8000 0x26d 123 #define MSR_MTRRfix4K_F0000 0x26e 124 #define MSR_MTRRfix4K_F8000 0x26f 125 #define MSR_MTRRdefType 0x2ff 126 127 #define MSR_IA32_MC0_CTL 0x400 128 #define MSR_IA32_MC0_STATUS 0x401 129 #define MSR_IA32_MC0_ADDR 0x402 130 #define MSR_IA32_MC0_MISC 0x403 131 132 #define MSR_P6_PERFCTR0 0xc1 133 #define MSR_P6_PERFCTR1 0xc2 134 #define MSR_P6_EVNTSEL0 0x186 135 #define MSR_P6_EVNTSEL1 0x187 136 137 /* K7/K8 MSRs. Not complete. See the architecture manual for a more complete list. */ 138 #define MSR_K7_EVNTSEL0 0xC0010000 139 #define MSR_K7_PERFCTR0 0xC0010004 140 #define MSR_K7_EVNTSEL1 0xC0010001 141 #define MSR_K7_PERFCTR1 0xC0010005 142 #define MSR_K7_EVNTSEL2 0xC0010002 143 #define MSR_K7_PERFCTR2 0xC0010006 144 #define MSR_K7_EVNTSEL3 0xC0010003 145 #define MSR_K7_PERFCTR3 0xC0010007 146 #define MSR_K8_TOP_MEM1 0xC001001A 147 #define MSR_K8_TOP_MEM2 0xC001001D 148 #define MSR_K8_SYSCFG 0xC0000010 149 150 /* K6 MSRs */ 151 #define MSR_K6_EFER 0xC0000080 152 #define MSR_K6_STAR 0xC0000081 153 #define MSR_K6_WHCR 0xC0000082 154 #define MSR_K6_UWCCR 0xC0000085 155 #define MSR_K6_PSOR 0xC0000087 156 #define MSR_K6_PFIR 0xC0000088 157 158 /* Centaur-Hauls/IDT defined MSRs. */ 159 #define MSR_IDT_FCR1 0x107 160 #define MSR_IDT_FCR2 0x108 161 #define MSR_IDT_FCR3 0x109 162 #define MSR_IDT_FCR4 0x10a 163 164 #define MSR_IDT_MCR0 0x110 165 #define MSR_IDT_MCR1 0x111 166 #define MSR_IDT_MCR2 0x112 167 #define MSR_IDT_MCR3 0x113 168 #define MSR_IDT_MCR4 0x114 169 #define MSR_IDT_MCR5 0x115 170 #define MSR_IDT_MCR6 0x116 171 #define MSR_IDT_MCR7 0x117 172 #define MSR_IDT_MCR_CTRL 0x120 173 174 /* VIA Cyrix defined MSRs*/ 175 #define MSR_VIA_FCR 0x1107 176 #define MSR_VIA_LONGHAUL 0x110a 177 #define MSR_VIA_RNG 0x110b 178 #define MSR_VIA_BCR2 0x1147 179 180 /* Intel defined MSRs. */ 181 #define MSR_IA32_P5_MC_ADDR 0 182 #define MSR_IA32_P5_MC_TYPE 1 183 #define MSR_IA32_PLATFORM_ID 0x17 184 #define MSR_IA32_EBL_CR_POWERON 0x2a 185 186 #define MSR_IA32_APICBASE 0x1b 187 #define MSR_IA32_APICBASE_BSP (1<<8) 188 #define MSR_IA32_APICBASE_ENABLE (1<<11) 189 #define MSR_IA32_APICBASE_BASE (0xfffff<<12) 190 191 #endif 192