1 2 /* 3 * include/asm-s390/lowcore.h 4 * 5 * S390 version 6 * Copyright (C) 1999 IBM Deutschland Entwicklung GmbH, IBM Corporation 7 * Author(s): Hartmut Penner (hpenner@de.ibm.com), 8 * Martin Schwidefsky (schwidefsky@de.ibm.com), 9 * Denis Joseph Barrow (djbarrow@de.ibm.com,barrow_dj@yahoo.com) 10 */ 11 12 #ifndef _ASM_S390_LOWCORE_H 13 #define _ASM_S390_LOWCORE_H 14 15 #define __LC_EXT_OLD_PSW 0x0130 16 #define __LC_SVC_OLD_PSW 0x0140 17 #define __LC_PGM_OLD_PSW 0x0150 18 #define __LC_MCK_OLD_PSW 0x0160 19 #define __LC_IO_OLD_PSW 0x0170 20 #define __LC_EXT_NEW_PSW 0x01b0 21 #define __LC_SVC_NEW_PSW 0x01c0 22 #define __LC_PGM_NEW_PSW 0x01d0 23 #define __LC_MCK_NEW_PSW 0x01e0 24 #define __LC_IO_NEW_PSW 0x01f0 25 #define __LC_RETURN_PSW 0x0200 26 #define __LC_SYNC_IO_WORD 0x0210 27 #define __LC_EXT_PARAMS 0x080 28 #define __LC_CPU_ADDRESS 0x084 29 #define __LC_EXT_INT_CODE 0x086 30 #define __LC_SVC_ILC 0x088 31 #define __LC_SVC_INT_CODE 0x08A 32 #define __LC_PGM_ILC 0x08C 33 #define __LC_PGM_INT_CODE 0x08E 34 #define __LC_TRANS_EXC_ADDR 0x0a8 35 #define __LC_SUBCHANNEL_ID 0x0B8 36 #define __LC_SUBCHANNEL_NR 0x0BA 37 #define __LC_IO_INT_PARM 0x0BC 38 #define __LC_IO_INT_WORD 0x0C0 39 #define __LC_MCCK_CODE 0x0E8 40 41 #define __LC_DIAG44_OPCODE 0x214 42 43 #define __LC_SAVE_AREA 0xC00 44 #define __LC_KERNEL_STACK 0xD40 45 #define __LC_ASYNC_STACK 0xD48 46 #define __LC_CPUID 0xD90 47 #define __LC_CPUADDR 0xD98 48 #define __LC_IPLDEV 0xDB8 49 50 #define __LC_JIFFY_TIMER 0xDC0 51 #define __LC_INT_CLOCK 0xDC8 52 53 #define __LC_PANIC_MAGIC 0xE00 54 55 #define __LC_AREGS_SAVE_AREA 0x1340 56 #define __LC_CREGS_SAVE_AREA 0x1380 57 58 #define __LC_PFAULT_INTPARM 0x11B8 59 60 /* interrupt handler start with all io, external and mcck interrupt disabled */ 61 62 #define _RESTART_PSW_MASK 0x0000000180000000 63 #define _EXT_PSW_MASK 0x0400000180000000 64 #define _PGM_PSW_MASK 0x0400000180000000 65 #define _SVC_PSW_MASK 0x0400000180000000 66 #define _MCCK_PSW_MASK 0x0400000180000000 67 #define _IO_PSW_MASK 0x0400000180000000 68 #define _USER_PSW_MASK 0x0705C00180000000 69 #define _WAIT_PSW_MASK 0x0706000180000000 70 #define _DW_PSW_MASK 0x0002000180000000 71 72 #define _PRIMARY_MASK 0x0000 /* MASK for SACF */ 73 #define _SECONDARY_MASK 0x0100 /* MASK for SACF */ 74 #define _ACCESS_MASK 0x0200 /* MASK for SACF */ 75 #define _HOME_MASK 0x0300 /* MASK for SACF */ 76 77 #define _PSW_PRIM_SPACE_MODE 0x0000000000000000 78 #define _PSW_SEC_SPACE_MODE 0x0000800000000000 79 #define _PSW_ACC_REG_MODE 0x0000400000000000 80 #define _PSW_HOME_SPACE_MODE 0x0000C00000000000 81 82 #define _PSW_WAIT_MASK_BIT 0x0002000000000000 83 #define _PSW_IO_MASK_BIT 0x0200000000000000 84 #define _PSW_IO_WAIT 0x0202000000000000 85 86 #ifndef __ASSEMBLY__ 87 88 #include <linux/config.h> 89 #include <asm/processor.h> 90 #include <linux/types.h> 91 #include <asm/atomic.h> 92 #include <asm/sigp.h> 93 94 void restart_int_handler(void); 95 void ext_int_handler(void); 96 void system_call(void); 97 void pgm_check_handler(void); 98 void mcck_int_handler(void); 99 void io_int_handler(void); 100 101 struct _lowcore 102 { 103 /* prefix area: defined by architecture */ 104 __u32 ccw1[2]; /* 0x000 */ 105 __u32 ccw2[4]; /* 0x008 */ 106 __u8 pad1[0x80-0x18]; /* 0x018 */ 107 __u32 ext_params; /* 0x080 */ 108 __u16 cpu_addr; /* 0x084 */ 109 __u16 ext_int_code; /* 0x086 */ 110 __u16 svc_ilc; /* 0x088 */ 111 __u16 svc_code; /* 0x08a */ 112 __u16 pgm_ilc; /* 0x08c */ 113 __u16 pgm_code; /* 0x08e */ 114 __u32 data_exc_code; /* 0x090 */ 115 __u16 mon_class_num; /* 0x094 */ 116 __u16 per_perc_atmid; /* 0x096 */ 117 addr_t per_address; /* 0x098 */ 118 __u8 exc_access_id; /* 0x0a0 */ 119 __u8 per_access_id; /* 0x0a1 */ 120 __u8 op_access_id; /* 0x0a2 */ 121 __u8 ar_access_id; /* 0x0a3 */ 122 __u8 pad2[0xA8-0xA4]; /* 0x0a4 */ 123 addr_t trans_exc_code; /* 0x0A0 */ 124 addr_t monitor_code; /* 0x09c */ 125 __u16 subchannel_id; /* 0x0b8 */ 126 __u16 subchannel_nr; /* 0x0ba */ 127 __u32 io_int_parm; /* 0x0bc */ 128 __u32 io_int_word; /* 0x0c0 */ 129 __u8 pad3[0xc8-0xc4]; /* 0x0c4 */ 130 __u32 stfl_fac_list; /* 0x0c8 */ 131 __u8 pad4[0xe8-0xcc]; /* 0x0cc */ 132 __u32 mcck_interruption_code[2]; /* 0x0e8 */ 133 __u8 pad5[0xf4-0xf0]; /* 0x0f0 */ 134 __u32 external_damage_code; /* 0x0f4 */ 135 addr_t failing_storage_address; /* 0x0f8 */ 136 __u8 pad6[0x120-0x100]; /* 0x100 */ 137 psw_t restart_old_psw; /* 0x120 */ 138 psw_t external_old_psw; /* 0x130 */ 139 psw_t svc_old_psw; /* 0x140 */ 140 psw_t program_old_psw; /* 0x150 */ 141 psw_t mcck_old_psw; /* 0x160 */ 142 psw_t io_old_psw; /* 0x170 */ 143 __u8 pad7[0x1a0-0x180]; /* 0x180 */ 144 psw_t restart_psw; /* 0x1a0 */ 145 psw_t external_new_psw; /* 0x1b0 */ 146 psw_t svc_new_psw; /* 0x1c0 */ 147 psw_t program_new_psw; /* 0x1d0 */ 148 psw_t mcck_new_psw; /* 0x1e0 */ 149 psw_t io_new_psw; /* 0x1f0 */ 150 psw_t return_psw; /* 0x200 */ 151 __u32 sync_io_word; /* 0x210 */ 152 __u32 diag44_opcode; /* 0x214 */ 153 __u8 pad8[0xc00-0x218]; /* 0x218 */ 154 /* System info area */ 155 __u64 save_area[16]; /* 0xc00 */ 156 __u8 pad9[0xd40-0xc80]; /* 0xc80 */ 157 __u64 kernel_stack; /* 0xd40 */ 158 __u64 async_stack; /* 0xd48 */ 159 /* entry.S sensitive area start */ 160 __u8 pad10[0xd80-0xd50]; /* 0xd64 */ 161 struct cpuinfo_S390 cpu_data; /* 0xd80 */ 162 __u32 ipl_device; /* 0xdb8 */ 163 __u32 pad11; /* 0xdbc was lsw word of ipl_device until a bug was found DJB */ 164 /* entry.S sensitive area end */ 165 166 /* SMP info area: defined by DJB */ 167 __u64 jiffy_timer; /* 0xdc0 */ 168 __u64 int_clock; /* 0xdc8 */ 169 __u64 ext_call_fast; /* 0xdd0 */ 170 __u8 pad12[0xe00-0xdd8]; /* 0xdd8 */ 171 172 /* 0xe00 is used as indicator for dump tools */ 173 /* whether the kernel died with panic() or not */ 174 __u32 panic_magic; /* 0xe00 */ 175 176 __u8 pad13[0x1200-0xe04]; /* 0xe04 */ 177 178 /* System info area */ 179 180 __u64 floating_pt_save_area[16]; /* 0x1200 */ 181 __u64 gpregs_save_area[16]; /* 0x1280 */ 182 __u32 st_status_fixed_logout[4]; /* 0x1300 */ 183 __u8 pad14[0x1318-0x1310]; /* 0x1310 */ 184 __u32 prefixreg_save_area; /* 0x1318 */ 185 __u32 fpt_creg_save_area; /* 0x131c */ 186 __u8 pad15[0x1324-0x1320]; /* 0x1320 */ 187 __u32 tod_progreg_save_area; /* 0x1324 */ 188 __u32 cpu_timer_save_area[2]; /* 0x1328 */ 189 __u32 clock_comp_save_area[2]; /* 0x1330 */ 190 __u8 pad16[0x1340-0x1338]; /* 0x1338 */ 191 __u32 access_regs_save_area[16]; /* 0x1340 */ 192 __u64 cregs_save_area[16]; /* 0x1380 */ 193 194 /* align to the top of the prefix area */ 195 196 __u8 pad17[0x2000-0x1400]; /* 0x1400 */ 197 } __attribute__((packed)); /* End structure*/ 198 set_prefix(__u32 address)199extern __inline__ void set_prefix(__u32 address) 200 { 201 __asm__ __volatile__ ("spx %0" : : "m" (address) : "memory" ); 202 } 203 204 #define S390_lowcore (*((struct _lowcore *) 0)) 205 extern struct _lowcore *lowcore_ptr[]; 206 207 #ifndef CONFIG_SMP 208 #define get_cpu_lowcore(cpu) (&S390_lowcore) 209 #define safe_get_cpu_lowcore(cpu) (&S390_lowcore) 210 #else 211 #define get_cpu_lowcore(cpu) (lowcore_ptr[(cpu)]) 212 #define safe_get_cpu_lowcore(cpu) \ 213 ((cpu) == smp_processor_id() ? &S390_lowcore : lowcore_ptr[(cpu)]) 214 #endif 215 #endif /* __ASSEMBLY__ */ 216 217 #define __PANIC_MAGIC 0xDEADC0DE 218 219 #endif 220 221