1 /* 2 * uninorth.h: definitions for using the "UniNorth" host bridge chip 3 * from Apple. This chip is used on "Core99" machines 4 * 5 */ 6 #ifdef __KERNEL__ 7 #ifndef __ASM_UNINORTH_H__ 8 #define __ASM_UNINORTH_H__ 9 10 /* 11 * Uni-N config space reg. definitions 12 * 13 * (Little endian) 14 */ 15 16 /* Address ranges selection. This one should work with Bandit too */ 17 #define UNI_N_ADDR_SELECT 0x48 18 #define UNI_N_ADDR_COARSE_MASK 0xffff0000 /* 256Mb regions at *0000000 */ 19 #define UNI_N_ADDR_FINE_MASK 0x0000ffff /* 16Mb regions at f*000000 */ 20 21 /* AGP registers */ 22 #define UNI_N_CFG_GART_BASE 0x8c 23 #define UNI_N_CFG_AGP_BASE 0x90 24 #define UNI_N_CFG_GART_CTRL 0x94 25 #define UNI_N_CFG_INTERNAL_STATUS 0x98 26 27 /* UNI_N_CFG_GART_CTRL bits definitions */ 28 #define UNI_N_CFG_GART_INVAL 0x00000001 29 #define UNI_N_CFG_GART_ENABLE 0x00000100 30 #define UNI_N_CFG_GART_2xRESET 0x00010000 31 #define UNI_N_CFG_GART_DISSBADET 0x00020000 32 33 /* My understanding of UniNorth AGP as of UniNorth rev 1.0x, 34 * revision 1.5 (x4 AGP) may need further changes. 35 * 36 * AGP_BASE register contains the base address of the AGP aperture on 37 * the AGP bus. It doesn't seem to be visible to the CPU as of UniNorth 1.x, 38 * even if decoding of this address range is enabled in the address select 39 * register. Apparently, the only supported bases are 256Mb multiples 40 * (high 4 bits of that register). 41 * 42 * GART_BASE register appear to contain the physical address of the GART 43 * in system memory in the high address bits (page aligned), and the 44 * GART size in the low order bits (number of GART pages) 45 * 46 * The GART format itself is one 32bits word per physical memory page. 47 * This word contains, in little-endian format (!!!), the physical address 48 * of the page in the high bits, and what appears to be an "enable" bit 49 * in the LSB bit (0) that must be set to 1 when the entry is valid. 50 * 51 * Obviously, the GART is not cache coherent and so any change to it 52 * must be flushed to memory (or maybe just make the GART space non 53 * cachable). AGP memory itself doens't seem to be cache coherent neither. 54 * 55 * In order to invalidate the GART (which is probably necessary to inval 56 * the bridge internal TLBs), the following sequence has to be written, 57 * in order, to the GART_CTRL register: 58 * 59 * UNI_N_CFG_GART_ENABLE | UNI_N_CFG_GART_INVAL 60 * UNI_N_CFG_GART_ENABLE 61 * UNI_N_CFG_GART_ENABLE | UNI_N_CFG_GART_2xRESET 62 * UNI_N_CFG_GART_ENABLE 63 * 64 * As far as AGP "features" are concerned, it looks like fast write may 65 * not be supported but this has to be confirmed. 66 * 67 * Turning on AGP seem to require a double invalidate operation, one before 68 * setting the AGP command register, on after. 69 * 70 * Turning off AGP seems to require the following sequence: first wait 71 * for the AGP to be idle by reading the internal status register, then 72 * write in that order to the GART_CTRL register: 73 * 74 * UNI_N_CFG_GART_ENABLE | UNI_N_CFG_GART_INVAL 75 * 0 76 * UNI_N_CFG_GART_2xRESET 77 * 0 78 */ 79 80 /* 81 * Uni-N memory mapped reg. definitions 82 * 83 * Those registers are Big-Endian !! 84 * 85 * Their meaning come from either Darwin and/or from experiments I made with 86 * the bootrom, I'm not sure about their exact meaning yet 87 * 88 */ 89 90 /* Version of the UniNorth chip */ 91 #define UNI_N_VERSION 0x0000 /* Known versions: 3,7 and 8 */ 92 93 /* This register is used to enable/disable various clocks */ 94 #define UNI_N_CLOCK_CNTL 0x0020 95 #define UNI_N_CLOCK_CNTL_PCI 0x00000001 /* PCI2 clock control */ 96 #define UNI_N_CLOCK_CNTL_GMAC 0x00000002 /* GMAC clock control */ 97 #define UNI_N_CLOCK_CNTL_FW 0x00000004 /* FireWire clock control */ 98 #define UNI_N_CLOCK_CNTL_ATA100 0x00000010 /* ATA-100 clock control (U2) */ 99 100 /* Power Management control */ 101 #define UNI_N_POWER_MGT 0x0030 102 #define UNI_N_POWER_MGT_NORMAL 0x00 103 #define UNI_N_POWER_MGT_IDLE2 0x01 104 #define UNI_N_POWER_MGT_SLEEP 0x02 105 106 /* This register is configured by Darwin depending on the UniN 107 * revision 108 */ 109 #define UNI_N_ARB_CTRL 0x0040 110 #define UNI_N_ARB_CTRL_QACK_DELAY_SHIFT 15 111 #define UNI_N_ARB_CTRL_QACK_DELAY_MASK 0x0e1f8000 112 #define UNI_N_ARB_CTRL_QACK_DELAY 0x30 113 #define UNI_N_ARB_CTRL_QACK_DELAY105 0x00 114 115 /* This one _might_ return the CPU number of the CPU reading it; 116 * the bootROM decides wether to boot or to sleep/spinloop depending 117 * on this register beeing 0 or not 118 */ 119 #define UNI_N_CPU_NUMBER 0x0050 120 121 /* This register appear to be read by the bootROM to decide what 122 * to do on a non-recoverable reset (powerup or wakeup) 123 */ 124 #define UNI_N_HWINIT_STATE 0x0070 125 #define UNI_N_HWINIT_STATE_SLEEPING 0x01 126 #define UNI_N_HWINIT_STATE_RUNNING 0x02 127 /* This last bit appear to be used by the bootROM to know the second 128 * CPU has started and will enter it's sleep loop with IP=0 129 */ 130 #define UNI_N_HWINIT_STATE_CPU1_FLAG 0x10000000 131 132 /* Uninorth 1.5 rev. has additional perf. monitor registers at 0xf00-0xf50 */ 133 134 #endif /* __ASM_UNINORTH_H__ */ 135 #endif /* __KERNEL__ */ 136