1 /* 2 * include/asm-ppc/ppc4xx_dma.h 3 * 4 * IBM PPC4xx DMA engine library 5 * 6 * Copyright 2000-2003 MontaVista Software Inc. 7 * 8 * Cleaned by Matt Porter <mporter@mvista.com> 9 * 10 * Original code by Armin Kuster <akuster@mvista.com> 11 * and Pete Popov <ppopov@mvista.com> 12 * 13 * This program is free software; you can redistribute it and/or modify it 14 * under the terms of the GNU General Public License as published by the 15 * Free Software Foundation; either version 2 of the License, or (at your 16 * option) any later version. 17 * 18 * You should have received a copy of the GNU General Public License along 19 * with this program; if not, write to the Free Software Foundation, Inc., 20 * 675 Mass Ave, Cambridge, MA 02139, USA. 21 */ 22 23 #ifdef __KERNEL__ 24 #ifndef __ASMPPC_PPC4xx_DMA_H 25 #define __ASMPPC_PPC4xx_DMA_H 26 27 #include <linux/config.h> 28 #include <linux/types.h> 29 #include <asm/mmu.h> 30 #include <asm/ibm4xx.h> 31 32 #undef DEBUG_4xxDMA 33 34 #define MAX_PPC4xx_DMA_CHANNELS 4 35 36 /* in arch/ppc/kernel/setup.c -- Cort */ 37 extern unsigned long DMA_MODE_WRITE, DMA_MODE_READ; 38 39 /* 40 * Function return status codes 41 * These values are used to indicate whether or not the function 42 * call was successful, or a bad/invalid parameter was passed. 43 */ 44 #define DMA_STATUS_GOOD 0 45 #define DMA_STATUS_BAD_CHANNEL 1 46 #define DMA_STATUS_BAD_HANDLE 2 47 #define DMA_STATUS_BAD_MODE 3 48 #define DMA_STATUS_NULL_POINTER 4 49 #define DMA_STATUS_OUT_OF_MEMORY 5 50 #define DMA_STATUS_SGL_LIST_EMPTY 6 51 #define DMA_STATUS_GENERAL_ERROR 7 52 #define DMA_STATUS_CHANNEL_NOTFREE 8 53 54 #define DMA_CHANNEL_BUSY 0x80000000 55 56 /* 57 * These indicate status as returned from the DMA Status Register. 58 */ 59 #define DMA_STATUS_NO_ERROR 0 60 #define DMA_STATUS_CS 1 /* Count Status */ 61 #define DMA_STATUS_TS 2 /* Transfer Status */ 62 #define DMA_STATUS_DMA_ERROR 3 /* DMA Error Occurred */ 63 #define DMA_STATUS_DMA_BUSY 4 /* The channel is busy */ 64 65 66 /* 67 * DMA Channel Control Registers 68 */ 69 70 #ifdef CONFIG_44x 71 #define PPC4xx_DMA_64BIT 72 #define DMA_CR_OFFSET 1 73 #else 74 #define DMA_CR_OFFSET 0 75 #endif 76 77 #define DMA_CE_ENABLE (1<<31) /* DMA Channel Enable */ 78 #define SET_DMA_CE_ENABLE(x) (((x)&0x1)<<31) 79 #define GET_DMA_CE_ENABLE(x) (((x)&DMA_CE_ENABLE)>>31) 80 81 #define DMA_CIE_ENABLE (1<<30) /* DMA Channel Interrupt Enable */ 82 #define SET_DMA_CIE_ENABLE(x) (((x)&0x1)<<30) 83 #define GET_DMA_CIE_ENABLE(x) (((x)&DMA_CIE_ENABLE)>>30) 84 85 #define DMA_TD (1<<29) 86 #define SET_DMA_TD(x) (((x)&0x1)<<29) 87 #define GET_DMA_TD(x) (((x)&DMA_TD)>>29) 88 89 #define DMA_PL (1<<28) /* Peripheral Location */ 90 #define SET_DMA_PL(x) (((x)&0x1)<<28) 91 #define GET_DMA_PL(x) (((x)&DMA_PL)>>28) 92 93 #define EXTERNAL_PERIPHERAL 0 94 #define INTERNAL_PERIPHERAL 1 95 96 #define SET_DMA_PW(x) (((x)&0x3)<<(26-DMA_CR_OFFSET)) /* Peripheral Width */ 97 #define DMA_PW_MASK SET_DMA_PW(3) 98 #define PW_8 0 99 #define PW_16 1 100 #define PW_32 2 101 #define PW_64 3 102 /* FIXME: Add PW_128 support for 440GP DMA block */ 103 #define GET_DMA_PW(x) (((x)&DMA_PW_MASK)>>(26-DMA_CR_OFFSET)) 104 105 #define DMA_DAI (1<<(25-DMA_CR_OFFSET)) /* Destination Address Increment */ 106 #define SET_DMA_DAI(x) (((x)&0x1)<<(25-DMA_CR_OFFSET)) 107 108 #define DMA_SAI (1<<(24-DMA_CR_OFFSET)) /* Source Address Increment */ 109 #define SET_DMA_SAI(x) (((x)&0x1)<<(24-DMA_CR_OFFSET)) 110 111 #define DMA_BEN (1<<(23-DMA_CR_OFFSET)) /* Buffer Enable */ 112 #define SET_DMA_BEN(x) (((x)&0x1)<<(23-DMA_CR_OFFSET)) 113 114 #define SET_DMA_TM(x) (((x)&0x3)<<(21-DMA_CR_OFFSET)) /* Transfer Mode */ 115 #define DMA_TM_MASK SET_DMA_TM(3) 116 #define TM_PERIPHERAL 0 /* Peripheral */ 117 #define TM_RESERVED 1 /* Reserved */ 118 #define TM_S_MM 2 /* Memory to Memory */ 119 #define TM_D_MM 3 /* Device Paced Memory to Memory */ 120 #define GET_DMA_TM(x) (((x)&DMA_TM_MASK)>>(21-DMA_CR_OFFSET)) 121 122 #define SET_DMA_PSC(x) (((x)&0x3)<<(19-DMA_CR_OFFSET)) /* Peripheral Setup Cycles */ 123 #define DMA_PSC_MASK SET_DMA_PSC(3) 124 #define GET_DMA_PSC(x) (((x)&DMA_PSC_MASK)>>(19-DMA_CR_OFFSET)) 125 126 #define SET_DMA_PWC(x) (((x)&0x3F)<<(13-DMA_CR_OFFSET)) /* Peripheral Wait Cycles */ 127 #define DMA_PWC_MASK SET_DMA_PWC(0x3F) 128 #define GET_DMA_PWC(x) (((x)&DMA_PWC_MASK)>>(13-DMA_CR_OFFSET)) 129 130 #define SET_DMA_PHC(x) (((x)&0x7)<<(10-DMA_CR_OFFSET)) /* Peripheral Hold Cycles */ 131 #define DMA_PHC_MASK SET_DMA_PHC(0x7) 132 #define GET_DMA_PHC(x) (((x)&DMA_PHC_MASK)>>(10-DMA_CR_OFFSET)) 133 134 #define DMA_ETD_OUTPUT (1<<(9-DMA_CR_OFFSET)) /* EOT pin is a TC output */ 135 #define SET_DMA_ETD(x) (((x)&0x1)<<(9-DMA_CR_OFFSET)) 136 137 #define DMA_TCE_ENABLE (1<<(8-DMA_CR_OFFSET)) 138 #define SET_DMA_TCE(x) (((x)&0x1)<<(8-DMA_CR_OFFSET)) 139 140 #define DMA_DEC (1<<(2)) /* Address Decrement */ 141 #define SET_DMA_DEC(x) (((x)&0x1)<<2) 142 #define GET_DMA_DEC(x) (((x)&DMA_DEC)>>2) 143 144 /* 145 * Transfer Modes 146 * These modes are defined in a way that makes it possible to 147 * simply "or" in the value in the control register. 148 */ 149 150 #define DMA_MODE_MM (SET_DMA_TM(TM_S_MM)) /* memory to memory */ 151 152 /* Device-paced memory to memory, */ 153 /* device is at source address */ 154 #define DMA_MODE_MM_DEVATSRC (DMA_TD | SET_DMA_TM(TM_D_MM)) 155 156 /* Device-paced memory to memory, */ 157 /* device is at destination address */ 158 #define DMA_MODE_MM_DEVATDST (SET_DMA_TM(TM_D_MM)) 159 160 /* 405gp/440gp */ 161 #define SET_DMA_PREFETCH(x) (((x)&0x3)<<(4-DMA_CR_OFFSET)) /* Memory Read Prefetch */ 162 #define DMA_PREFETCH_MASK SET_DMA_PREFETCH(3) 163 #define PREFETCH_1 0 /* Prefetch 1 Double Word */ 164 #define PREFETCH_2 1 165 #define PREFETCH_4 2 166 #define GET_DMA_PREFETCH(x) (((x)&DMA_PREFETCH_MASK)>>(4-DMA_CR_OFFSET)) 167 168 #define DMA_PCE (1<<(3-DMA_CR_OFFSET)) /* Parity Check Enable */ 169 #define SET_DMA_PCE(x) (((x)&0x1)<<(3-DMA_CR_OFFSET)) 170 #define GET_DMA_PCE(x) (((x)&DMA_PCE)>>(3-DMA_CR_OFFSET)) 171 172 /* stb3x */ 173 174 #define DMA_ECE_ENABLE (1<<5) 175 #define SET_DMA_ECE(x) (((x)&0x1)<<5) 176 #define GET_DMA_ECE(x) (((x)&DMA_ECE_ENABLE)>>5) 177 178 #define DMA_TCD_DISABLE (1<<4) 179 #define SET_DMA_TCD(x) (((x)&0x1)<<4) 180 #define GET_DMA_TCD(x) (((x)&DMA_TCD_DISABLE)>>4) 181 182 typedef uint32_t sgl_handle_t; 183 184 #ifdef CONFIG_PPC4xx_EDMA 185 186 #define SGL_LIST_SIZE 4096 187 #define DMA_PPC4xx_SIZE SGL_LIST_SIZE 188 189 #define SET_DMA_PRIORITY(x) (((x)&0x3)<<(6-DMA_CR_OFFSET)) /* DMA Channel Priority */ 190 #define DMA_PRIORITY_MASK SET_DMA_PRIORITY(3) 191 #define PRIORITY_LOW 0 192 #define PRIORITY_MID_LOW 1 193 #define PRIORITY_MID_HIGH 2 194 #define PRIORITY_HIGH 3 195 #define GET_DMA_PRIORITY(x) (((x)&DMA_PRIORITY_MASK)>>(6-DMA_CR_OFFSET)) 196 197 /* 198 * DMA Polarity Configuration Register 199 */ 200 201 #define DMAReq0_ActiveLow (1<<31) 202 #define DMAAck0_ActiveLow (1<<30) 203 #define EOT0_ActiveLow (1<<29) /* End of Transfer */ 204 205 #define DMAReq1_ActiveLow (1<<28) 206 #define DMAAck1_ActiveLow (1<<27) 207 #define EOT1_ActiveLow (1<<26) 208 209 #define DMAReq2_ActiveLow (1<<25) 210 #define DMAAck2_ActiveLow (1<<24) 211 #define EOT2_ActiveLow (1<<23) 212 213 #define DMAReq3_ActiveLow (1<<22) 214 #define DMAAck3_ActiveLow (1<<21) 215 #define EOT3_ActiveLow (1<<20) 216 217 /* 218 * DMA Sleep Mode Register 219 */ 220 #define SLEEP_MODE_ENABLE (1<<21) 221 222 /* 223 * DMA Status Register 224 */ 225 #define DMA_CS0 (1<<31) /* Terminal Count has been reached */ 226 #define DMA_CS1 (1<<30) 227 #define DMA_CS2 (1<<29) 228 #define DMA_CS3 (1<<28) 229 230 #define DMA_TS0 (1<<27) /* End of Transfer has been requested */ 231 #define DMA_TS1 (1<<26) 232 #define DMA_TS2 (1<<25) 233 #define DMA_TS3 (1<<24) 234 235 #define DMA_CH0_ERR (1<<23) /* DMA Chanel 0 Error */ 236 #define DMA_CH1_ERR (1<<22) 237 #define DMA_CH2_ERR (1<<21) 238 #define DMA_CH3_ERR (1<<20) 239 240 #define DMA_IN_DMA_REQ0 (1<<19) /* Internal DMA Request is pending */ 241 #define DMA_IN_DMA_REQ1 (1<<18) 242 #define DMA_IN_DMA_REQ2 (1<<17) 243 #define DMA_IN_DMA_REQ3 (1<<16) 244 245 #define DMA_EXT_DMA_REQ0 (1<<15) /* External DMA Request is pending */ 246 #define DMA_EXT_DMA_REQ1 (1<<14) 247 #define DMA_EXT_DMA_REQ2 (1<<13) 248 #define DMA_EXT_DMA_REQ3 (1<<12) 249 250 #define DMA_CH0_BUSY (1<<11) /* DMA Channel 0 Busy */ 251 #define DMA_CH1_BUSY (1<<10) 252 #define DMA_CH2_BUSY (1<<9) 253 #define DMA_CH3_BUSY (1<<8) 254 255 #define DMA_SG0 (1<<7) /* DMA Channel 0 Scatter/Gather in progress */ 256 #define DMA_SG1 (1<<6) 257 #define DMA_SG2 (1<<5) 258 #define DMA_SG3 (1<<4) 259 260 /* 261 * DMA SG Command Register 262 */ 263 #define SSG0_ENABLE (1<<31) /* Start Scatter Gather */ 264 #define SSG1_ENABLE (1<<30) 265 #define SSG2_ENABLE (1<<29) 266 #define SSG3_ENABLE (1<<28) 267 #define SSG0_MASK_ENABLE (1<<15) /* Enable writing to SSG0 bit */ 268 #define SSG1_MASK_ENABLE (1<<14) 269 #define SSG2_MASK_ENABLE (1<<13) 270 #define SSG3_MASK_ENABLE (1<<12) 271 272 /* 273 * DMA Scatter/Gather Descriptor Bit fields 274 */ 275 #define SG_LINK (1<<31) /* Link */ 276 #define SG_TCI_ENABLE (1<<29) /* Enable Terminal Count Interrupt */ 277 #define SG_ETI_ENABLE (1<<28) /* Enable End of Transfer Interrupt */ 278 #define SG_ERI_ENABLE (1<<27) /* Enable Error Interrupt */ 279 #define SG_COUNT_MASK 0xFFFF /* Count Field */ 280 281 #define SET_DMA_CONTROL \ 282 (SET_DMA_CIE_ENABLE(p_init->int_enable) | /* interrupt enable */ \ 283 SET_DMA_BEN(p_init->buffer_enable) | /* buffer enable */\ 284 SET_DMA_ETD(p_init->etd_output) | /* end of transfer pin */ \ 285 SET_DMA_TCE(p_init->tce_enable) | /* terminal count enable */ \ 286 SET_DMA_PL(p_init->pl) | /* peripheral location */ \ 287 SET_DMA_DAI(p_init->dai) | /* dest addr increment */ \ 288 SET_DMA_SAI(p_init->sai) | /* src addr increment */ \ 289 SET_DMA_PRIORITY(p_init->cp) | /* channel priority */ \ 290 SET_DMA_PW(p_init->pwidth) | /* peripheral/bus width */ \ 291 SET_DMA_PSC(p_init->psc) | /* peripheral setup cycles */ \ 292 SET_DMA_PWC(p_init->pwc) | /* peripheral wait cycles */ \ 293 SET_DMA_PHC(p_init->phc) | /* peripheral hold cycles */ \ 294 SET_DMA_PREFETCH(p_init->pf) /* read prefetch */) 295 296 #define GET_DMA_POLARITY(chan) (DMAReq##chan##_ActiveLow | DMAAck##chan##_ActiveLow | EOT##chan##_ActiveLow) 297 298 #elif defined(CONFIG_STBXXX_DMA) /* stb03xxx */ 299 300 #define DMA_PPC4xx_SIZE 4096 301 302 /* 303 * DMA Status Register 304 */ 305 306 #define SET_DMA_PRIORITY(x) (((x)&0x00800001)) /* DMA Channel Priority */ 307 #define DMA_PRIORITY_MASK 0x00800001 308 #define PRIORITY_LOW 0x00000000 309 #define PRIORITY_MID_LOW 0x00000001 310 #define PRIORITY_MID_HIGH 0x00800000 311 #define PRIORITY_HIGH 0x00800001 312 #define GET_DMA_PRIORITY(x) (((((x)&DMA_PRIORITY_MASK) &0x00800000) >> 22 ) | (((x)&DMA_PRIORITY_MASK) &0x00000001)) 313 314 #define DMA_CS0 (1<<31) /* Terminal Count has been reached */ 315 #define DMA_CS1 (1<<30) 316 #define DMA_CS2 (1<<29) 317 #define DMA_CS3 (1<<28) 318 319 #define DMA_TS0 (1<<27) /* End of Transfer has been requested */ 320 #define DMA_TS1 (1<<26) 321 #define DMA_TS2 (1<<25) 322 #define DMA_TS3 (1<<24) 323 324 #define DMA_CH0_ERR (1<<23) /* DMA Chanel 0 Error */ 325 #define DMA_CH1_ERR (1<<22) 326 #define DMA_CH2_ERR (1<<21) 327 #define DMA_CH3_ERR (1<<20) 328 329 #define DMA_CT0 (1<<19) /* Chained transfere */ 330 331 #define DMA_IN_DMA_REQ0 (1<<18) /* Internal DMA Request is pending */ 332 #define DMA_IN_DMA_REQ1 (1<<17) 333 #define DMA_IN_DMA_REQ2 (1<<16) 334 #define DMA_IN_DMA_REQ3 (1<<15) 335 336 #define DMA_EXT_DMA_REQ0 (1<<14) /* External DMA Request is pending */ 337 #define DMA_EXT_DMA_REQ1 (1<<13) 338 #define DMA_EXT_DMA_REQ2 (1<<12) 339 #define DMA_EXT_DMA_REQ3 (1<<11) 340 341 #define DMA_CH0_BUSY (1<<10) /* DMA Channel 0 Busy */ 342 #define DMA_CH1_BUSY (1<<9) 343 #define DMA_CH2_BUSY (1<<8) 344 #define DMA_CH3_BUSY (1<<7) 345 346 #define DMA_CT1 (1<<6) /* Chained transfere */ 347 #define DMA_CT2 (1<<5) 348 #define DMA_CT3 (1<<4) 349 350 #define DMA_CH_ENABLE (1<<7) 351 #define SET_DMA_CH(x) (((x)&0x1)<<7) 352 #define GET_DMA_CH(x) (((x)&DMA_CH_ENABLE)>>7) 353 354 /* STBx25xxx dma unique */ 355 /* enable device port on a dma channel 356 * example ext 0 on dma 1 357 */ 358 359 #define SSP0_RECV 15 360 #define SSP0_XMIT 14 361 #define EXT_DMA_0 12 362 #define SC1_XMIT 11 363 #define SC1_RECV 10 364 #define EXT_DMA_2 9 365 #define EXT_DMA_3 8 366 #define SERIAL2_XMIT 7 367 #define SERIAL2_RECV 6 368 #define SC0_XMIT 5 369 #define SC0_RECV 4 370 #define SERIAL1_XMIT 3 371 #define SERIAL1_RECV 2 372 #define SERIAL0_XMIT 1 373 #define SERIAL0_RECV 0 374 375 #define DMA_CHAN_0 1 376 #define DMA_CHAN_1 2 377 #define DMA_CHAN_2 3 378 #define DMA_CHAN_3 4 379 380 /* end STBx25xx */ 381 382 /* 383 * Bit 30 must be one for Redwoods, otherwise transfers may receive errors. 384 */ 385 #define DMA_CR_MB0 0x2 386 387 #define SET_DMA_CONTROL \ 388 (SET_DMA_CIE_ENABLE(p_init->int_enable) | /* interrupt enable */ \ 389 SET_DMA_ETD(p_init->etd_output) | /* end of transfer pin */ \ 390 SET_DMA_TCE(p_init->tce_enable) | /* terminal count enable */ \ 391 SET_DMA_PL(p_init->pl) | /* peripheral location */ \ 392 SET_DMA_DAI(p_init->dai) | /* dest addr increment */ \ 393 SET_DMA_SAI(p_init->sai) | /* src addr increment */ \ 394 SET_DMA_PRIORITY(p_init->cp) | /* channel priority */ \ 395 SET_DMA_PW(p_init->pwidth) | /* peripheral/bus width */ \ 396 SET_DMA_PSC(p_init->psc) | /* peripheral setup cycles */ \ 397 SET_DMA_PWC(p_init->pwc) | /* peripheral wait cycles */ \ 398 SET_DMA_PHC(p_init->phc) | /* peripheral hold cycles */ \ 399 SET_DMA_TCD(p_init->tcd_disable) | /* TC chain mode disable */ \ 400 SET_DMA_ECE(p_init->ece_enable) | /* ECE chanin mode enable */ \ 401 SET_DMA_CH(p_init->ch_enable) | /* Chain enable */ \ 402 DMA_CR_MB0 /* must be one */) 403 404 #define GET_DMA_POLARITY(chan) chan 405 406 #endif 407 408 typedef struct { 409 unsigned short in_use; /* set when channel is being used, clr when 410 * available. 411 */ 412 /* 413 * Valid polarity settings: 414 * DMAReq0_ActiveLow 415 * DMAAck0_ActiveLow 416 * EOT0_ActiveLow 417 * 418 * DMAReq1_ActiveLow 419 * DMAAck1_ActiveLow 420 * EOT1_ActiveLow 421 * 422 * DMAReq2_ActiveLow 423 * DMAAck2_ActiveLow 424 * EOT2_ActiveLow 425 * 426 * DMAReq3_ActiveLow 427 * DMAAck3_ActiveLow 428 * EOT3_ActiveLow 429 */ 430 unsigned int polarity; 431 432 char buffer_enable; /* Boolean: buffer enable */ 433 char tce_enable; /* Boolean: terminal count enable */ 434 char etd_output; /* Boolean: eot pin is a tc output */ 435 char pce; /* Boolean: parity check enable */ 436 437 /* 438 * Peripheral location: 439 * INTERNAL_PERIPHERAL (UART0 on the 405GP) 440 * EXTERNAL_PERIPHERAL 441 */ 442 char pl; /* internal/external peripheral */ 443 444 /* 445 * Valid pwidth settings: 446 * PW_8 447 * PW_16 448 * PW_32 449 * PW_64 450 */ 451 unsigned int pwidth; 452 453 char dai; /* Boolean: dst address increment */ 454 char sai; /* Boolean: src address increment */ 455 456 /* 457 * Valid psc settings: 0-3 458 */ 459 unsigned int psc; /* Peripheral Setup Cycles */ 460 461 /* 462 * Valid pwc settings: 463 * 0-63 464 */ 465 unsigned int pwc; /* Peripheral Wait Cycles */ 466 467 /* 468 * Valid phc settings: 469 * 0-7 470 */ 471 unsigned int phc; /* Peripheral Hold Cycles */ 472 473 /* 474 * Valid cp (channel priority) settings: 475 * PRIORITY_LOW 476 * PRIORITY_MID_LOW 477 * PRIORITY_MID_HIGH 478 * PRIORITY_HIGH 479 */ 480 unsigned int cp; /* channel priority */ 481 482 /* 483 * Valid pf (memory read prefetch) settings: 484 * 485 * PREFETCH_1 486 * PREFETCH_2 487 * PREFETCH_4 488 */ 489 unsigned int pf; /* memory read prefetch */ 490 491 /* 492 * Boolean: channel interrupt enable 493 * NOTE: for sgl transfers, only the last descriptor will be setup to 494 * interrupt. 495 */ 496 char int_enable; 497 498 char shift; /* easy access to byte_count shift, based on */ 499 /* the width of the channel */ 500 501 uint32_t control; /* channel control word */ 502 503 /* These variabled are used ONLY in single dma transfers */ 504 unsigned int mode; /* transfer mode */ 505 phys_addr_t addr; 506 char ce; /* channel enable */ 507 #ifdef CONFIG_STB03xxx 508 char ch_enable; 509 char tcd_disable; 510 char ece_enable; 511 char td; /* transfer direction */ 512 #endif 513 514 } ppc_dma_ch_t; 515 516 /* 517 * PPC44x DMA implementations have a slightly different 518 * descriptor layout. Probably moved about due to the 519 * change to 64-bit addresses and link pointer. I don't 520 * know why they didn't just leave control_count after 521 * the dst_addr. 522 */ 523 #ifdef PPC4xx_DMA_64BIT 524 typedef struct { 525 uint32_t control; 526 uint32_t control_count; 527 phys_addr_t src_addr; 528 phys_addr_t dst_addr; 529 phys_addr_t next; 530 } ppc_sgl_t; 531 #else 532 typedef struct { 533 uint32_t control; 534 phys_addr_t src_addr; 535 phys_addr_t dst_addr; 536 uint32_t control_count; 537 uint32_t next; 538 } ppc_sgl_t; 539 #endif 540 541 typedef struct { 542 unsigned int dmanr; 543 uint32_t control; /* channel ctrl word; loaded from each descrptr */ 544 uint32_t sgl_control; /* LK, TCI, ETI, and ERI bits in sgl descriptor */ 545 dma_addr_t dma_addr; /* dma (physical) address of this list */ 546 ppc_sgl_t *phead; 547 ppc_sgl_t *ptail; 548 uint32_t pad32[2]; 549 550 } sgl_list_info_t; 551 552 typedef struct { 553 phys_addr_t *src_addr; 554 phys_addr_t *dst_addr; 555 phys_addr_t dma_src_addr; 556 phys_addr_t dma_dst_addr; 557 } pci_alloc_desc_t; 558 559 extern ppc_dma_ch_t dma_channels[]; 560 561 /* 562 * The DMA API are in ppc4xx_dma.c and ppc4xx_sgdma.c 563 */ 564 extern int ppc4xx_init_dma_channel(unsigned int, ppc_dma_ch_t *); 565 extern int ppc4xx_get_channel_config(unsigned int, ppc_dma_ch_t *); 566 extern int ppc4xx_set_channel_priority(unsigned int, unsigned int); 567 extern unsigned int ppc4xx_get_peripheral_width(unsigned int); 568 extern int ppc4xx_alloc_dma_handle(sgl_handle_t *, unsigned int, unsigned int); 569 extern void ppc4xx_free_dma_handle(sgl_handle_t); 570 extern int ppc4xx_get_dma_status(void); 571 extern void ppc4xx_set_src_addr(int dmanr, phys_addr_t src_addr); 572 extern void ppc4xx_set_dst_addr(int dmanr, phys_addr_t dst_addr); 573 extern void ppc4xx_enable_dma(unsigned int dmanr); 574 extern void ppc4xx_disable_dma(unsigned int dmanr); 575 extern void ppc4xx_set_dma_count(unsigned int dmanr, unsigned int count); 576 extern int ppc4xx_get_dma_residue(unsigned int dmanr); 577 extern void ppc4xx_set_dma_addr2(unsigned int dmanr, phys_addr_t src_dma_addr, 578 phys_addr_t dst_dma_addr); 579 extern int ppc4xx_enable_dma_interrupt(unsigned int dmanr); 580 extern int ppc4xx_disable_dma_interrupt(unsigned int dmanr); 581 extern int ppc4xx_clr_dma_status(unsigned int dmanr); 582 extern int ppc4xx_map_dma_port(unsigned int dmanr, unsigned int ocp_dma,short dma_chan); 583 extern int ppc4xx_disable_dma_port(unsigned int dmanr, unsigned int ocp_dma,short dma_chan); 584 extern int ppc4xx_set_dma_mode(unsigned int dmanr, unsigned int mode); 585 586 /* These are in kernel/dma.c: */ 587 588 /* reserve a DMA channel */ 589 extern int request_dma(unsigned int dmanr, const char *device_id); 590 /* release it again */ 591 extern void free_dma(unsigned int dmanr); 592 #endif 593 #endif /* __KERNEL__ */ 594