1 /* 2 * keylargo.h: definitions for using the "KeyLargo" I/O controller chip. 3 * 4 */ 5 6 /* "Pangea" chipset has keylargo device-id 0x25 while core99 7 * has device-id 0x22. The rev. of the pangea one is 0, so we 8 * fake an artificial rev. in keylargo_rev by oring 0x100 9 */ 10 #define KL_PANGEA_REV 0x100 11 12 /* offset from base for feature control registers */ 13 #define KEYLARGO_MBCR 0x34 /* KL Only, Media bay control/status */ 14 #define KEYLARGO_FCR0 0x38 15 #define KEYLARGO_FCR1 0x3c 16 #define KEYLARGO_FCR2 0x40 17 #define KEYLARGO_FCR3 0x44 18 #define KEYLARGO_FCR4 0x48 19 #define KEYLARGO_FCR5 0x4c /* Pangea only */ 20 21 /* GPIO registers */ 22 #define KEYLARGO_GPIO_LEVELS0 0x50 23 #define KEYLARGO_GPIO_LEVELS1 0x54 24 #define KEYLARGO_GPIO_EXTINT_0 0x58 25 #define KEYLARGO_GPIO_EXTINT_CNT 18 26 #define KEYLARGO_GPIO_0 0x6A 27 #define KEYLARGO_GPIO_CNT 17 28 #define KEYLARGO_GPIO_EXTINT_DUAL_EDGE 0x80 29 #define KEYLARGO_GPIO_OUTPUT_ENABLE 0x04 30 #define KEYLARGO_GPIO_OUTOUT_DATA 0x01 31 #define KEYLARGO_GPIO_INPUT_DATA 0x02 32 33 /* Specific GPIO regs */ 34 35 #define KL_GPIO_MODEM_RESET (KEYLARGO_GPIO_0+0x03) 36 #define KL_GPIO_MODEM_POWER (KEYLARGO_GPIO_0+0x02) /* Pangea */ 37 38 #define KL_GPIO_SOUND_POWER (KEYLARGO_GPIO_0+0x05) 39 40 /* Hrm... this one is only to be used on Pismo. It seeem to also 41 * control the timebase enable on other machines. Still to be 42 * experimented... --BenH. 43 */ 44 #define KL_GPIO_FW_CABLE_POWER (KEYLARGO_GPIO_0+0x09) 45 #define KL_GPIO_TB_ENABLE (KEYLARGO_GPIO_0+0x09) 46 47 #define KL_GPIO_ETH_PHY_RESET (KEYLARGO_GPIO_0+0x10) 48 49 #define KL_GPIO_EXTINT_CPU1 (KEYLARGO_GPIO_0+0x0a) 50 #define KL_GPIO_EXTINT_CPU1_ASSERT 0x04 51 #define KL_GPIO_EXTINT_CPU1_RELEASE 0x38 52 53 #define KL_GPIO_RESET_CPU0 (KEYLARGO_GPIO_EXTINT_0+0x03) 54 #define KL_GPIO_RESET_CPU1 (KEYLARGO_GPIO_EXTINT_0+0x04) 55 #define KL_GPIO_RESET_CPU2 (KEYLARGO_GPIO_EXTINT_0+0x0f) 56 #define KL_GPIO_RESET_CPU3 (KEYLARGO_GPIO_EXTINT_0+0x10) 57 58 #define KL_GPIO_PMU_MESSAGE_IRQ (KEYLARGO_GPIO_EXTINT_0+0x09) 59 #define KL_GPIO_PMU_MESSAGE_BIT KEYLARGO_GPIO_INPUT_DATA 60 61 #define KL_GPIO_MEDIABAY_IRQ (KEYLARGO_GPIO_EXTINT_0+0x0e) 62 63 #define KL_GPIO_AIRPORT_0 (KEYLARGO_GPIO_EXTINT_0+0x0a) 64 #define KL_GPIO_AIRPORT_1 (KEYLARGO_GPIO_EXTINT_0+0x0d) 65 #define KL_GPIO_AIRPORT_2 (KEYLARGO_GPIO_0+0x0d) 66 #define KL_GPIO_AIRPORT_3 (KEYLARGO_GPIO_0+0x0e) 67 #define KL_GPIO_AIRPORT_4 (KEYLARGO_GPIO_0+0x0f) 68 69 /* 70 * Bits in feature control register 71 */ 72 #define KL_MBCR_MB0_PCI_ENABLE 0x00000800 /* exist ? */ 73 #define KL_MBCR_MB0_IDE_ENABLE 0x00001000 74 #define KL_MBCR_MB0_FLOPPY_ENABLE 0x00002000 /* exist ? */ 75 #define KL_MBCR_MB0_SOUND_ENABLE 0x00004000 /* hrm... */ 76 #define KL_MBCR_MB0_DEV_MASK 0x00007800 77 #define KL_MBCR_MB0_DEV_POWER 0x00000400 78 #define KL_MBCR_MB0_DEV_RESET 0x00000200 79 #define KL_MBCR_MB0_ENABLE 0x00000100 80 #define KL_MBCR_MB1_PCI_ENABLE 0x08000000 /* exist ? */ 81 #define KL_MBCR_MB1_IDE_ENABLE 0x10000000 82 #define KL_MBCR_MB1_FLOPPY_ENABLE 0x20000000 /* exist ? */ 83 #define KL_MBCR_MB1_SOUND_ENABLE 0x40000000 /* hrm... */ 84 #define KL_MBCR_MB1_DEV_MASK 0x78000000 85 #define KL_MBCR_MB1_DEV_POWER 0x04000000 86 #define KL_MBCR_MB1_DEV_RESET 0x02000000 87 #define KL_MBCR_MB1_ENABLE 0x01000000 88 89 #define KL0_SCC_B_INTF_ENABLE 0x00000001 /* (KL Only) */ 90 #define KL0_SCC_A_INTF_ENABLE 0x00000002 91 #define KL0_SCC_SLOWPCLK 0x00000004 92 #define KL0_SCC_RESET 0x00000008 93 #define KL0_SCCA_ENABLE 0x00000010 94 #define KL0_SCCB_ENABLE 0x00000020 95 #define KL0_SCC_CELL_ENABLE 0x00000040 96 #define KL0_IRDA_HIGH_BAND 0x00000100 /* (KL Only) */ 97 #define KL0_IRDA_SOURCE2_SEL 0x00000200 /* (KL Only) */ 98 #define KL0_IRDA_SOURCE1_SEL 0x00000400 /* (KL Only) */ 99 #define KL0_PG_USB0_PMI_ENABLE 0x00000400 /* (Pangea/Intrepid Only) */ 100 #define KL0_IRDA_RESET 0x00000800 /* (KL Only) */ 101 #define KL0_PG_USB0_REF_SUSPEND_SEL 0x00000800 /* (Pangea/Intrepid Only) */ 102 #define KL0_IRDA_DEFAULT1 0x00001000 /* (KL Only) */ 103 #define KL0_PG_USB0_REF_SUSPEND 0x00001000 /* (Pangea/Intrepid Only) */ 104 #define KL0_IRDA_DEFAULT0 0x00002000 /* (KL Only) */ 105 #define KL0_PG_USB0_PAD_SUSPEND 0x00002000 /* (Pangea/Intrepid Only) */ 106 #define KL0_IRDA_FAST_CONNECT 0x00004000 /* (KL Only) */ 107 #define KL0_PG_USB1_PMI_ENABLE 0x00004000 /* (Pangea/Intrepid Only) */ 108 #define KL0_IRDA_ENABLE 0x00008000 /* (KL Only) */ 109 #define KL0_PG_USB1_REF_SUSPEND_SEL 0x00008000 /* (Pangea/Intrepid Only) */ 110 #define KL0_IRDA_CLK32_ENABLE 0x00010000 /* (KL Only) */ 111 #define KL0_PG_USB1_REF_SUSPEND 0x00010000 /* (Pangea/Intrepid Only) */ 112 #define KL0_IRDA_CLK19_ENABLE 0x00020000 /* (KL Only) */ 113 #define KL0_PG_USB1_PAD_SUSPEND 0x00020000 /* (Pangea/Intrepid Only) */ 114 #define KL0_USB0_PAD_SUSPEND0 0x00040000 115 #define KL0_USB0_PAD_SUSPEND1 0x00080000 116 #define KL0_USB0_CELL_ENABLE 0x00100000 117 #define KL0_USB1_PAD_SUSPEND0 0x00400000 118 #define KL0_USB1_PAD_SUSPEND1 0x00800000 119 #define KL0_USB1_CELL_ENABLE 0x01000000 120 #define KL0_USB_REF_SUSPEND 0x10000000 /* (KL Only) */ 121 122 #define KL0_SERIAL_ENABLE (KL0_SCC_B_INTF_ENABLE | \ 123 KL0_SCC_SLOWPCLK | \ 124 KL0_SCC_CELL_ENABLE | KL0_SCCA_ENABLE) 125 126 #define KL1_USB2_PMI_ENABLE 0x00000001 /* Intrepid only */ 127 #define KL1_AUDIO_SEL_22MCLK 0x00000002 /* KL/Pangea only */ 128 #define KL1_USB2_REF_SUSPEND_SEL 0x00000002 /* Intrepid only */ 129 #define KL1_USB2_REF_SUSPEND 0x00000004 /* Intrepid only */ 130 #define KL1_AUDIO_CLK_ENABLE_BIT 0x00000008 /* KL/Pangea only */ 131 #define KL1_USB2_PAD_SUSPEND_SEL 0x00000008 /* Intrepid only */ 132 #define KL1_USB2_PAD_SUSPEND0 0x00000010 /* Intrepid only */ 133 #define KL1_AUDIO_CLK_OUT_ENABLE 0x00000020 /* KL/Pangea only */ 134 #define KL1_USB2_PAD_SUSPEND1 0x00000020 /* Intrepid only */ 135 #define KL1_AUDIO_CELL_ENABLE 0x00000040 /* KL/Pangea only */ 136 #define KL1_USB2_CELL_ENABLE 0x00000040 /* Intrepid only */ 137 #define KL1_AUDIO_CHOOSE 0x00000080 /* KL/Pangea only */ 138 #define KL1_I2S0_CHOOSE 0x00000200 /* KL Only */ 139 #define KL1_I2S0_CELL_ENABLE 0x00000400 140 #define KL1_I2S0_CLK_ENABLE_BIT 0x00001000 141 #define KL1_I2S0_ENABLE 0x00002000 142 #define KL1_I2S1_CELL_ENABLE 0x00020000 143 #define KL1_I2S1_CLK_ENABLE_BIT 0x00080000 144 #define KL1_I2S1_ENABLE 0x00100000 145 #define KL1_EIDE0_ENABLE 0x00800000 /* KL/Intrepid Only */ 146 #define KL1_EIDE0_RESET_N 0x01000000 /* KL/Intrepid Only */ 147 #define KL1_EIDE1_ENABLE 0x04000000 /* KL Only */ 148 #define KL1_EIDE1_RESET_N 0x08000000 /* KL Only */ 149 #define KL1_UIDE_ENABLE 0x20000000 /* KL/Pangea Only */ 150 #define KL1_UIDE_RESET_N 0x40000000 /* KL/Pangea Only */ 151 152 #define KL2_IOBUS_ENABLE 0x00000002 153 #define KL2_SLEEP_STATE_BIT 0x00000100 /* KL Only */ 154 #define KL2_PG_STOP_ALL_CLOCKS 0x00000100 /* Pangea Only */ 155 #define KL2_MPIC_ENABLE 0x00020000 156 #define KL2_CARDSLOT_RESET 0x00040000 /* Pangea/Intrepid Only */ 157 #define KL2_ALT_DATA_OUT 0x02000000 /* KL Only ??? */ 158 #define KL2_MEM_IS_BIG 0x04000000 159 #define KL2_CARDSEL_16 0x08000000 160 161 #define KL3_SHUTDOWN_PLL_TOTAL 0x00000001 /* KL/Pangea only */ 162 #define KL3_SHUTDOWN_PLLKW6 0x00000002 /* KL/Pangea only */ 163 #define KL3_IT_SHUTDOWN_PLL3 0x00000002 /* Intrepid only */ 164 #define KL3_SHUTDOWN_PLLKW4 0x00000004 /* KL/Pangea only */ 165 #define KL3_IT_SHUTDOWN_PLL2 0x00000004 /* Intrepid only */ 166 #define KL3_SHUTDOWN_PLLKW35 0x00000008 /* KL/Pangea only */ 167 #define KL3_IT_SHUTDOWN_PLL1 0x00000008 /* Intrepid only */ 168 #define KL3_SHUTDOWN_PLLKW12 0x00000010 /* KL Only */ 169 #define KL3_IT_ENABLE_PLL3_SHUTDOWN 0x00000010 /* Intrepid only */ 170 #define KL3_PLL_RESET 0x00000020 /* KL/Pangea only */ 171 #define KL3_IT_ENABLE_PLL2_SHUTDOWN 0x00000020 /* Intrepid only */ 172 #define KL3_IT_ENABLE_PLL1_SHUTDOWN 0x00000010 /* Intrepid only */ 173 #define KL3_SHUTDOWN_PLL2X 0x00000080 /* KL Only */ 174 #define KL3_CLK66_ENABLE 0x00000100 /* KL Only */ 175 #define KL3_CLK49_ENABLE 0x00000200 176 #define KL3_CLK45_ENABLE 0x00000400 177 #define KL3_CLK31_ENABLE 0x00000800 /* KL/Pangea only */ 178 #define KL3_TIMER_CLK18_ENABLE 0x00001000 179 #define KL3_I2S1_CLK18_ENABLE 0x00002000 180 #define KL3_I2S0_CLK18_ENABLE 0x00004000 181 #define KL3_VIA_CLK16_ENABLE 0x00008000 /* KL/Pangea only */ 182 #define KL3_IT_VIA_CLK32_ENABLE 0x00008000 /* Intrepid only */ 183 #define KL3_STOPPING33_ENABLED 0x00080000 /* KL Only */ 184 #define KL3_PG_PLL_ENABLE_TEST 0x00080000 /* Pangea Only */ 185 186 /* Intrepid USB bus 2, port 0,1 */ 187 #define KL3_IT_PORT_WAKEUP_ENABLE(p) (0x00080000 << ((p)<<3)) 188 #define KL3_IT_PORT_RESUME_WAKE_EN(p) (0x00040000 << ((p)<<3)) 189 #define KL3_IT_PORT_CONNECT_WAKE_EN(p) (0x00020000 << ((p)<<3)) 190 #define KL3_IT_PORT_DISCONNECT_WAKE_EN(p) (0x00010000 << ((p)<<3)) 191 #define KL3_IT_PORT_RESUME_STAT(p) (0x00300000 << ((p)<<3)) 192 #define KL3_IT_PORT_CONNECT_STAT(p) (0x00200000 << ((p)<<3)) 193 #define KL3_IT_PORT_DISCONNECT_STAT(p) (0x00100000 << ((p)<<3)) 194 195 /* Port 0,1 : bus 0, port 2,3 : bus 1 */ 196 #define KL4_PORT_WAKEUP_ENABLE(p) (0x00000008 << ((p)<<3)) 197 #define KL4_PORT_RESUME_WAKE_EN(p) (0x00000004 << ((p)<<3)) 198 #define KL4_PORT_CONNECT_WAKE_EN(p) (0x00000002 << ((p)<<3)) 199 #define KL4_PORT_DISCONNECT_WAKE_EN(p) (0x00000001 << ((p)<<3)) 200 #define KL4_PORT_RESUME_STAT(p) (0x00000040 << ((p)<<3)) 201 #define KL4_PORT_CONNECT_STAT(p) (0x00000020 << ((p)<<3)) 202 #define KL4_PORT_DISCONNECT_STAT(p) (0x00000010 << ((p)<<3)) 203 204 /* Pangea and Intrepid only */ 205 #define KL5_VIA_USE_CLK31 0x000000001 /* Pangea Only */ 206 #define KL5_SCC_USE_CLK31 0x000000002 /* Pangea Only */ 207 #define KL5_PWM_CLK32_EN 0x000000004 208 #define KL5_CLK3_68_EN 0x000000010 209 #define KL5_CLK32_EN 0x000000020 210 211