1 /* 2 * MPC8xx Internal Memory Map 3 * Copyright (c) 1997 Dan Malek (dmalek@jlc.net) 4 * 5 * The I/O on the MPC860 is comprised of blocks of special registers 6 * and the dual port ram for the Communication Processor Module. 7 * Within this space are functional units such as the SIU, memory 8 * controller, system timers, and other control functions. It is 9 * a combination that I found difficult to separate into logical 10 * functional files.....but anyone else is welcome to try. -- Dan 11 */ 12 #ifdef __KERNEL__ 13 #ifndef __IMMAP_8XX__ 14 #define __IMMAP_8XX__ 15 16 /* System configuration registers. 17 */ 18 typedef struct sys_conf { 19 uint sc_siumcr; 20 uint sc_sypcr; 21 uint sc_swt; 22 char res1[2]; 23 ushort sc_swsr; 24 uint sc_sipend; 25 uint sc_simask; 26 uint sc_siel; 27 uint sc_sivec; 28 uint sc_tesr; 29 char res2[0xc]; 30 uint sc_sdcr; 31 char res3[0x4c]; 32 } sysconf8xx_t; 33 34 /* PCMCIA configuration registers. 35 */ 36 typedef struct pcmcia_conf { 37 uint pcmc_pbr0; 38 uint pcmc_por0; 39 uint pcmc_pbr1; 40 uint pcmc_por1; 41 uint pcmc_pbr2; 42 uint pcmc_por2; 43 uint pcmc_pbr3; 44 uint pcmc_por3; 45 uint pcmc_pbr4; 46 uint pcmc_por4; 47 uint pcmc_pbr5; 48 uint pcmc_por5; 49 uint pcmc_pbr6; 50 uint pcmc_por6; 51 uint pcmc_pbr7; 52 uint pcmc_por7; 53 char res1[0x20]; 54 uint pcmc_pgcra; 55 uint pcmc_pgcrb; 56 uint pcmc_pscr; 57 char res2[4]; 58 uint pcmc_pipr; 59 char res3[4]; 60 uint pcmc_per; 61 char res4[4]; 62 } pcmconf8xx_t; 63 64 /* Memory controller registers. 65 */ 66 typedef struct mem_ctlr { 67 uint memc_br0; 68 uint memc_or0; 69 uint memc_br1; 70 uint memc_or1; 71 uint memc_br2; 72 uint memc_or2; 73 uint memc_br3; 74 uint memc_or3; 75 uint memc_br4; 76 uint memc_or4; 77 uint memc_br5; 78 uint memc_or5; 79 uint memc_br6; 80 uint memc_or6; 81 uint memc_br7; 82 uint memc_or7; 83 char res1[0x24]; 84 uint memc_mar; 85 uint memc_mcr; 86 char res2[4]; 87 uint memc_mamr; 88 uint memc_mbmr; 89 ushort memc_mstat; 90 ushort memc_mptpr; 91 uint memc_mdr; 92 char res3[0x80]; 93 } memctl8xx_t; 94 95 /* System Integration Timers. 96 */ 97 typedef struct sys_int_timers { 98 ushort sit_tbscr; 99 uint sit_tbreff0; 100 uint sit_tbreff1; 101 char res1[0x14]; 102 ushort sit_rtcsc; 103 uint sit_rtc; 104 uint sit_rtsec; 105 uint sit_rtcal; 106 char res2[0x10]; 107 ushort sit_piscr; 108 char res3[2]; 109 uint sit_pitc; 110 uint sit_pitr; 111 char res4[0x34]; 112 } sit8xx_t; 113 114 #define TBSCR_TBIRQ_MASK ((ushort)0xff00) 115 #define TBSCR_REFA ((ushort)0x0080) 116 #define TBSCR_REFB ((ushort)0x0040) 117 #define TBSCR_REFAE ((ushort)0x0008) 118 #define TBSCR_REFBE ((ushort)0x0004) 119 #define TBSCR_TBF ((ushort)0x0002) 120 #define TBSCR_TBE ((ushort)0x0001) 121 122 #define RTCSC_RTCIRQ_MASK ((ushort)0xff00) 123 #define RTCSC_SEC ((ushort)0x0080) 124 #define RTCSC_ALR ((ushort)0x0040) 125 #define RTCSC_38K ((ushort)0x0010) 126 #define RTCSC_SIE ((ushort)0x0008) 127 #define RTCSC_ALE ((ushort)0x0004) 128 #define RTCSC_RTF ((ushort)0x0002) 129 #define RTCSC_RTE ((ushort)0x0001) 130 131 #define PISCR_PIRQ_MASK ((ushort)0xff00) 132 #define PISCR_PS ((ushort)0x0080) 133 #define PISCR_PIE ((ushort)0x0004) 134 #define PISCR_PTF ((ushort)0x0002) 135 #define PISCR_PTE ((ushort)0x0001) 136 137 /* Clocks and Reset. 138 */ 139 typedef struct clk_and_reset { 140 uint car_sccr; 141 uint car_plprcr; 142 uint car_rsr; 143 char res[0x74]; /* Reserved area */ 144 } car8xx_t; 145 146 /* System Integration Timers keys. 147 */ 148 typedef struct sitk { 149 uint sitk_tbscrk; 150 uint sitk_tbreff0k; 151 uint sitk_tbreff1k; 152 uint sitk_tbk; 153 char res1[0x10]; 154 uint sitk_rtcsck; 155 uint sitk_rtck; 156 uint sitk_rtseck; 157 uint sitk_rtcalk; 158 char res2[0x10]; 159 uint sitk_piscrk; 160 uint sitk_pitck; 161 char res3[0x38]; 162 } sitk8xx_t; 163 164 /* Clocks and reset keys. 165 */ 166 typedef struct cark { 167 uint cark_sccrk; 168 uint cark_plprcrk; 169 uint cark_rsrk; 170 char res[0x474]; 171 } cark8xx_t; 172 173 /* The key to unlock registers maintained by keep-alive power. 174 */ 175 #define KAPWR_KEY ((unsigned int)0x55ccaa33) 176 177 /* LCD interface. MPC821 Only. 178 */ 179 typedef struct lcd { 180 ushort lcd_lcolr[16]; 181 char res[0x20]; 182 uint lcd_lccr; 183 uint lcd_lchcr; 184 uint lcd_lcvcr; 185 char res2[4]; 186 uint lcd_lcfaa; 187 uint lcd_lcfba; 188 char lcd_lcsr; 189 char res3[0x7]; 190 } lcd8xx_t; 191 192 /* I2C 193 */ 194 typedef struct i2c { 195 u_char i2c_i2mod; 196 char res1[3]; 197 u_char i2c_i2add; 198 char res2[3]; 199 u_char i2c_i2brg; 200 char res3[3]; 201 u_char i2c_i2com; 202 char res4[3]; 203 u_char i2c_i2cer; 204 char res5[3]; 205 u_char i2c_i2cmr; 206 char res6[0x8b]; 207 } i2c8xx_t; 208 209 /* DMA control/status registers. 210 */ 211 typedef struct sdma_csr { 212 char res1[4]; 213 uint sdma_sdar; 214 u_char sdma_sdsr; 215 char res3[3]; 216 u_char sdma_sdmr; 217 char res4[3]; 218 u_char sdma_idsr1; 219 char res5[3]; 220 u_char sdma_idmr1; 221 char res6[3]; 222 u_char sdma_idsr2; 223 char res7[3]; 224 u_char sdma_idmr2; 225 char res8[0x13]; 226 } sdma8xx_t; 227 228 /* Communication Processor Module Interrupt Controller. 229 */ 230 typedef struct cpm_ic { 231 ushort cpic_civr; 232 char res[0xe]; 233 uint cpic_cicr; 234 uint cpic_cipr; 235 uint cpic_cimr; 236 uint cpic_cisr; 237 } cpic8xx_t; 238 239 /* Input/Output Port control/status registers. 240 */ 241 typedef struct io_port { 242 ushort iop_padir; 243 ushort iop_papar; 244 ushort iop_paodr; 245 ushort iop_padat; 246 char res1[8]; 247 ushort iop_pcdir; 248 ushort iop_pcpar; 249 ushort iop_pcso; 250 ushort iop_pcdat; 251 ushort iop_pcint; 252 char res2[6]; 253 ushort iop_pddir; 254 ushort iop_pdpar; 255 char res3[2]; 256 ushort iop_pddat; 257 char res4[8]; 258 } iop8xx_t; 259 260 /* Communication Processor Module Timers 261 */ 262 typedef struct cpm_timers { 263 ushort cpmt_tgcr; 264 char res1[0xe]; 265 ushort cpmt_tmr1; 266 ushort cpmt_tmr2; 267 ushort cpmt_trr1; 268 ushort cpmt_trr2; 269 ushort cpmt_tcr1; 270 ushort cpmt_tcr2; 271 ushort cpmt_tcn1; 272 ushort cpmt_tcn2; 273 ushort cpmt_tmr3; 274 ushort cpmt_tmr4; 275 ushort cpmt_trr3; 276 ushort cpmt_trr4; 277 ushort cpmt_tcr3; 278 ushort cpmt_tcr4; 279 ushort cpmt_tcn3; 280 ushort cpmt_tcn4; 281 ushort cpmt_ter1; 282 ushort cpmt_ter2; 283 ushort cpmt_ter3; 284 ushort cpmt_ter4; 285 char res2[8]; 286 } cpmtimer8xx_t; 287 288 /* Finally, the Communication Processor stuff..... 289 */ 290 typedef struct scc { /* Serial communication channels */ 291 uint scc_gsmrl; 292 uint scc_gsmrh; 293 ushort scc_pmsr; 294 char res1[2]; 295 ushort scc_todr; 296 ushort scc_dsr; 297 ushort scc_scce; 298 char res2[2]; 299 ushort scc_sccm; 300 char res3; 301 u_char scc_sccs; 302 char res4[8]; 303 } scc_t; 304 305 typedef struct smc { /* Serial management channels */ 306 char res1[2]; 307 ushort smc_smcmr; 308 char res2[2]; 309 u_char smc_smce; 310 char res3[3]; 311 u_char smc_smcm; 312 char res4[5]; 313 } smc_t; 314 315 /* MPC860T Fast Ethernet Controller. It isn't part of the CPM, but 316 * it fits within the address space. 317 */ 318 typedef struct fec { 319 uint fec_addr_low; /* LS 32 bits of station address */ 320 ushort fec_addr_high; /* MS 16 bits of address */ 321 ushort res1; 322 uint fec_hash_table_high; 323 uint fec_hash_table_low; 324 uint fec_r_des_start; 325 uint fec_x_des_start; 326 uint fec_r_buff_size; 327 uint res2[9]; 328 uint fec_ecntrl; 329 uint fec_ievent; 330 uint fec_imask; 331 uint fec_ivec; 332 uint fec_r_des_active; 333 uint fec_x_des_active; 334 uint res3[10]; 335 uint fec_mii_data; 336 uint fec_mii_speed; 337 uint res4[17]; 338 uint fec_r_bound; 339 uint fec_r_fstart; 340 uint res5[6]; 341 uint fec_x_fstart; 342 uint res6[17]; 343 uint fec_fun_code; 344 uint res7[3]; 345 uint fec_r_cntrl; 346 uint fec_r_hash; 347 uint res8[14]; 348 uint fec_x_cntrl; 349 uint res9[0x1e]; 350 } fec_t; 351 352 typedef struct comm_proc { 353 /* General control and status registers. 354 */ 355 ushort cp_cpcr; 356 char res1[2]; 357 ushort cp_rccr; 358 char res2[6]; 359 ushort cp_cpmcr1; 360 ushort cp_cpmcr2; 361 ushort cp_cpmcr3; 362 ushort cp_cpmcr4; 363 char res3[2]; 364 ushort cp_rter; 365 char res4[2]; 366 ushort cp_rtmr; 367 char res5[0x14]; 368 369 /* Baud rate generators. 370 */ 371 uint cp_brgc1; 372 uint cp_brgc2; 373 uint cp_brgc3; 374 uint cp_brgc4; 375 376 /* Serial Communication Channels. 377 */ 378 scc_t cp_scc[4]; 379 380 /* Serial Management Channels. 381 */ 382 smc_t cp_smc[2]; 383 384 /* Serial Peripheral Interface. 385 */ 386 ushort cp_spmode; 387 char res6[4]; 388 u_char cp_spie; 389 char res7[3]; 390 u_char cp_spim; 391 char res8[2]; 392 u_char cp_spcom; 393 char res9[2]; 394 395 /* Parallel Interface Port. 396 */ 397 char res10[2]; 398 ushort cp_pipc; 399 char res11[2]; 400 ushort cp_ptpr; 401 uint cp_pbdir; 402 uint cp_pbpar; 403 char res12[2]; 404 ushort cp_pbodr; 405 uint cp_pbdat; 406 char res13[0x18]; 407 408 /* Serial Interface and Time Slot Assignment. 409 */ 410 uint cp_simode; 411 u_char cp_sigmr; 412 char res14; 413 u_char cp_sistr; 414 u_char cp_sicmr; 415 char res15[4]; 416 uint cp_sicr; 417 uint cp_sirp; 418 char res16[0x10c]; 419 u_char cp_siram[0x200]; 420 421 /* The fast ethernet controller is not really part of the CPM, 422 * but it resides in the address space. 423 */ 424 fec_t cp_fec; 425 char res18[0x1000]; 426 427 /* Dual Ported RAM follows. 428 * There are many different formats for this memory area 429 * depending upon the devices used and options chosen. 430 */ 431 u_char cp_dpmem[0x1000]; /* BD / Data / ucode */ 432 u_char res19[0xc00]; 433 u_char cp_dparam[0x400]; /* Parameter RAM */ 434 } cpm8xx_t; 435 436 /* Internal memory map. 437 */ 438 typedef struct immap { 439 sysconf8xx_t im_siu_conf; /* SIU Configuration */ 440 pcmconf8xx_t im_pcmcia; /* PCMCIA Configuration */ 441 memctl8xx_t im_memctl; /* Memory Controller */ 442 sit8xx_t im_sit; /* System integration timers */ 443 car8xx_t im_clkrst; /* Clocks and reset */ 444 sitk8xx_t im_sitk; /* Sys int timer keys */ 445 cark8xx_t im_clkrstk; /* Clocks and reset keys */ 446 lcd8xx_t im_lcd; /* LCD (821 only) */ 447 i2c8xx_t im_i2c; /* I2C control/status */ 448 sdma8xx_t im_sdma; /* SDMA control/status */ 449 cpic8xx_t im_cpic; /* CPM Interrupt Controller */ 450 iop8xx_t im_ioport; /* IO Port control/status */ 451 cpmtimer8xx_t im_cpmtimer; /* CPM timers */ 452 cpm8xx_t im_cpm; /* Communication processor */ 453 } immap_t; 454 455 #endif /* __IMMAP_8XX__ */ 456 #endif /* __KERNEL__ */ 457