1 /* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Copyright (C) 1992 - 1997 Silicon Graphics, Inc. 7 */ 8 #ifndef __ASM_SN_INTR_H 9 #define __ASM_SN_INTR_H 10 11 /* Number of interrupt levels associated with each interrupt register. */ 12 #define N_INTPEND_BITS 64 13 14 #define INT_PEND0_BASELVL 0 15 #define INT_PEND1_BASELVL 64 16 17 #define N_INTPENDJUNK_BITS 8 18 #define INTPENDJUNK_CLRBIT 0x80 19 20 #include <asm/sn/intr_public.h> 21 22 #ifndef __ASSEMBLY__ 23 24 /* 25 * Macros to manipulate the interrupt register on the calling hub chip. 26 */ 27 28 #define LOCAL_HUB_SEND_INTR(_level) LOCAL_HUB_S(PI_INT_PEND_MOD, \ 29 (0x100|(_level))) 30 #define REMOTE_HUB_SEND_INTR(_hub, _level) \ 31 REMOTE_HUB_S((_hub), PI_INT_PEND_MOD, (0x100|(_level))) 32 33 /* 34 * When clearing the interrupt, make sure this clear does make it 35 * to the hub. Otherwise we could end up losing interrupts. 36 * We do an uncached load of the int_pend0 register to ensure this. 37 */ 38 39 #define LOCAL_HUB_CLR_INTR(_level) \ 40 LOCAL_HUB_S(PI_INT_PEND_MOD, (_level)), \ 41 LOCAL_HUB_L(PI_INT_PEND0) 42 #define REMOTE_HUB_CLR_INTR(_hub, _level) \ 43 REMOTE_HUB_S((_hub), PI_INT_PEND_MOD, (_level)), \ 44 REMOTE_HUB_L((_hub), PI_INT_PEND0) 45 46 #else /* __ASSEMBLY__ */ 47 48 #endif /* __ASSEMBLY__ */ 49 50 /* 51 * Hard-coded interrupt levels: 52 */ 53 54 /* 55 * L0 = SW1 56 * L1 = SW2 57 * L2 = INT_PEND0 58 * L3 = INT_PEND1 59 * L4 = RTC 60 * L5 = Profiling Timer 61 * L6 = Hub Errors 62 * L7 = Count/Compare (T5 counters) 63 */ 64 65 66 /* INT_PEND0 hard-coded bits. */ 67 #ifdef SABLE 68 #define SDISK_INTR 63 69 #endif 70 #ifdef DEBUG_INTR_TSTAMP 71 /* hard coded interrupt level for interrupt latency test interrupt */ 72 #define CPU_INTRLAT_B 62 73 #define CPU_INTRLAT_A 61 74 #endif 75 76 /* Hardcoded bits required by software. */ 77 #define MSC_MESG_INTR 13 78 #define CPU_ACTION_B 11 79 #define CPU_ACTION_A 10 80 81 /* These are determined by hardware: */ 82 #define CC_PEND_B 6 83 #define CC_PEND_A 5 84 #define UART_INTR 4 85 #define PG_MIG_INTR 3 86 #define GFX_INTR_B 2 87 #define GFX_INTR_A 1 88 #define RESERVED_INTR 0 89 90 /* INT_PEND1 hard-coded bits: */ 91 #define MSC_PANIC_INTR 63 92 #define NI_ERROR_INTR 62 93 #define MD_COR_ERR_INTR 61 94 #define COR_ERR_INTR_B 60 95 #define COR_ERR_INTR_A 59 96 #define CLK_ERR_INTR 58 97 #define IO_ERROR_INTR 57 /* set up by prom */ 98 99 #define DEBUG_INTR_B 55 /* used by symmon to stop all cpus */ 100 #define DEBUG_INTR_A 54 101 102 #define BRIDGE_ERROR_INTR 53 /* Setup by PROM to catch Bridge Errors */ 103 104 #define IP27_INTR_0 52 /* Reserved for PROM use */ 105 #define IP27_INTR_1 51 /* (do not use in Kernel) */ 106 #define IP27_INTR_2 50 107 #define IP27_INTR_3 49 108 #define IP27_INTR_4 48 109 #define IP27_INTR_5 47 110 #define IP27_INTR_6 46 111 #define IP27_INTR_7 45 112 113 #define TLB_INTR_B 44 /* used for tlb flush random */ 114 #define TLB_INTR_A 43 115 116 #define LLP_PFAIL_INTR_B 42 /* see ml/SN/SN0/sysctlr.c */ 117 #define LLP_PFAIL_INTR_A 41 118 119 #define NI_BRDCAST_ERR_B 40 120 #define NI_BRDCAST_ERR_A 39 121 122 #endif /* __ASM_SN_INTR_H */ 123