1 /* 2 * linux/include/asm/traps.h 3 * 4 * Copyright (C) 1993 Hamish Macdonald 5 * 6 * This file is subject to the terms and conditions of the GNU General Public 7 * License. See the file COPYING in the main directory of this archive 8 * for more details. 9 */ 10 11 #ifndef _M68K_TRAPS_H 12 #define _M68K_TRAPS_H 13 14 #ifndef __ASSEMBLY__ 15 16 typedef void (*e_vector)(void); 17 18 extern e_vector vectors[]; 19 20 #endif 21 22 #define VEC_BUSERR (2) 23 #define VEC_ADDRERR (3) 24 #define VEC_ILLEGAL (4) 25 #define VEC_ZERODIV (5) 26 #define VEC_CHK (6) 27 #define VEC_TRAP (7) 28 #define VEC_PRIV (8) 29 #define VEC_TRACE (9) 30 #define VEC_LINE10 (10) 31 #define VEC_LINE11 (11) 32 #define VEC_RESV1 (12) 33 #define VEC_COPROC (13) 34 #define VEC_FORMAT (14) 35 #define VEC_UNINT (15) 36 #define VEC_SPUR (24) 37 #define VEC_INT1 (25) 38 #define VEC_INT2 (26) 39 #define VEC_INT3 (27) 40 #define VEC_INT4 (28) 41 #define VEC_INT5 (29) 42 #define VEC_INT6 (30) 43 #define VEC_INT7 (31) 44 #define VEC_SYS (32) 45 #define VEC_TRAP1 (33) 46 #define VEC_TRAP2 (34) 47 #define VEC_TRAP3 (35) 48 #define VEC_TRAP4 (36) 49 #define VEC_TRAP5 (37) 50 #define VEC_TRAP6 (38) 51 #define VEC_TRAP7 (39) 52 #define VEC_TRAP8 (40) 53 #define VEC_TRAP9 (41) 54 #define VEC_TRAP10 (42) 55 #define VEC_TRAP11 (43) 56 #define VEC_TRAP12 (44) 57 #define VEC_TRAP13 (45) 58 #define VEC_TRAP14 (46) 59 #define VEC_TRAP15 (47) 60 #define VEC_FPBRUC (48) 61 #define VEC_FPIR (49) 62 #define VEC_FPDIVZ (50) 63 #define VEC_FPUNDER (51) 64 #define VEC_FPOE (52) 65 #define VEC_FPOVER (53) 66 #define VEC_FPNAN (54) 67 #define VEC_FPUNSUP (55) 68 #define VEC_UNIMPEA (60) 69 #define VEC_UNIMPII (61) 70 #define VEC_USER (64) 71 72 #define VECOFF(vec) ((vec)<<2) 73 74 #ifndef __ASSEMBLY__ 75 76 /* Status register bits */ 77 #define PS_T (0x8000) 78 #define PS_S (0x2000) 79 #define PS_M (0x1000) 80 #define PS_C (0x0001) 81 82 /* bits for 68020/68030 special status word */ 83 84 #define FC (0x8000) 85 #define FB (0x4000) 86 #define RC (0x2000) 87 #define RB (0x1000) 88 #define DF (0x0100) 89 #define RM (0x0080) 90 #define RW (0x0040) 91 #define SZ (0x0030) 92 #define DFC (0x0007) 93 94 /* bits for 68030 MMU status register (mmusr,psr) */ 95 96 #define MMU_B (0x8000) /* bus error */ 97 #define MMU_L (0x4000) /* limit violation */ 98 #define MMU_S (0x2000) /* supervisor violation */ 99 #define MMU_WP (0x0800) /* write-protected */ 100 #define MMU_I (0x0400) /* invalid descriptor */ 101 #define MMU_M (0x0200) /* ATC entry modified */ 102 #define MMU_T (0x0040) /* transparent translation */ 103 #define MMU_NUM (0x0007) /* number of levels traversed */ 104 105 106 /* bits for 68040 special status word */ 107 #define CP_040 (0x8000) 108 #define CU_040 (0x4000) 109 #define CT_040 (0x2000) 110 #define CM_040 (0x1000) 111 #define MA_040 (0x0800) 112 #define ATC_040 (0x0400) 113 #define LK_040 (0x0200) 114 #define RW_040 (0x0100) 115 #define SIZ_040 (0x0060) 116 #define TT_040 (0x0018) 117 #define TM_040 (0x0007) 118 119 /* bits for 68040 write back status word */ 120 #define WBV_040 (0x80) 121 #define WBSIZ_040 (0x60) 122 #define WBBYT_040 (0x20) 123 #define WBWRD_040 (0x40) 124 #define WBLNG_040 (0x00) 125 #define WBTT_040 (0x18) 126 #define WBTM_040 (0x07) 127 128 /* bus access size codes */ 129 #define BA_SIZE_BYTE (0x20) 130 #define BA_SIZE_WORD (0x40) 131 #define BA_SIZE_LONG (0x00) 132 #define BA_SIZE_LINE (0x60) 133 134 /* bus access transfer type codes */ 135 #define BA_TT_MOVE16 (0x08) 136 137 /* bits for 68040 MMU status register (mmusr) */ 138 #define MMU_B_040 (0x0800) 139 #define MMU_G_040 (0x0400) 140 #define MMU_S_040 (0x0080) 141 #define MMU_CM_040 (0x0060) 142 #define MMU_M_040 (0x0010) 143 #define MMU_WP_040 (0x0004) 144 #define MMU_T_040 (0x0002) 145 #define MMU_R_040 (0x0001) 146 147 /* bits in the 68060 fault status long word (FSLW) */ 148 #define MMU060_MA (0x08000000) /* misaligned */ 149 #define MMU060_LK (0x02000000) /* locked transfer */ 150 #define MMU060_RW (0x01800000) /* read/write */ 151 # define MMU060_RW_W (0x00800000) /* write */ 152 # define MMU060_RW_R (0x01000000) /* read */ 153 # define MMU060_RW_RMW (0x01800000) /* read/modify/write */ 154 # define MMU060_W (0x00800000) /* general write, includes rmw */ 155 #define MMU060_SIZ (0x00600000) /* transfer size */ 156 #define MMU060_TT (0x00180000) /* transfer type (TT) bits */ 157 #define MMU060_TM (0x00070000) /* transfer modifier (TM) bits */ 158 #define MMU060_IO (0x00008000) /* instruction or operand */ 159 #define MMU060_PBE (0x00004000) /* push buffer bus error */ 160 #define MMU060_SBE (0x00002000) /* store buffer bus error */ 161 #define MMU060_PTA (0x00001000) /* pointer A fault */ 162 #define MMU060_PTB (0x00000800) /* pointer B fault */ 163 #define MMU060_IL (0x00000400) /* double indirect descr fault */ 164 #define MMU060_PF (0x00000200) /* page fault (invalid descr) */ 165 #define MMU060_SP (0x00000100) /* supervisor protection */ 166 #define MMU060_WP (0x00000080) /* write protection */ 167 #define MMU060_TWE (0x00000040) /* bus error on table search */ 168 #define MMU060_RE (0x00000020) /* bus error on read */ 169 #define MMU060_WE (0x00000010) /* bus error on write */ 170 #define MMU060_TTR (0x00000008) /* error caused by TTR translation */ 171 #define MMU060_BPE (0x00000004) /* branch prediction error */ 172 #define MMU060_SEE (0x00000001) /* software emulated error */ 173 174 /* cases of missing or invalid descriptors */ 175 #define MMU060_DESC_ERR (MMU060_PTA | MMU060_PTB | \ 176 MMU060_IL | MMU060_PF) 177 /* bits that indicate real errors */ 178 #define MMU060_ERR_BITS (MMU060_PBE | MMU060_SBE | MMU060_DESC_ERR | MMU060_SP | \ 179 MMU060_WP | MMU060_TWE | MMU060_RE | MMU060_WE) 180 181 /* structure for stack frames */ 182 183 struct frame { 184 struct pt_regs ptregs; 185 union { 186 struct { 187 unsigned long iaddr; /* instruction address */ 188 } fmt2; 189 struct { 190 unsigned long effaddr; /* effective address */ 191 } fmt3; 192 struct { 193 unsigned long effaddr; /* effective address */ 194 unsigned long pc; /* pc of faulted instr */ 195 } fmt4; 196 struct { 197 unsigned long effaddr; /* effective address */ 198 unsigned short ssw; /* special status word */ 199 unsigned short wb3s; /* write back 3 status */ 200 unsigned short wb2s; /* write back 2 status */ 201 unsigned short wb1s; /* write back 1 status */ 202 unsigned long faddr; /* fault address */ 203 unsigned long wb3a; /* write back 3 address */ 204 unsigned long wb3d; /* write back 3 data */ 205 unsigned long wb2a; /* write back 2 address */ 206 unsigned long wb2d; /* write back 2 data */ 207 unsigned long wb1a; /* write back 1 address */ 208 unsigned long wb1dpd0; /* write back 1 data/push data 0*/ 209 unsigned long pd1; /* push data 1*/ 210 unsigned long pd2; /* push data 2*/ 211 unsigned long pd3; /* push data 3*/ 212 } fmt7; 213 struct { 214 unsigned long iaddr; /* instruction address */ 215 unsigned short int1[4]; /* internal registers */ 216 } fmt9; 217 struct { 218 unsigned short int1; 219 unsigned short ssw; /* special status word */ 220 unsigned short isc; /* instruction stage c */ 221 unsigned short isb; /* instruction stage b */ 222 unsigned long daddr; /* data cycle fault address */ 223 unsigned short int2[2]; 224 unsigned long dobuf; /* data cycle output buffer */ 225 unsigned short int3[2]; 226 } fmta; 227 struct { 228 unsigned short int1; 229 unsigned short ssw; /* special status word */ 230 unsigned short isc; /* instruction stage c */ 231 unsigned short isb; /* instruction stage b */ 232 unsigned long daddr; /* data cycle fault address */ 233 unsigned short int2[2]; 234 unsigned long dobuf; /* data cycle output buffer */ 235 unsigned short int3[4]; 236 unsigned long baddr; /* stage B address */ 237 unsigned short int4[2]; 238 unsigned long dibuf; /* data cycle input buffer */ 239 unsigned short int5[3]; 240 unsigned ver : 4; /* stack frame version # */ 241 unsigned int6:12; 242 unsigned short int7[18]; 243 } fmtb; 244 } un; 245 }; 246 247 #endif /* __ASSEMBLY__ */ 248 249 #endif /* _M68K_TRAPS_H */ 250