1 /* $Id$ 2 * 3 * This file is subject to the terms and conditions of the GNU General Public 4 * License. See the file "COPYING" in the main directory of this archive 5 * for more details. 6 * 7 * Copyright (C) 1992-1997,2000-2003 Silicon Graphics, Inc. All Rights Reserved. 8 */ 9 #ifndef _ASM_SN_SN_XTALK_XBOW_H 10 #define _ASM_SN_SN_XTALK_XBOW_H 11 12 /* 13 * xbow.h - header file for crossbow chip and xbow section of xbridge 14 */ 15 16 #include <linux/config.h> 17 #include <asm/sn/xtalk/xtalk.h> 18 #include <asm/sn/xtalk/xwidget.h> 19 #include <asm/sn/xtalk/xswitch.h> 20 #ifndef __ASSEMBLY__ 21 #include <asm/sn/xtalk/xbow_info.h> 22 #endif 23 24 25 #define XBOW_DRV_PREFIX "xbow_" 26 27 /* The crossbow chip supports 8 8/16 bits I/O ports, numbered 0x8 through 0xf. 28 * It also implements the widget 0 address space and register set. 29 */ 30 #define XBOW_PORT_0 0x0 31 #define XBOW_PORT_8 0x8 32 #define XBOW_PORT_9 0x9 33 #define XBOW_PORT_A 0xa 34 #define XBOW_PORT_B 0xb 35 #define XBOW_PORT_C 0xc 36 #define XBOW_PORT_D 0xd 37 #define XBOW_PORT_E 0xe 38 #define XBOW_PORT_F 0xf 39 40 #define MAX_XBOW_PORTS 8 /* number of ports on xbow chip */ 41 #define BASE_XBOW_PORT XBOW_PORT_8 /* Lowest external port */ 42 #define MAX_PORT_NUM 0x10 /* maximum port number + 1 */ 43 #define XBOW_WIDGET_ID 0 /* xbow is itself widget 0 */ 44 45 #define XBOW_HUBLINK_LOW 0xa 46 #define XBOW_HUBLINK_HIGH 0xb 47 48 #define XBOW_PEER_LINK(link) (link == XBOW_HUBLINK_LOW) ? \ 49 XBOW_HUBLINK_HIGH : XBOW_HUBLINK_LOW 50 51 52 #define XBOW_CREDIT 4 53 54 #define MAX_XBOW_NAME 16 55 56 #ifndef __ASSEMBLY__ 57 typedef uint32_t xbowreg_t; 58 59 #define XBOWCONST (xbowreg_t) 60 61 /* Generic xbow register, given base and offset */ 62 #define XBOW_REG_PTR(base, offset) ((volatile xbowreg_t*) \ 63 ((__psunsigned_t)(base) + (__psunsigned_t)(offset))) 64 65 /* Register set for each xbow link */ 66 typedef volatile struct xb_linkregs_s { 67 #ifdef LITTLE_ENDIAN 68 /* 69 * we access these through synergy unswizzled space, so the address 70 * gets twiddled (i.e. references to 0x4 actually go to 0x0 and vv.) 71 * That's why we put the register first and filler second. 72 */ 73 xbowreg_t link_ibf; 74 xbowreg_t filler0; /* filler for proper alignment */ 75 xbowreg_t link_control; 76 xbowreg_t filler1; 77 xbowreg_t link_status; 78 xbowreg_t filler2; 79 xbowreg_t link_arb_upper; 80 xbowreg_t filler3; 81 xbowreg_t link_arb_lower; 82 xbowreg_t filler4; 83 xbowreg_t link_status_clr; 84 xbowreg_t filler5; 85 xbowreg_t link_reset; 86 xbowreg_t filler6; 87 xbowreg_t link_aux_status; 88 xbowreg_t filler7; 89 #else 90 xbowreg_t filler0; /* filler for proper alignment */ 91 xbowreg_t link_ibf; 92 xbowreg_t filler1; 93 xbowreg_t link_control; 94 xbowreg_t filler2; 95 xbowreg_t link_status; 96 xbowreg_t filler3; 97 xbowreg_t link_arb_upper; 98 xbowreg_t filler4; 99 xbowreg_t link_arb_lower; 100 xbowreg_t filler5; 101 xbowreg_t link_status_clr; 102 xbowreg_t filler6; 103 xbowreg_t link_reset; 104 xbowreg_t filler7; 105 xbowreg_t link_aux_status; 106 #endif /* LITTLE_ENDIAN */ 107 } xb_linkregs_t; 108 109 typedef volatile struct xbow_s { 110 /* standard widget configuration 0x000000-0x000057 */ 111 widget_cfg_t xb_widget; /* 0x000000 */ 112 113 /* helper fieldnames for accessing bridge widget */ 114 115 #define xb_wid_id xb_widget.w_id 116 #define xb_wid_stat xb_widget.w_status 117 #define xb_wid_err_upper xb_widget.w_err_upper_addr 118 #define xb_wid_err_lower xb_widget.w_err_lower_addr 119 #define xb_wid_control xb_widget.w_control 120 #define xb_wid_req_timeout xb_widget.w_req_timeout 121 #define xb_wid_int_upper xb_widget.w_intdest_upper_addr 122 #define xb_wid_int_lower xb_widget.w_intdest_lower_addr 123 #define xb_wid_err_cmdword xb_widget.w_err_cmd_word 124 #define xb_wid_llp xb_widget.w_llp_cfg 125 #define xb_wid_stat_clr xb_widget.w_tflush 126 127 #ifdef LITTLE_ENDIAN 128 /* 129 * we access these through synergy unswizzled space, so the address 130 * gets twiddled (i.e. references to 0x4 actually go to 0x0 and vv.) 131 * That's why we put the register first and filler second. 132 */ 133 /* xbow-specific widget configuration 0x000058-0x0000FF */ 134 xbowreg_t xb_wid_arb_reload; /* 0x00005C */ 135 xbowreg_t _pad_000058; 136 xbowreg_t xb_perf_ctr_a; /* 0x000064 */ 137 xbowreg_t _pad_000060; 138 xbowreg_t xb_perf_ctr_b; /* 0x00006c */ 139 xbowreg_t _pad_000068; 140 xbowreg_t xb_nic; /* 0x000074 */ 141 xbowreg_t _pad_000070; 142 143 /* Xbridge only */ 144 xbowreg_t xb_w0_rst_fnc; /* 0x00007C */ 145 xbowreg_t _pad_000078; 146 xbowreg_t xb_l8_rst_fnc; /* 0x000084 */ 147 xbowreg_t _pad_000080; 148 xbowreg_t xb_l9_rst_fnc; /* 0x00008c */ 149 xbowreg_t _pad_000088; 150 xbowreg_t xb_la_rst_fnc; /* 0x000094 */ 151 xbowreg_t _pad_000090; 152 xbowreg_t xb_lb_rst_fnc; /* 0x00009c */ 153 xbowreg_t _pad_000098; 154 xbowreg_t xb_lc_rst_fnc; /* 0x0000a4 */ 155 xbowreg_t _pad_0000a0; 156 xbowreg_t xb_ld_rst_fnc; /* 0x0000ac */ 157 xbowreg_t _pad_0000a8; 158 xbowreg_t xb_le_rst_fnc; /* 0x0000b4 */ 159 xbowreg_t _pad_0000b0; 160 xbowreg_t xb_lf_rst_fnc; /* 0x0000bc */ 161 xbowreg_t _pad_0000b8; 162 xbowreg_t xb_lock; /* 0x0000c4 */ 163 xbowreg_t _pad_0000c0; 164 xbowreg_t xb_lock_clr; /* 0x0000cc */ 165 xbowreg_t _pad_0000c8; 166 /* end of Xbridge only */ 167 xbowreg_t _pad_0000d0[12]; 168 #else 169 /* xbow-specific widget configuration 0x000058-0x0000FF */ 170 xbowreg_t _pad_000058; 171 xbowreg_t xb_wid_arb_reload; /* 0x00005C */ 172 xbowreg_t _pad_000060; 173 xbowreg_t xb_perf_ctr_a; /* 0x000064 */ 174 xbowreg_t _pad_000068; 175 xbowreg_t xb_perf_ctr_b; /* 0x00006c */ 176 xbowreg_t _pad_000070; 177 xbowreg_t xb_nic; /* 0x000074 */ 178 179 /* Xbridge only */ 180 xbowreg_t _pad_000078; 181 xbowreg_t xb_w0_rst_fnc; /* 0x00007C */ 182 xbowreg_t _pad_000080; 183 xbowreg_t xb_l8_rst_fnc; /* 0x000084 */ 184 xbowreg_t _pad_000088; 185 xbowreg_t xb_l9_rst_fnc; /* 0x00008c */ 186 xbowreg_t _pad_000090; 187 xbowreg_t xb_la_rst_fnc; /* 0x000094 */ 188 xbowreg_t _pad_000098; 189 xbowreg_t xb_lb_rst_fnc; /* 0x00009c */ 190 xbowreg_t _pad_0000a0; 191 xbowreg_t xb_lc_rst_fnc; /* 0x0000a4 */ 192 xbowreg_t _pad_0000a8; 193 xbowreg_t xb_ld_rst_fnc; /* 0x0000ac */ 194 xbowreg_t _pad_0000b0; 195 xbowreg_t xb_le_rst_fnc; /* 0x0000b4 */ 196 xbowreg_t _pad_0000b8; 197 xbowreg_t xb_lf_rst_fnc; /* 0x0000bc */ 198 xbowreg_t _pad_0000c0; 199 xbowreg_t xb_lock; /* 0x0000c4 */ 200 xbowreg_t _pad_0000c8; 201 xbowreg_t xb_lock_clr; /* 0x0000cc */ 202 /* end of Xbridge only */ 203 xbowreg_t _pad_0000d0[12]; 204 #endif /* LITTLE_ENDIAN */ 205 206 /* Link Specific Registers, port 8..15 0x000100-0x000300 */ 207 xb_linkregs_t xb_link_raw[MAX_XBOW_PORTS]; 208 #define xb_link(p) xb_link_raw[(p) & (MAX_XBOW_PORTS - 1)] 209 210 } xbow_t; 211 212 /* Configuration structure which describes each xbow link */ 213 typedef struct xbow_cfg_s { 214 int xb_port; /* port number (0-15) */ 215 int xb_flags; /* port software flags */ 216 short xb_shift; /* shift for arb reg (mask is 0xff) */ 217 short xb_ul; /* upper or lower arb reg */ 218 int xb_pad; /* use this later (pad to ptr align) */ 219 xb_linkregs_t *xb_linkregs; /* pointer to link registers */ 220 widget_cfg_t *xb_widget; /* pointer to widget registers */ 221 char xb_name[MAX_XBOW_NAME]; /* port name */ 222 xbowreg_t xb_sh_arb_upper; /* shadow upper arb register */ 223 xbowreg_t xb_sh_arb_lower; /* shadow lower arb register */ 224 } xbow_cfg_t; 225 226 #define XB_FLAGS_EXISTS 0x1 /* device exists */ 227 #define XB_FLAGS_MASTER 0x2 228 #define XB_FLAGS_SLAVE 0x0 229 #define XB_FLAGS_GBR 0x4 230 #define XB_FLAGS_16BIT 0x8 231 #define XB_FLAGS_8BIT 0x0 232 233 /* get xbow config information for port p */ 234 #define XB_CONFIG(p) xbow_cfg[xb_ports[p]] 235 236 /* is widget port number valid? (based on version 7.0 of xbow spec) */ 237 #define XBOW_WIDGET_IS_VALID(wid) ((wid) >= XBOW_PORT_8 && (wid) <= XBOW_PORT_F) 238 239 /* whether to use upper or lower arbitration register, given source widget id */ 240 #define XBOW_ARB_IS_UPPER(wid) ((wid) >= XBOW_PORT_8 && (wid) <= XBOW_PORT_B) 241 #define XBOW_ARB_IS_LOWER(wid) ((wid) >= XBOW_PORT_C && (wid) <= XBOW_PORT_F) 242 243 /* offset of arbitration register, given source widget id */ 244 #define XBOW_ARB_OFF(wid) (XBOW_ARB_IS_UPPER(wid) ? 0x1c : 0x24) 245 246 #endif /* __ASSEMBLY__ */ 247 248 #define XBOW_WID_ID WIDGET_ID 249 #define XBOW_WID_STAT WIDGET_STATUS 250 #define XBOW_WID_ERR_UPPER WIDGET_ERR_UPPER_ADDR 251 #define XBOW_WID_ERR_LOWER WIDGET_ERR_LOWER_ADDR 252 #define XBOW_WID_CONTROL WIDGET_CONTROL 253 #define XBOW_WID_REQ_TO WIDGET_REQ_TIMEOUT 254 #define XBOW_WID_INT_UPPER WIDGET_INTDEST_UPPER_ADDR 255 #define XBOW_WID_INT_LOWER WIDGET_INTDEST_LOWER_ADDR 256 #define XBOW_WID_ERR_CMDWORD WIDGET_ERR_CMD_WORD 257 #define XBOW_WID_LLP WIDGET_LLP_CFG 258 #define XBOW_WID_STAT_CLR WIDGET_TFLUSH 259 #define XBOW_WID_ARB_RELOAD 0x5c 260 #define XBOW_WID_PERF_CTR_A 0x64 261 #define XBOW_WID_PERF_CTR_B 0x6c 262 #define XBOW_WID_NIC 0x74 263 264 /* Xbridge only */ 265 #define XBOW_W0_RST_FNC 0x00007C 266 #define XBOW_L8_RST_FNC 0x000084 267 #define XBOW_L9_RST_FNC 0x00008c 268 #define XBOW_LA_RST_FNC 0x000094 269 #define XBOW_LB_RST_FNC 0x00009c 270 #define XBOW_LC_RST_FNC 0x0000a4 271 #define XBOW_LD_RST_FNC 0x0000ac 272 #define XBOW_LE_RST_FNC 0x0000b4 273 #define XBOW_LF_RST_FNC 0x0000bc 274 #define XBOW_RESET_FENCE(x) ((x) > 7 && (x) < 16) ? \ 275 (XBOW_W0_RST_FNC + ((x) - 7) * 8) : \ 276 ((x) == 0) ? XBOW_W0_RST_FNC : 0 277 #define XBOW_LOCK 0x0000c4 278 #define XBOW_LOCK_CLR 0x0000cc 279 /* End of Xbridge only */ 280 281 /* used only in ide, but defined here within the reserved portion */ 282 /* of the widget0 address space (before 0xf4) */ 283 #define XBOW_WID_UNDEF 0xe4 284 285 /* pointer to link arbitration register, given xbow base, dst and src widget id */ 286 #define XBOW_PRIO_ARBREG_PTR(base, dst_wid, src_wid) \ 287 XBOW_REG_PTR(XBOW_PRIO_LINKREGS_PTR(base, dst_wid), XBOW_ARB_OFF(src_wid)) 288 289 /* pointer to link registers base, given xbow base and destination widget id */ 290 #define XBOW_PRIO_LINKREGS_PTR(base, dst_wid) (xb_linkregs_t*) \ 291 XBOW_REG_PTR(base, XB_LINK_REG_BASE(dst_wid)) 292 293 /* xbow link register set base, legal value for x is 0x8..0xf */ 294 #define XB_LINK_BASE 0x100 295 #define XB_LINK_OFFSET 0x40 296 #define XB_LINK_REG_BASE(x) (XB_LINK_BASE + ((x) & (MAX_XBOW_PORTS - 1)) * XB_LINK_OFFSET) 297 298 #define XB_LINK_IBUF_FLUSH(x) (XB_LINK_REG_BASE(x) + 0x4) 299 #define XB_LINK_CTRL(x) (XB_LINK_REG_BASE(x) + 0xc) 300 #define XB_LINK_STATUS(x) (XB_LINK_REG_BASE(x) + 0x14) 301 #define XB_LINK_ARB_UPPER(x) (XB_LINK_REG_BASE(x) + 0x1c) 302 #define XB_LINK_ARB_LOWER(x) (XB_LINK_REG_BASE(x) + 0x24) 303 #define XB_LINK_STATUS_CLR(x) (XB_LINK_REG_BASE(x) + 0x2c) 304 #define XB_LINK_RESET(x) (XB_LINK_REG_BASE(x) + 0x34) 305 #define XB_LINK_AUX_STATUS(x) (XB_LINK_REG_BASE(x) + 0x3c) 306 307 /* link_control(x) */ 308 #define XB_CTRL_LINKALIVE_IE 0x80000000 /* link comes alive */ 309 /* reserved: 0x40000000 */ 310 #define XB_CTRL_PERF_CTR_MODE_MSK 0x30000000 /* perf counter mode */ 311 #define XB_CTRL_IBUF_LEVEL_MSK 0x0e000000 /* input packet buffer level */ 312 #define XB_CTRL_8BIT_MODE 0x01000000 /* force link into 8 bit mode */ 313 #define XB_CTRL_BAD_LLP_PKT 0x00800000 /* force bad LLP packet */ 314 #define XB_CTRL_WIDGET_CR_MSK 0x007c0000 /* LLP widget credit mask */ 315 #define XB_CTRL_WIDGET_CR_SHFT 18 /* LLP widget credit shift */ 316 #define XB_CTRL_ILLEGAL_DST_IE 0x00020000 /* illegal destination */ 317 #define XB_CTRL_OALLOC_IBUF_IE 0x00010000 /* overallocated input buffer */ 318 /* reserved: 0x0000fe00 */ 319 #define XB_CTRL_BNDWDTH_ALLOC_IE 0x00000100 /* bandwidth alloc */ 320 #define XB_CTRL_RCV_CNT_OFLOW_IE 0x00000080 /* rcv retry overflow */ 321 #define XB_CTRL_XMT_CNT_OFLOW_IE 0x00000040 /* xmt retry overflow */ 322 #define XB_CTRL_XMT_MAX_RTRY_IE 0x00000020 /* max transmit retry */ 323 #define XB_CTRL_RCV_IE 0x00000010 /* receive */ 324 #define XB_CTRL_XMT_RTRY_IE 0x00000008 /* transmit retry */ 325 /* reserved: 0x00000004 */ 326 #define XB_CTRL_MAXREQ_TOUT_IE 0x00000002 /* maximum request timeout */ 327 #define XB_CTRL_SRC_TOUT_IE 0x00000001 /* source timeout */ 328 329 /* link_status(x) */ 330 #define XB_STAT_LINKALIVE XB_CTRL_LINKALIVE_IE 331 /* reserved: 0x7ff80000 */ 332 #define XB_STAT_MULTI_ERR 0x00040000 /* multi error */ 333 #define XB_STAT_ILLEGAL_DST_ERR XB_CTRL_ILLEGAL_DST_IE 334 #define XB_STAT_OALLOC_IBUF_ERR XB_CTRL_OALLOC_IBUF_IE 335 #define XB_STAT_BNDWDTH_ALLOC_ID_MSK 0x0000ff00 /* port bitmask */ 336 #define XB_STAT_RCV_CNT_OFLOW_ERR XB_CTRL_RCV_CNT_OFLOW_IE 337 #define XB_STAT_XMT_CNT_OFLOW_ERR XB_CTRL_XMT_CNT_OFLOW_IE 338 #define XB_STAT_XMT_MAX_RTRY_ERR XB_CTRL_XMT_MAX_RTRY_IE 339 #define XB_STAT_RCV_ERR XB_CTRL_RCV_IE 340 #define XB_STAT_XMT_RTRY_ERR XB_CTRL_XMT_RTRY_IE 341 /* reserved: 0x00000004 */ 342 #define XB_STAT_MAXREQ_TOUT_ERR XB_CTRL_MAXREQ_TOUT_IE 343 #define XB_STAT_SRC_TOUT_ERR XB_CTRL_SRC_TOUT_IE 344 345 /* link_aux_status(x) */ 346 #define XB_AUX_STAT_RCV_CNT 0xff000000 347 #define XB_AUX_STAT_XMT_CNT 0x00ff0000 348 #define XB_AUX_STAT_TOUT_DST 0x0000ff00 349 #define XB_AUX_LINKFAIL_RST_BAD 0x00000040 350 #define XB_AUX_STAT_PRESENT 0x00000020 351 #define XB_AUX_STAT_PORT_WIDTH 0x00000010 352 /* reserved: 0x0000000f */ 353 354 /* 355 * link_arb_upper/link_arb_lower(x), (reg) should be the link_arb_upper 356 * register if (x) is 0x8..0xb, link_arb_lower if (x) is 0xc..0xf 357 */ 358 #define XB_ARB_GBR_MSK 0x1f 359 #define XB_ARB_RR_MSK 0x7 360 #define XB_ARB_GBR_SHFT(x) (((x) & 0x3) * 8) 361 #define XB_ARB_RR_SHFT(x) (((x) & 0x3) * 8 + 5) 362 #define XB_ARB_GBR_CNT(reg,x) ((reg) >> XB_ARB_GBR_SHFT(x) & XB_ARB_GBR_MSK) 363 #define XB_ARB_RR_CNT(reg,x) ((reg) >> XB_ARB_RR_SHFT(x) & XB_ARB_RR_MSK) 364 365 /* XBOW_WID_STAT */ 366 #define XB_WID_STAT_LINK_INTR_SHFT (24) 367 #define XB_WID_STAT_LINK_INTR_MASK (0xFF << XB_WID_STAT_LINK_INTR_SHFT) 368 #define XB_WID_STAT_LINK_INTR(x) (0x1 << (((x)&7) + XB_WID_STAT_LINK_INTR_SHFT)) 369 #define XB_WID_STAT_WIDGET0_INTR 0x00800000 370 #define XB_WID_STAT_SRCID_MASK 0x000003c0 /* Xbridge only */ 371 #define XB_WID_STAT_REG_ACC_ERR 0x00000020 372 #define XB_WID_STAT_RECV_TOUT 0x00000010 /* Xbridge only */ 373 #define XB_WID_STAT_ARB_TOUT 0x00000008 /* Xbridge only */ 374 #define XB_WID_STAT_XTALK_ERR 0x00000004 375 #define XB_WID_STAT_DST_TOUT 0x00000002 /* Xbridge only */ 376 #define XB_WID_STAT_MULTI_ERR 0x00000001 377 378 #define XB_WID_STAT_SRCID_SHFT 6 379 380 /* XBOW_WID_CONTROL */ 381 #define XB_WID_CTRL_REG_ACC_IE XB_WID_STAT_REG_ACC_ERR 382 #define XB_WID_CTRL_RECV_TOUT XB_WID_STAT_RECV_TOUT 383 #define XB_WID_CTRL_ARB_TOUT XB_WID_STAT_ARB_TOUT 384 #define XB_WID_CTRL_XTALK_IE XB_WID_STAT_XTALK_ERR 385 386 /* XBOW_WID_INT_UPPER */ 387 /* defined in xwidget.h for WIDGET_INTDEST_UPPER_ADDR */ 388 389 /* XBOW WIDGET part number, in the ID register */ 390 #define XBOW_WIDGET_PART_NUM 0x0 /* crossbow */ 391 #define XXBOW_WIDGET_PART_NUM 0xd000 /* Xbridge */ 392 #define XBOW_WIDGET_MFGR_NUM 0x0 393 #define XXBOW_WIDGET_MFGR_NUM 0x0 394 #define PXBOW_WIDGET_PART_NUM 0xd100 /* PIC */ 395 396 #define XBOW_REV_1_0 0x1 /* xbow rev 1.0 is "1" */ 397 #define XBOW_REV_1_1 0x2 /* xbow rev 1.1 is "2" */ 398 #define XBOW_REV_1_2 0x3 /* xbow rev 1.2 is "3" */ 399 #define XBOW_REV_1_3 0x4 /* xbow rev 1.3 is "4" */ 400 #define XBOW_REV_2_0 0x5 /* xbow rev 2.0 is "5" */ 401 402 #define XXBOW_PART_REV_1_0 (XXBOW_WIDGET_PART_NUM << 4 | 0x1 ) 403 #define XXBOW_PART_REV_2_0 (XXBOW_WIDGET_PART_NUM << 4 | 0x2 ) 404 405 /* XBOW_WID_ARB_RELOAD */ 406 #define XBOW_WID_ARB_RELOAD_INT 0x3f /* GBR reload interval */ 407 408 #define IS_XBRIDGE_XBOW(wid) \ 409 (XWIDGET_PART_NUM(wid) == XXBOW_WIDGET_PART_NUM && \ 410 XWIDGET_MFG_NUM(wid) == XXBOW_WIDGET_MFGR_NUM) 411 412 #define IS_PIC_XBOW(wid) \ 413 (XWIDGET_PART_NUM(wid) == PXBOW_WIDGET_PART_NUM && \ 414 XWIDGET_MFG_NUM(wid) == XXBOW_WIDGET_MFGR_NUM) 415 416 #define XBOW_WAR_ENABLED(pv, widid) ((1 << XWIDGET_REV_NUM(widid)) & pv) 417 #define PV854827 (~0) /* PIC: fake widget 0xf presence bit. permanent */ 418 #define PV863579 (1 << 1) /* PIC: PIO to PIC register */ 419 420 421 #ifndef __ASSEMBLY__ 422 /* 423 * XBOW Widget 0 Register formats. 424 * Format for many of these registers are similar to the standard 425 * widget register format described as part of xtalk specification 426 * Standard widget register field format description is available in 427 * xwidget.h 428 * Following structures define the format for xbow widget 0 registers 429 */ 430 /* 431 * Xbow Widget 0 Command error word 432 */ 433 #ifdef LITTLE_ENDIAN 434 435 typedef union xbw0_cmdword_u { 436 xbowreg_t cmdword; 437 struct { 438 uint32_t rsvd:8, /* Reserved */ 439 barr:1, /* Barrier operation */ 440 error:1, /* Error Occured */ 441 vbpm:1, /* Virtual Backplane message */ 442 gbr:1, /* GBR enable ? */ 443 ds:2, /* Data size */ 444 ct:1, /* Is it a coherent transaction */ 445 tnum:5, /* Transaction Number */ 446 pactyp:4, /* Packet type: */ 447 srcid:4, /* Source ID number */ 448 destid:4; /* Desination ID number */ 449 450 } xbw0_cmdfield; 451 } xbw0_cmdword_t; 452 453 #else 454 455 typedef union xbw0_cmdword_u { 456 xbowreg_t cmdword; 457 struct { 458 uint32_t destid:4, /* Desination ID number */ 459 srcid:4, /* Source ID number */ 460 pactyp:4, /* Packet type: */ 461 tnum:5, /* Transaction Number */ 462 ct:1, /* Is it a coherent transaction */ 463 ds:2, /* Data size */ 464 gbr:1, /* GBR enable ? */ 465 vbpm:1, /* Virtual Backplane message */ 466 error:1, /* Error Occured */ 467 barr:1, /* Barrier operation */ 468 rsvd:8; /* Reserved */ 469 } xbw0_cmdfield; 470 } xbw0_cmdword_t; 471 472 #endif 473 474 #define xbcmd_destid xbw0_cmdfield.destid 475 #define xbcmd_srcid xbw0_cmdfield.srcid 476 #define xbcmd_pactyp xbw0_cmdfield.pactyp 477 #define xbcmd_tnum xbw0_cmdfield.tnum 478 #define xbcmd_ct xbw0_cmdfield.ct 479 #define xbcmd_ds xbw0_cmdfield.ds 480 #define xbcmd_gbr xbw0_cmdfield.gbr 481 #define xbcmd_vbpm xbw0_cmdfield.vbpm 482 #define xbcmd_error xbw0_cmdfield.error 483 #define xbcmd_barr xbw0_cmdfield.barr 484 485 /* 486 * Values for field PACTYP in xbow error command word 487 */ 488 #define XBCMDTYP_READREQ 0 /* Read Request packet */ 489 #define XBCMDTYP_READRESP 1 /* Read Response packet */ 490 #define XBCMDTYP_WRREQ_RESP 2 /* Write Request with response */ 491 #define XBCMDTYP_WRRESP 3 /* Write Response */ 492 #define XBCMDTYP_WRREQ_NORESP 4 /* Write request with No Response */ 493 #define XBCMDTYP_FETCHOP 6 /* Fetch & Op packet */ 494 #define XBCMDTYP_STOREOP 8 /* Store & Op packet */ 495 #define XBCMDTYP_SPLPKT_REQ 0xE /* Special packet request */ 496 #define XBCMDTYP_SPLPKT_RESP 0xF /* Special packet response */ 497 498 /* 499 * Values for field ds (datasize) in xbow error command word 500 */ 501 #define XBCMDSZ_DOUBLEWORD 0 502 #define XBCMDSZ_QUARTRCACHE 1 503 #define XBCMDSZ_FULLCACHE 2 504 505 /* 506 * Xbow widget 0 Status register format. 507 */ 508 #ifdef LITTLE_ENDIAN 509 510 typedef union xbw0_status_u { 511 xbowreg_t statusword; 512 struct { 513 uint32_t mult_err:1, /* Multiple error occurred */ 514 connect_tout:1, /* Connection timeout */ 515 xtalk_err:1, /* Xtalk pkt with error bit */ 516 /* End of Xbridge only */ 517 w0_arb_tout, /* arbiter timeout err */ 518 w0_recv_tout, /* receive timeout err */ 519 /* Xbridge only */ 520 regacc_err:1, /* Reg Access error */ 521 src_id:4, /* source id. Xbridge only */ 522 resvd1:13, 523 wid0intr:1; /* Widget 0 err intr */ 524 } xbw0_stfield; 525 } xbw0_status_t; 526 527 #else 528 529 typedef union xbw0_status_u { 530 xbowreg_t statusword; 531 struct { 532 uint32_t linkXintr:8, /* link(x) error intr */ 533 wid0intr:1, /* Widget 0 err intr */ 534 resvd1:13, 535 src_id:4, /* source id. Xbridge only */ 536 regacc_err:1, /* Reg Access error */ 537 /* Xbridge only */ 538 w0_recv_tout, /* receive timeout err */ 539 w0_arb_tout, /* arbiter timeout err */ 540 /* End of Xbridge only */ 541 xtalk_err:1, /* Xtalk pkt with error bit */ 542 connect_tout:1, /* Connection timeout */ 543 mult_err:1; /* Multiple error occurred */ 544 } xbw0_stfield; 545 } xbw0_status_t; 546 547 #endif 548 549 #define xbst_linkXintr xbw0_stfield.linkXintr 550 #define xbst_w0intr xbw0_stfield.wid0intr 551 #define xbst_regacc_err xbw0_stfield.regacc_err 552 #define xbst_xtalk_err xbw0_stfield.xtalk_err 553 #define xbst_connect_tout xbw0_stfield.connect_tout 554 #define xbst_mult_err xbw0_stfield.mult_err 555 #define xbst_src_id xbw0_stfield.src_id /* Xbridge only */ 556 #define xbst_w0_recv_tout xbw0_stfield.w0_recv_tout /* Xbridge only */ 557 #define xbst_w0_arb_tout xbw0_stfield.w0_arb_tout /* Xbridge only */ 558 559 /* 560 * Xbow widget 0 Control register format 561 */ 562 #ifdef LITTLE_ENDIAN 563 564 typedef union xbw0_ctrl_u { 565 xbowreg_t ctrlword; 566 struct { 567 uint32_t 568 resvd3:1, 569 conntout_intr:1, 570 xtalkerr_intr:1, 571 w0_arg_tout_intr:1, /* Xbridge only */ 572 w0_recv_tout_intr:1, /* Xbridge only */ 573 accerr_intr:1, 574 enable_w0_tout_cntr:1, /* Xbridge only */ 575 enable_watchdog:1, /* Xbridge only */ 576 resvd1:24; 577 } xbw0_ctrlfield; 578 } xbw0_ctrl_t; 579 580 #else 581 582 typedef union xbw0_ctrl_u { 583 xbowreg_t ctrlword; 584 struct { 585 uint32_t 586 resvd1:24, 587 enable_watchdog:1, /* Xbridge only */ 588 enable_w0_tout_cntr:1, /* Xbridge only */ 589 accerr_intr:1, 590 w0_recv_tout_intr:1, /* Xbridge only */ 591 w0_arg_tout_intr:1, /* Xbridge only */ 592 xtalkerr_intr:1, 593 conntout_intr:1, 594 resvd3:1; 595 } xbw0_ctrlfield; 596 } xbw0_ctrl_t; 597 598 #endif 599 600 #ifdef LITTLE_ENDIAN 601 602 typedef union xbow_linkctrl_u { 603 xbowreg_t xbl_ctrlword; 604 struct { 605 uint32_t srcto_intr:1, 606 maxto_intr:1, 607 rsvd3:1, 608 trx_retry_intr:1, 609 rcv_err_intr:1, 610 trx_max_retry_intr:1, 611 trxov_intr:1, 612 rcvov_intr:1, 613 bwalloc_intr:1, 614 rsvd2:7, 615 obuf_intr:1, 616 idest_intr:1, 617 llp_credit:5, 618 force_badllp:1, 619 send_bm8:1, 620 inbuf_level:3, 621 perf_mode:2, 622 rsvd1:1, 623 alive_intr:1; 624 625 } xb_linkcontrol; 626 } xbow_linkctrl_t; 627 628 #else 629 630 typedef union xbow_linkctrl_u { 631 xbowreg_t xbl_ctrlword; 632 struct { 633 uint32_t alive_intr:1, 634 rsvd1:1, 635 perf_mode:2, 636 inbuf_level:3, 637 send_bm8:1, 638 force_badllp:1, 639 llp_credit:5, 640 idest_intr:1, 641 obuf_intr:1, 642 rsvd2:7, 643 bwalloc_intr:1, 644 rcvov_intr:1, 645 trxov_intr:1, 646 trx_max_retry_intr:1, 647 rcv_err_intr:1, 648 trx_retry_intr:1, 649 rsvd3:1, 650 maxto_intr:1, 651 srcto_intr:1; 652 } xb_linkcontrol; 653 } xbow_linkctrl_t; 654 655 #endif 656 657 658 #define xbctl_accerr_intr (xbw0_ctrlfield.accerr_intr) 659 #define xbctl_xtalkerr_intr (xbw0_ctrlfield.xtalkerr_intr) 660 #define xbctl_cnntout_intr (xbw0_ctrlfield.conntout_intr) 661 662 #define XBW0_CTRL_ACCERR_INTR (1 << 5) 663 #define XBW0_CTRL_XTERR_INTR (1 << 2) 664 #define XBW0_CTRL_CONNTOUT_INTR (1 << 1) 665 666 /* 667 * Xbow Link specific Registers structure definitions. 668 */ 669 670 #ifdef LITTLE_ENDIAN 671 672 typedef union xbow_linkX_status_u { 673 xbowreg_t linkstatus; 674 struct { 675 uint32_t pkt_toutsrc:1, 676 pkt_toutconn:1, /* max_req_tout in Xbridge */ 677 pkt_toutdest:1, /* reserved in Xbridge */ 678 llp_xmitretry:1, 679 llp_rcverror:1, 680 llp_maxtxretry:1, 681 llp_txovflow:1, 682 llp_rxovflow:1, 683 bw_errport:8, /* BW allocation error port */ 684 ioe:1, /* Input overallocation error */ 685 illdest:1, 686 merror:1, 687 resvd1:12, 688 alive:1; 689 } xb_linkstatus; 690 } xbwX_stat_t; 691 692 #else 693 694 typedef union xbow_linkX_status_u { 695 xbowreg_t linkstatus; 696 struct { 697 uint32_t alive:1, 698 resvd1:12, 699 merror:1, 700 illdest:1, 701 ioe:1, /* Input overallocation error */ 702 bw_errport:8, /* BW allocation error port */ 703 llp_rxovflow:1, 704 llp_txovflow:1, 705 llp_maxtxretry:1, 706 llp_rcverror:1, 707 llp_xmitretry:1, 708 pkt_toutdest:1, /* reserved in Xbridge */ 709 pkt_toutconn:1, /* max_req_tout in Xbridge */ 710 pkt_toutsrc:1; 711 } xb_linkstatus; 712 } xbwX_stat_t; 713 714 #endif 715 716 #define link_alive xb_linkstatus.alive 717 #define link_multierror xb_linkstatus.merror 718 #define link_illegal_dest xb_linkstatus.illdest 719 #define link_ioe xb_linkstatus.ioe 720 #define link_max_req_tout xb_linkstatus.pkt_toutconn /* Xbridge */ 721 #define link_pkt_toutconn xb_linkstatus.pkt_toutconn /* Xbow */ 722 #define link_pkt_toutdest xb_linkstatus.pkt_toutdest 723 #define link_pkt_toutsrc xb_linkstatus.pkt_toutsrc 724 725 #ifdef LITTLE_ENDIAN 726 727 typedef union xbow_aux_linkX_status_u { 728 xbowreg_t aux_linkstatus; 729 struct { 730 uint32_t rsvd2:4, 731 bit_mode_8:1, 732 wid_present:1, 733 fail_mode:1, 734 rsvd1:1, 735 to_src_loc:8, 736 tx_retry_cnt:8, 737 rx_err_cnt:8; 738 } xb_aux_linkstatus; 739 } xbow_aux_link_status_t; 740 741 #else 742 743 typedef union xbow_aux_linkX_status_u { 744 xbowreg_t aux_linkstatus; 745 struct { 746 uint32_t rx_err_cnt:8, 747 tx_retry_cnt:8, 748 to_src_loc:8, 749 rsvd1:1, 750 fail_mode:1, 751 wid_present:1, 752 bit_mode_8:1, 753 rsvd2:4; 754 } xb_aux_linkstatus; 755 } xbow_aux_link_status_t; 756 757 #endif 758 759 760 #ifdef LITTLE_ENDIAN 761 762 typedef union xbow_perf_count_u { 763 xbowreg_t xb_counter_val; 764 struct { 765 uint32_t count:20, 766 link_select:3, 767 rsvd:9; 768 } xb_perf; 769 } xbow_perfcount_t; 770 771 #else 772 773 typedef union xbow_perf_count_u { 774 xbowreg_t xb_counter_val; 775 struct { 776 uint32_t rsvd:9, 777 link_select:3, 778 count:20; 779 } xb_perf; 780 } xbow_perfcount_t; 781 782 #endif 783 784 #define XBOW_COUNTER_MASK 0xFFFFF 785 786 extern int xbow_widget_present(xbow_t * xbow, int port); 787 788 extern xwidget_intr_preset_f xbow_intr_preset; 789 extern xswitch_reset_link_f xbow_reset_link; 790 void xbow_mlreset(xbow_t *); 791 792 /* ======================================================================== 793 */ 794 795 #ifdef MACROFIELD_LINE 796 /* 797 * This table forms a relation between the byte offset macros normally 798 * used for ASM coding and the calculated byte offsets of the fields 799 * in the C structure. 800 * 801 * See xbow_check.c xbow_html.c for further details. 802 */ 803 #ifndef MACROFIELD_LINE_BITFIELD 804 #define MACROFIELD_LINE_BITFIELD(m) /* ignored */ 805 #endif 806 807 struct macrofield_s xbow_macrofield[] = 808 { 809 810 MACROFIELD_LINE(XBOW_WID_ID, xb_wid_id) 811 MACROFIELD_LINE(XBOW_WID_STAT, xb_wid_stat) 812 MACROFIELD_LINE_BITFIELD(XB_WID_STAT_LINK_INTR(0xF)) 813 MACROFIELD_LINE_BITFIELD(XB_WID_STAT_LINK_INTR(0xE)) 814 MACROFIELD_LINE_BITFIELD(XB_WID_STAT_LINK_INTR(0xD)) 815 MACROFIELD_LINE_BITFIELD(XB_WID_STAT_LINK_INTR(0xC)) 816 MACROFIELD_LINE_BITFIELD(XB_WID_STAT_LINK_INTR(0xB)) 817 MACROFIELD_LINE_BITFIELD(XB_WID_STAT_LINK_INTR(0xA)) 818 MACROFIELD_LINE_BITFIELD(XB_WID_STAT_LINK_INTR(0x9)) 819 MACROFIELD_LINE_BITFIELD(XB_WID_STAT_LINK_INTR(0x8)) 820 MACROFIELD_LINE_BITFIELD(XB_WID_STAT_WIDGET0_INTR) 821 MACROFIELD_LINE_BITFIELD(XB_WID_STAT_REG_ACC_ERR) 822 MACROFIELD_LINE_BITFIELD(XB_WID_STAT_XTALK_ERR) 823 MACROFIELD_LINE_BITFIELD(XB_WID_STAT_MULTI_ERR) 824 MACROFIELD_LINE(XBOW_WID_ERR_UPPER, xb_wid_err_upper) 825 MACROFIELD_LINE(XBOW_WID_ERR_LOWER, xb_wid_err_lower) 826 MACROFIELD_LINE(XBOW_WID_CONTROL, xb_wid_control) 827 MACROFIELD_LINE_BITFIELD(XB_WID_CTRL_REG_ACC_IE) 828 MACROFIELD_LINE_BITFIELD(XB_WID_CTRL_XTALK_IE) 829 MACROFIELD_LINE(XBOW_WID_REQ_TO, xb_wid_req_timeout) 830 MACROFIELD_LINE(XBOW_WID_INT_UPPER, xb_wid_int_upper) 831 MACROFIELD_LINE(XBOW_WID_INT_LOWER, xb_wid_int_lower) 832 MACROFIELD_LINE(XBOW_WID_ERR_CMDWORD, xb_wid_err_cmdword) 833 MACROFIELD_LINE(XBOW_WID_LLP, xb_wid_llp) 834 MACROFIELD_LINE(XBOW_WID_STAT_CLR, xb_wid_stat_clr) 835 MACROFIELD_LINE(XBOW_WID_ARB_RELOAD, xb_wid_arb_reload) 836 MACROFIELD_LINE(XBOW_WID_PERF_CTR_A, xb_perf_ctr_a) 837 MACROFIELD_LINE(XBOW_WID_PERF_CTR_B, xb_perf_ctr_b) 838 MACROFIELD_LINE(XBOW_WID_NIC, xb_nic) 839 MACROFIELD_LINE(XB_LINK_REG_BASE(8), xb_link(8)) 840 MACROFIELD_LINE(XB_LINK_IBUF_FLUSH(8), xb_link(8).link_ibf) 841 MACROFIELD_LINE(XB_LINK_CTRL(8), xb_link(8).link_control) 842 MACROFIELD_LINE_BITFIELD(XB_CTRL_LINKALIVE_IE) 843 MACROFIELD_LINE_BITFIELD(XB_CTRL_PERF_CTR_MODE_MSK) 844 MACROFIELD_LINE_BITFIELD(XB_CTRL_IBUF_LEVEL_MSK) 845 MACROFIELD_LINE_BITFIELD(XB_CTRL_8BIT_MODE) 846 MACROFIELD_LINE_BITFIELD(XB_CTRL_BAD_LLP_PKT) 847 MACROFIELD_LINE_BITFIELD(XB_CTRL_WIDGET_CR_MSK) 848 MACROFIELD_LINE_BITFIELD(XB_CTRL_ILLEGAL_DST_IE) 849 MACROFIELD_LINE_BITFIELD(XB_CTRL_OALLOC_IBUF_IE) 850 MACROFIELD_LINE_BITFIELD(XB_CTRL_BNDWDTH_ALLOC_IE) 851 MACROFIELD_LINE_BITFIELD(XB_CTRL_RCV_CNT_OFLOW_IE) 852 MACROFIELD_LINE_BITFIELD(XB_CTRL_XMT_CNT_OFLOW_IE) 853 MACROFIELD_LINE_BITFIELD(XB_CTRL_XMT_MAX_RTRY_IE) 854 MACROFIELD_LINE_BITFIELD(XB_CTRL_RCV_IE) 855 MACROFIELD_LINE_BITFIELD(XB_CTRL_XMT_RTRY_IE) 856 MACROFIELD_LINE_BITFIELD(XB_CTRL_MAXREQ_TOUT_IE) 857 MACROFIELD_LINE_BITFIELD(XB_CTRL_SRC_TOUT_IE) 858 MACROFIELD_LINE(XB_LINK_STATUS(8), xb_link(8).link_status) 859 MACROFIELD_LINE_BITFIELD(XB_STAT_LINKALIVE) 860 MACROFIELD_LINE_BITFIELD(XB_STAT_MULTI_ERR) 861 MACROFIELD_LINE_BITFIELD(XB_STAT_ILLEGAL_DST_ERR) 862 MACROFIELD_LINE_BITFIELD(XB_STAT_OALLOC_IBUF_ERR) 863 MACROFIELD_LINE_BITFIELD(XB_STAT_BNDWDTH_ALLOC_ID_MSK) 864 MACROFIELD_LINE_BITFIELD(XB_STAT_RCV_CNT_OFLOW_ERR) 865 MACROFIELD_LINE_BITFIELD(XB_STAT_XMT_CNT_OFLOW_ERR) 866 MACROFIELD_LINE_BITFIELD(XB_STAT_XMT_MAX_RTRY_ERR) 867 MACROFIELD_LINE_BITFIELD(XB_STAT_RCV_ERR) 868 MACROFIELD_LINE_BITFIELD(XB_STAT_XMT_RTRY_ERR) 869 MACROFIELD_LINE_BITFIELD(XB_STAT_MAXREQ_TOUT_ERR) 870 MACROFIELD_LINE_BITFIELD(XB_STAT_SRC_TOUT_ERR) 871 MACROFIELD_LINE(XB_LINK_ARB_UPPER(8), xb_link(8).link_arb_upper) 872 MACROFIELD_LINE_BITFIELD(XB_ARB_RR_MSK << XB_ARB_RR_SHFT(0xb)) 873 MACROFIELD_LINE_BITFIELD(XB_ARB_GBR_MSK << XB_ARB_GBR_SHFT(0xb)) 874 MACROFIELD_LINE_BITFIELD(XB_ARB_RR_MSK << XB_ARB_RR_SHFT(0xa)) 875 MACROFIELD_LINE_BITFIELD(XB_ARB_GBR_MSK << XB_ARB_GBR_SHFT(0xa)) 876 MACROFIELD_LINE_BITFIELD(XB_ARB_RR_MSK << XB_ARB_RR_SHFT(0x9)) 877 MACROFIELD_LINE_BITFIELD(XB_ARB_GBR_MSK << XB_ARB_GBR_SHFT(0x9)) 878 MACROFIELD_LINE_BITFIELD(XB_ARB_RR_MSK << XB_ARB_RR_SHFT(0x8)) 879 MACROFIELD_LINE_BITFIELD(XB_ARB_GBR_MSK << XB_ARB_GBR_SHFT(0x8)) 880 MACROFIELD_LINE(XB_LINK_ARB_LOWER(8), xb_link(8).link_arb_lower) 881 MACROFIELD_LINE_BITFIELD(XB_ARB_RR_MSK << XB_ARB_RR_SHFT(0xf)) 882 MACROFIELD_LINE_BITFIELD(XB_ARB_GBR_MSK << XB_ARB_GBR_SHFT(0xf)) 883 MACROFIELD_LINE_BITFIELD(XB_ARB_RR_MSK << XB_ARB_RR_SHFT(0xe)) 884 MACROFIELD_LINE_BITFIELD(XB_ARB_GBR_MSK << XB_ARB_GBR_SHFT(0xe)) 885 MACROFIELD_LINE_BITFIELD(XB_ARB_RR_MSK << XB_ARB_RR_SHFT(0xd)) 886 MACROFIELD_LINE_BITFIELD(XB_ARB_GBR_MSK << XB_ARB_GBR_SHFT(0xd)) 887 MACROFIELD_LINE_BITFIELD(XB_ARB_RR_MSK << XB_ARB_RR_SHFT(0xc)) 888 MACROFIELD_LINE_BITFIELD(XB_ARB_GBR_MSK << XB_ARB_GBR_SHFT(0xc)) 889 MACROFIELD_LINE(XB_LINK_STATUS_CLR(8), xb_link(8).link_status_clr) 890 MACROFIELD_LINE(XB_LINK_RESET(8), xb_link(8).link_reset) 891 MACROFIELD_LINE(XB_LINK_AUX_STATUS(8), xb_link(8).link_aux_status) 892 MACROFIELD_LINE_BITFIELD(XB_AUX_STAT_RCV_CNT) 893 MACROFIELD_LINE_BITFIELD(XB_AUX_STAT_XMT_CNT) 894 MACROFIELD_LINE_BITFIELD(XB_AUX_LINKFAIL_RST_BAD) 895 MACROFIELD_LINE_BITFIELD(XB_AUX_STAT_PRESENT) 896 MACROFIELD_LINE_BITFIELD(XB_AUX_STAT_PORT_WIDTH) 897 MACROFIELD_LINE_BITFIELD(XB_AUX_STAT_TOUT_DST) 898 MACROFIELD_LINE(XB_LINK_REG_BASE(0x8), xb_link(0x8)) 899 MACROFIELD_LINE(XB_LINK_REG_BASE(0x9), xb_link(0x9)) 900 MACROFIELD_LINE(XB_LINK_REG_BASE(0xA), xb_link(0xA)) 901 MACROFIELD_LINE(XB_LINK_REG_BASE(0xB), xb_link(0xB)) 902 MACROFIELD_LINE(XB_LINK_REG_BASE(0xC), xb_link(0xC)) 903 MACROFIELD_LINE(XB_LINK_REG_BASE(0xD), xb_link(0xD)) 904 MACROFIELD_LINE(XB_LINK_REG_BASE(0xE), xb_link(0xE)) 905 MACROFIELD_LINE(XB_LINK_REG_BASE(0xF), xb_link(0xF)) 906 }; /* xbow_macrofield[] */ 907 908 #endif /* MACROFIELD_LINE */ 909 910 #endif /* __ASSEMBLY__ */ 911 #endif /* _ASM_SN_SN_XTALK_XBOW_H */ 912