1 /* $Id$ 2 * 3 * This file is subject to the terms and conditions of the GNU General Public 4 * License. See the file "COPYING" in the main directory of this archive 5 * for more details. 6 * 7 * Copyright (C) 1992 - 1997, 2000-2003 Silicon Graphics, Inc. All rights reserved. 8 */ 9 #ifndef _ASM_SN_PCI_PIC_H 10 #define _ASM_SN_PCI_PIC_H 11 12 13 /* 14 * The PIC ASIC is a follow-on to the Bridge and Xbridge ASICs. 15 * It shares many of the same registers as those chips and therefore 16 * the primary structure for the PIC will be bridge_s as defined 17 * in irix/kern/sys/PCI/bridge.h. This file is intended as a complement 18 * to bridge.h, which includes this file. 19 */ 20 21 /* 22 * PIC AS DEVICE ZERO 23 * ------------------ 24 * 25 * PIC handles PCI/X busses. PCI/X requires that the 'bridge' (i.e. PIC) 26 * be designated as 'device 0'. That is a departure from earlier SGI 27 * PCI bridges. Because of that we use config space 1 to access the 28 * config space of the first actual PCI device on the bus. 29 * Here's what the PIC manual says: 30 * 31 * The current PCI-X bus specification now defines that the parent 32 * hosts bus bridge (PIC for example) must be device 0 on bus 0. PIC 33 * reduced the total number of devices from 8 to 4 and removed the 34 * device registers and windows, now only supporting devices 0,1,2, and 35 * 3. PIC did leave all 8 configuration space windows. The reason was 36 * there was nothing to gain by removing them. Here in lies the problem. 37 * The device numbering we do using 0 through 3 is unrelated to the device 38 * numbering which PCI-X requires in configuration space. In the past we 39 * correlated Configs pace and our device space 0 <-> 0, 1 <-> 1, etc. 40 * PCI-X requires we start a 1, not 0 and currently the PX brick 41 * does associate our: 42 * 43 * device 0 with configuration space window 1, 44 * device 1 with configuration space window 2, 45 * device 2 with configuration space window 3, 46 * device 3 with configuration space window 4. 47 * 48 * The net effect is that all config space access are off-by-one with 49 * relation to other per-slot accesses on the PIC. 50 * Here is a table that shows some of that: 51 * 52 * Internal Slot# 53 * | 54 * | 0 1 2 3 55 * ----------|--------------------------------------- 56 * config | 0x21000 0x22000 0x23000 0x24000 57 * | 58 * even rrb | 0[0] n/a 1[0] n/a [] == implied even/odd 59 * | 60 * odd rrb | n/a 0[1] n/a 1[1] 61 * | 62 * int dev | 00 01 10 11 63 * | 64 * ext slot# | 1 2 3 4 65 * ----------|--------------------------------------- 66 */ 67 68 69 #ifndef __ASSEMBLY__ 70 71 #ifdef __cplusplus 72 extern "C" { 73 #endif 74 75 76 /********************************************************************* 77 * bus provider function table 78 * 79 * Normally, this table is only handed off explicitly 80 * during provider initialization, and the PCI generic 81 * layer will stash a pointer to it in the vertex; however, 82 * exporting it explicitly enables a performance hack in 83 * the generic PCI provider where if we know at compile 84 * time that the only possible PCI provider is a 85 * pcibr, we can go directly to this ops table. 86 */ 87 88 #ifdef __KERNEL__ 89 #include <linux/config.h> 90 #include <asm/sn/pci/pciio.h> 91 extern pciio_provider_t pci_pic_provider; 92 #else 93 #include <linux/config.h> 94 #endif 95 96 97 /********************************************************************* 98 * misc defines 99 * 100 */ 101 #define PIC_WIDGET_PART_NUM_BUS0 0xd102 102 #define PIC_WIDGET_PART_NUM_BUS1 0xd112 103 #define PIC_WIDGET_MFGR_NUM 0x24 104 #define PIC_WIDGET_REV_A 0x1 105 106 #define IS_PIC_PART_REV_A(rev) \ 107 ((rev == (PIC_WIDGET_PART_NUM_BUS0 << 4 | PIC_WIDGET_REV_A)) || \ 108 (rev == (PIC_WIDGET_PART_NUM_BUS1 << 4 | PIC_WIDGET_REV_A))) 109 110 /********************************************************************* 111 * register offset defines 112 * 113 */ 114 /* Identification Register -- read-only */ 115 #define PIC_IDENTIFICATION 0x00000000 116 117 /* Status Register -- read-only */ 118 #define PIC_STATUS 0x00000008 119 120 /* Upper Address Holding Register Bus Side Errors -- read-only */ 121 #define PIC_UPPER_ADDR_REG_BUS_SIDE_ERRS 0x00000010 122 123 /* Lower Address Holding Register Bus Side Errors -- read-only */ 124 #define PIC_LOWER_ADDR_REG_BUS_SIDE_ERRS 0x00000018 125 126 /* Control Register -- read/write */ 127 #define PIC_CONTROL 0x00000020 128 129 /* PCI Request Time-out Value Register -- read/write */ 130 #define PIC_PCI_REQ_TIME_OUT_VALUE 0x00000028 131 132 /* Interrupt Destination Upper Address Register -- read/write */ 133 #define PIC_INTR_DEST_UPPER_ADDR 0x00000030 134 135 /* Interrupt Destination Lower Address Register -- read/write */ 136 #define PIC_INTR_DEST_LOWER_ADDR 0x00000038 137 138 /* Command Word Holding Register Bus Side -- read-only */ 139 #define PIC_CMD_WORD_REG_BUS_SIDE 0x00000040 140 141 /* LLP Configuration Register (Bus 0 Only) -- read/write */ 142 #define PIC_LLP_CFG_REG_(BUS_0_ONLY) 0x00000048 143 144 /* PCI Target Flush Register -- read-only */ 145 #define PIC_PCI_TARGET_FLUSH 0x00000050 146 147 /* Command Word Holding Register Link Side -- read-only */ 148 #define PIC_CMD_WORD_REG_LINK_SIDE 0x00000058 149 150 /* Response Buffer Error Upper Address Holding -- read-only */ 151 #define PIC_RESP_BUF_ERR_UPPER_ADDR_ 0x00000060 152 153 /* Response Buffer Error Lower Address Holding -- read-only */ 154 #define PIC_RESP_BUF_ERR_LOWER_ADDR_ 0x00000068 155 156 /* Test Pin Control Register -- read/write */ 157 #define PIC_TEST_PIN_CONTROL 0x00000070 158 159 /* Address Holding Register Link Side Errors -- read-only */ 160 #define PIC_ADDR_REG_LINK_SIDE_ERRS 0x00000078 161 162 /* Direct Map Register -- read/write */ 163 #define PIC_DIRECT_MAP 0x00000080 164 165 /* PCI Map Fault Address Register -- read-only */ 166 #define PIC_PCI_MAP_FAULT_ADDR 0x00000090 167 168 /* Arbitration Priority Register -- read/write */ 169 #define PIC_ARBITRATION_PRIORITY 0x000000A0 170 171 /* Internal Ram Parity Error Register -- read-only */ 172 #define PIC_INTERNAL_RAM_PARITY_ERR 0x000000B0 173 174 /* PCI Time-out Register -- read/write */ 175 #define PIC_PCI_TIME_OUT 0x000000C0 176 177 /* PCI Type 1 Configuration Register -- read/write */ 178 #define PIC_PCI_TYPE_1_CFG 0x000000C8 179 180 /* PCI Bus Error Upper Address Holding Register -- read-only */ 181 #define PIC_PCI_BUS_ERR_UPPER_ADDR_ 0x000000D0 182 183 /* PCI Bus Error Lower Address Holding Register -- read-only */ 184 #define PIC_PCI_BUS_ERR_LOWER_ADDR_ 0x000000D8 185 186 /* PCIX Error Address Register -- read-only */ 187 #define PIC_PCIX_ERR_ADDR 0x000000E0 188 189 /* PCIX Error Attribute Register -- read-only */ 190 #define PIC_PCIX_ERR_ATTRIBUTE 0x000000E8 191 192 /* PCIX Error Data Register -- read-only */ 193 #define PIC_PCIX_ERR_DATA 0x000000F0 194 195 /* PCIX Read Request Timeout Error Register -- read-only */ 196 #define PIC_PCIX_READ_REQ_TIMEOUT_ERR 0x000000F8 197 198 /* Interrupt Status Register -- read-only */ 199 #define PIC_INTR_STATUS 0x00000100 200 201 /* Interrupt Enable Register -- read/write */ 202 #define PIC_INTR_ENABLE 0x00000108 203 204 /* Reset Interrupt Status Register -- write-only */ 205 #define PIC_RESET_INTR_STATUS 0x00000110 206 207 /* Interrupt Mode Register -- read/write */ 208 #define PIC_INTR_MODE 0x00000118 209 210 /* Interrupt Device Register -- read/write */ 211 #define PIC_INTR_DEVICE 0x00000120 212 213 /* Host Error Field Register -- read/write */ 214 #define PIC_HOST_ERR_FIELD 0x00000128 215 216 /* Interrupt Pin 0 Host Address Register -- read/write */ 217 #define PIC_INTR_PIN_0_HOST_ADDR 0x00000130 218 219 /* Interrupt Pin 1 Host Address Register -- read/write */ 220 #define PIC_INTR_PIN_1_HOST_ADDR 0x00000138 221 222 /* Interrupt Pin 2 Host Address Register -- read/write */ 223 #define PIC_INTR_PIN_2_HOST_ADDR 0x00000140 224 225 /* Interrupt Pin 3 Host Address Register -- read/write */ 226 #define PIC_INTR_PIN_3_HOST_ADDR 0x00000148 227 228 /* Interrupt Pin 4 Host Address Register -- read/write */ 229 #define PIC_INTR_PIN_4_HOST_ADDR 0x00000150 230 231 /* Interrupt Pin 5 Host Address Register -- read/write */ 232 #define PIC_INTR_PIN_5_HOST_ADDR 0x00000158 233 234 /* Interrupt Pin 6 Host Address Register -- read/write */ 235 #define PIC_INTR_PIN_6_HOST_ADDR 0x00000160 236 237 /* Interrupt Pin 7 Host Address Register -- read/write */ 238 #define PIC_INTR_PIN_7_HOST_ADDR 0x00000168 239 240 /* Error Interrupt View Register -- read-only */ 241 #define PIC_ERR_INTR_VIEW 0x00000170 242 243 /* Multiple Interrupt Register -- read-only */ 244 #define PIC_MULTIPLE_INTR 0x00000178 245 246 /* Force Always Interrupt 0 Register -- write-only */ 247 #define PIC_FORCE_ALWAYS_INTR_0 0x00000180 248 249 /* Force Always Interrupt 1 Register -- write-only */ 250 #define PIC_FORCE_ALWAYS_INTR_1 0x00000188 251 252 /* Force Always Interrupt 2 Register -- write-only */ 253 #define PIC_FORCE_ALWAYS_INTR_2 0x00000190 254 255 /* Force Always Interrupt 3 Register -- write-only */ 256 #define PIC_FORCE_ALWAYS_INTR_3 0x00000198 257 258 /* Force Always Interrupt 4 Register -- write-only */ 259 #define PIC_FORCE_ALWAYS_INTR_4 0x000001A0 260 261 /* Force Always Interrupt 5 Register -- write-only */ 262 #define PIC_FORCE_ALWAYS_INTR_5 0x000001A8 263 264 /* Force Always Interrupt 6 Register -- write-only */ 265 #define PIC_FORCE_ALWAYS_INTR_6 0x000001B0 266 267 /* Force Always Interrupt 7 Register -- write-only */ 268 #define PIC_FORCE_ALWAYS_INTR_7 0x000001B8 269 270 /* Force w/Pin Interrupt 0 Register -- write-only */ 271 #define PIC_FORCE_PIN_INTR_0 0x000001C0 272 273 /* Force w/Pin Interrupt 1 Register -- write-only */ 274 #define PIC_FORCE_PIN_INTR_1 0x000001C8 275 276 /* Force w/Pin Interrupt 2 Register -- write-only */ 277 #define PIC_FORCE_PIN_INTR_2 0x000001D0 278 279 /* Force w/Pin Interrupt 3 Register -- write-only */ 280 #define PIC_FORCE_PIN_INTR_3 0x000001D8 281 282 /* Force w/Pin Interrupt 4 Register -- write-only */ 283 #define PIC_FORCE_PIN_INTR_4 0x000001E0 284 285 /* Force w/Pin Interrupt 5 Register -- write-only */ 286 #define PIC_FORCE_PIN_INTR_5 0x000001E8 287 288 /* Force w/Pin Interrupt 6 Register -- write-only */ 289 #define PIC_FORCE_PIN_INTR_6 0x000001F0 290 291 /* Force w/Pin Interrupt 7 Register -- write-only */ 292 #define PIC_FORCE_PIN_INTR_7 0x000001F8 293 294 /* Device 0 Register -- read/write */ 295 #define PIC_DEVICE_0 0x00000200 296 297 /* Device 1 Register -- read/write */ 298 #define PIC_DEVICE_1 0x00000208 299 300 /* Device 2 Register -- read/write */ 301 #define PIC_DEVICE_2 0x00000210 302 303 /* Device 3 Register -- read/write */ 304 #define PIC_DEVICE_3 0x00000218 305 306 /* Device 0 Write Request Buffer Register -- read-only */ 307 #define PIC_DEVICE_0_WRITE_REQ_BUF 0x00000240 308 309 /* Device 1 Write Request Buffer Register -- read-only */ 310 #define PIC_DEVICE_1_WRITE_REQ_BUF 0x00000248 311 312 /* Device 2 Write Request Buffer Register -- read-only */ 313 #define PIC_DEVICE_2_WRITE_REQ_BUF 0x00000250 314 315 /* Device 3 Write Request Buffer Register -- read-only */ 316 #define PIC_DEVICE_3_WRITE_REQ_BUF 0x00000258 317 318 /* Even Device Response Buffer Register -- read/write */ 319 #define PIC_EVEN_DEVICE_RESP_BUF 0x00000280 320 321 /* Odd Device Response Buffer Register -- read/write */ 322 #define PIC_ODD_DEVICE_RESP_BUF 0x00000288 323 324 /* Read Response Buffer Status Register -- read-only */ 325 #define PIC_READ_RESP_BUF_STATUS 0x00000290 326 327 /* Read Response Buffer Clear Register -- write-only */ 328 #define PIC_READ_RESP_BUF_CLEAR 0x00000298 329 330 /* PCI RR 0 Upper Address Match Register -- read-only */ 331 #define PIC_PCI_RR_0_UPPER_ADDR_MATCH 0x00000300 332 333 /* PCI RR 0 Lower Address Match Register -- read-only */ 334 #define PIC_PCI_RR_0_LOWER_ADDR_MATCH 0x00000308 335 336 /* PCI RR 1 Upper Address Match Register -- read-only */ 337 #define PIC_PCI_RR_1_UPPER_ADDR_MATCH 0x00000310 338 339 /* PCI RR 1 Lower Address Match Register -- read-only */ 340 #define PIC_PCI_RR_1_LOWER_ADDR_MATCH 0x00000318 341 342 /* PCI RR 2 Upper Address Match Register -- read-only */ 343 #define PIC_PCI_RR_2_UPPER_ADDR_MATCH 0x00000320 344 345 /* PCI RR 2 Lower Address Match Register -- read-only */ 346 #define PIC_PCI_RR_2_LOWER_ADDR_MATCH 0x00000328 347 348 /* PCI RR 3 Upper Address Match Register -- read-only */ 349 #define PIC_PCI_RR_3_UPPER_ADDR_MATCH 0x00000330 350 351 /* PCI RR 3 Lower Address Match Register -- read-only */ 352 #define PIC_PCI_RR_3_LOWER_ADDR_MATCH 0x00000338 353 354 /* PCI RR 4 Upper Address Match Register -- read-only */ 355 #define PIC_PCI_RR_4_UPPER_ADDR_MATCH 0x00000340 356 357 /* PCI RR 4 Lower Address Match Register -- read-only */ 358 #define PIC_PCI_RR_4_LOWER_ADDR_MATCH 0x00000348 359 360 /* PCI RR 5 Upper Address Match Register -- read-only */ 361 #define PIC_PCI_RR_5_UPPER_ADDR_MATCH 0x00000350 362 363 /* PCI RR 5 Lower Address Match Register -- read-only */ 364 #define PIC_PCI_RR_5_LOWER_ADDR_MATCH 0x00000358 365 366 /* PCI RR 6 Upper Address Match Register -- read-only */ 367 #define PIC_PCI_RR_6_UPPER_ADDR_MATCH 0x00000360 368 369 /* PCI RR 6 Lower Address Match Register -- read-only */ 370 #define PIC_PCI_RR_6_LOWER_ADDR_MATCH 0x00000368 371 372 /* PCI RR 7 Upper Address Match Register -- read-only */ 373 #define PIC_PCI_RR_7_UPPER_ADDR_MATCH 0x00000370 374 375 /* PCI RR 7 Lower Address Match Register -- read-only */ 376 #define PIC_PCI_RR_7_LOWER_ADDR_MATCH 0x00000378 377 378 /* PCI RR 8 Upper Address Match Register -- read-only */ 379 #define PIC_PCI_RR_8_UPPER_ADDR_MATCH 0x00000380 380 381 /* PCI RR 8 Lower Address Match Register -- read-only */ 382 #define PIC_PCI_RR_8_LOWER_ADDR_MATCH 0x00000388 383 384 /* PCI RR 9 Upper Address Match Register -- read-only */ 385 #define PIC_PCI_RR_9_UPPER_ADDR_MATCH 0x00000390 386 387 /* PCI RR 9 Lower Address Match Register -- read-only */ 388 #define PIC_PCI_RR_9_LOWER_ADDR_MATCH 0x00000398 389 390 /* PCI RR 10 Upper Address Match Register -- read-only */ 391 #define PIC_PCI_RR_10_UPPER_ADDR_MATCH 0x000003A0 392 393 /* PCI RR 10 Lower Address Match Register -- read-only */ 394 #define PIC_PCI_RR_10_LOWER_ADDR_MATCH 0x000003A8 395 396 /* PCI RR 11 Upper Address Match Register -- read-only */ 397 #define PIC_PCI_RR_11_UPPER_ADDR_MATCH 0x000003B0 398 399 /* PCI RR 11 Lower Address Match Register -- read-only */ 400 #define PIC_PCI_RR_11_LOWER_ADDR_MATCH 0x000003B8 401 402 /* PCI RR 12 Upper Address Match Register -- read-only */ 403 #define PIC_PCI_RR_12_UPPER_ADDR_MATCH 0x000003C0 404 405 /* PCI RR 12 Lower Address Match Register -- read-only */ 406 #define PIC_PCI_RR_12_LOWER_ADDR_MATCH 0x000003C8 407 408 /* PCI RR 13 Upper Address Match Register -- read-only */ 409 #define PIC_PCI_RR_13_UPPER_ADDR_MATCH 0x000003D0 410 411 /* PCI RR 13 Lower Address Match Register -- read-only */ 412 #define PIC_PCI_RR_13_LOWER_ADDR_MATCH 0x000003D8 413 414 /* PCI RR 14 Upper Address Match Register -- read-only */ 415 #define PIC_PCI_RR_14_UPPER_ADDR_MATCH 0x000003E0 416 417 /* PCI RR 14 Lower Address Match Register -- read-only */ 418 #define PIC_PCI_RR_14_LOWER_ADDR_MATCH 0x000003E8 419 420 /* PCI RR 15 Upper Address Match Register -- read-only */ 421 #define PIC_PCI_RR_15_UPPER_ADDR_MATCH 0x000003F0 422 423 /* PCI RR 15 Lower Address Match Register -- read-only */ 424 #define PIC_PCI_RR_15_LOWER_ADDR_MATCH 0x000003F8 425 426 /* Buffer 0 Flush Count with Data Touch Register -- read/write */ 427 #define PIC_BUF_0_FLUSH_CNT_WITH_DATA_TOUCH 0x00000400 428 429 /* Buffer 0 Flush Count w/o Data Touch Register -- read/write */ 430 #define PIC_BUF_0_FLUSH_CNT_W_O_DATA_TOUCH 0x00000408 431 432 /* Buffer 0 Request in Flight Count Register -- read/write */ 433 #define PIC_BUF_0_REQ_IN_FLIGHT_CNT 0x00000410 434 435 /* Buffer 0 Prefetch Request Count Register -- read/write */ 436 #define PIC_BUF_0_PREFETCH_REQ_CNT 0x00000418 437 438 /* Buffer 0 Total PCI Retry Count Register -- read/write */ 439 #define PIC_BUF_0_TOTAL_PCI_RETRY_CNT 0x00000420 440 441 /* Buffer 0 Max PCI Retry Count Register -- read/write */ 442 #define PIC_BUF_0_MAX_PCI_RETRY_CNT 0x00000428 443 444 /* Buffer 0 Max Latency Count Register -- read/write */ 445 #define PIC_BUF_0_MAX_LATENCY_CNT 0x00000430 446 447 /* Buffer 0 Clear All Register -- read/write */ 448 #define PIC_BUF_0_CLEAR_ALL 0x00000438 449 450 /* Buffer 2 Flush Count with Data Touch Register -- read/write */ 451 #define PIC_BUF_2_FLUSH_CNT_WITH_DATA_TOUCH 0x00000440 452 453 /* Buffer 2 Flush Count w/o Data Touch Register -- read/write */ 454 #define PIC_BUF_2_FLUSH_CNT_W_O_DATA_TOUCH 0x00000448 455 456 /* Buffer 2 Request in Flight Count Register -- read/write */ 457 #define PIC_BUF_2_REQ_IN_FLIGHT_CNT 0x00000450 458 459 /* Buffer 2 Prefetch Request Count Register -- read/write */ 460 #define PIC_BUF_2_PREFETCH_REQ_CNT 0x00000458 461 462 /* Buffer 2 Total PCI Retry Count Register -- read/write */ 463 #define PIC_BUF_2_TOTAL_PCI_RETRY_CNT 0x00000460 464 465 /* Buffer 2 Max PCI Retry Count Register -- read/write */ 466 #define PIC_BUF_2_MAX_PCI_RETRY_CNT 0x00000468 467 468 /* Buffer 2 Max Latency Count Register -- read/write */ 469 #define PIC_BUF_2_MAX_LATENCY_CNT 0x00000470 470 471 /* Buffer 2 Clear All Register -- read/write */ 472 #define PIC_BUF_2_CLEAR_ALL 0x00000478 473 474 /* Buffer 4 Flush Count with Data Touch Register -- read/write */ 475 #define PIC_BUF_4_FLUSH_CNT_WITH_DATA_TOUCH 0x00000480 476 477 /* Buffer 4 Flush Count w/o Data Touch Register -- read/write */ 478 #define PIC_BUF_4_FLUSH_CNT_W_O_DATA_TOUCH 0x00000488 479 480 /* Buffer 4 Request in Flight Count Register -- read/write */ 481 #define PIC_BUF_4_REQ_IN_FLIGHT_CNT 0x00000490 482 483 /* Buffer 4 Prefetch Request Count Register -- read/write */ 484 #define PIC_BUF_4_PREFETCH_REQ_CNT 0x00000498 485 486 /* Buffer 4 Total PCI Retry Count Register -- read/write */ 487 #define PIC_BUF_4_TOTAL_PCI_RETRY_CNT 0x000004A0 488 489 /* Buffer 4 Max PCI Retry Count Register -- read/write */ 490 #define PIC_BUF_4_MAX_PCI_RETRY_CNT 0x000004A8 491 492 /* Buffer 4 Max Latency Count Register -- read/write */ 493 #define PIC_BUF_4_MAX_LATENCY_CNT 0x000004B0 494 495 /* Buffer 4 Clear All Register -- read/write */ 496 #define PIC_BUF_4_CLEAR_ALL 0x000004B8 497 498 /* Buffer 6 Flush Count with Data Touch Register -- read/write */ 499 #define PIC_BUF_6_FLUSH_CNT_WITH_DATA_TOUCH 0x000004C0 500 501 /* Buffer 6 Flush Count w/o Data Touch Register -- read/write */ 502 #define PIC_BUF_6_FLUSH_CNT_W_O_DATA_TOUCH 0x000004C8 503 504 /* Buffer 6 Request in Flight Count Register -- read/write */ 505 #define PIC_BUF_6_REQ_IN_FLIGHT_CNT 0x000004D0 506 507 /* Buffer 6 Prefetch Request Count Register -- read/write */ 508 #define PIC_BUF_6_PREFETCH_REQ_CNT 0x000004D8 509 510 /* Buffer 6 Total PCI Retry Count Register -- read/write */ 511 #define PIC_BUF_6_TOTAL_PCI_RETRY_CNT 0x000004E0 512 513 /* Buffer 6 Max PCI Retry Count Register -- read/write */ 514 #define PIC_BUF_6_MAX_PCI_RETRY_CNT 0x000004E8 515 516 /* Buffer 6 Max Latency Count Register -- read/write */ 517 #define PIC_BUF_6_MAX_LATENCY_CNT 0x000004F0 518 519 /* Buffer 6 Clear All Register -- read/write */ 520 #define PIC_BUF_6_CLEAR_ALL 0x000004F8 521 522 /* Buffer 8 Flush Count with Data Touch Register -- read/write */ 523 #define PIC_BUF_8_FLUSH_CNT_WITH_DATA_TOUCH 0x00000500 524 525 /* Buffer 8 Flush Count w/o Data Touch Register -- read/write */ 526 #define PIC_BUF_8_FLUSH_CNT_W_O_DATA_TOUCH 0x00000508 527 528 /* Buffer 8 Request in Flight Count Register -- read/write */ 529 #define PIC_BUF_8_REQ_IN_FLIGHT_CNT 0x00000510 530 531 /* Buffer 8 Prefetch Request Count Register -- read/write */ 532 #define PIC_BUF_8_PREFETCH_REQ_CNT 0x00000518 533 534 /* Buffer 8 Total PCI Retry Count Register -- read/write */ 535 #define PIC_BUF_8_TOTAL_PCI_RETRY_CNT 0x00000520 536 537 /* Buffer 8 Max PCI Retry Count Register -- read/write */ 538 #define PIC_BUF_8_MAX_PCI_RETRY_CNT 0x00000528 539 540 /* Buffer 8 Max Latency Count Register -- read/write */ 541 #define PIC_BUF_8_MAX_LATENCY_CNT 0x00000530 542 543 /* Buffer 8 Clear All Register -- read/write */ 544 #define PIC_BUF_8_CLEAR_ALL 0x00000538 545 546 /* Buffer 10 Flush Count with Data Touch Register -- read/write */ 547 #define PIC_BUF_10_FLUSH_CNT_WITH_DATA_TOUCH 0x00000540 548 549 /* Buffer 10 Flush Count w/o Data Touch Register -- read/write */ 550 #define PIC_BUF_10_FLUSH_CNT_W_O_DATA_TOUCH 0x00000548 551 552 /* Buffer 10 Request in Flight Count Register -- read/write */ 553 #define PIC_BUF_10_REQ_IN_FLIGHT_CNT 0x00000550 554 555 /* Buffer 10 Prefetch Request Count Register -- read/write */ 556 #define PIC_BUF_10_PREFETCH_REQ_CNT 0x00000558 557 558 /* Buffer 10 Total PCI Retry Count Register -- read/write */ 559 #define PIC_BUF_10_TOTAL_PCI_RETRY_CNT 0x00000560 560 561 /* Buffer 10 Max PCI Retry Count Register -- read/write */ 562 #define PIC_BUF_10_MAX_PCI_RETRY_CNT 0x00000568 563 564 /* Buffer 10 Max Latency Count Register -- read/write */ 565 #define PIC_BUF_10_MAX_LATENCY_CNT 0x00000570 566 567 /* Buffer 10 Clear All Register -- read/write */ 568 #define PIC_BUF_10_CLEAR_ALL 0x00000578 569 570 /* Buffer 12 Flush Count with Data Touch Register -- read/write */ 571 #define PIC_BUF_12_FLUSH_CNT_WITH_DATA_TOUCH 0x00000580 572 573 /* Buffer 12 Flush Count w/o Data Touch Register -- read/write */ 574 #define PIC_BUF_12_FLUSH_CNT_W_O_DATA_TOUCH 0x00000588 575 576 /* Buffer 12 Request in Flight Count Register -- read/write */ 577 #define PIC_BUF_12_REQ_IN_FLIGHT_CNT 0x00000590 578 579 /* Buffer 12 Prefetch Request Count Register -- read/write */ 580 #define PIC_BUF_12_PREFETCH_REQ_CNT 0x00000598 581 582 /* Buffer 12 Total PCI Retry Count Register -- read/write */ 583 #define PIC_BUF_12_TOTAL_PCI_RETRY_CNT 0x000005A0 584 585 /* Buffer 12 Max PCI Retry Count Register -- read/write */ 586 #define PIC_BUF_12_MAX_PCI_RETRY_CNT 0x000005A8 587 588 /* Buffer 12 Max Latency Count Register -- read/write */ 589 #define PIC_BUF_12_MAX_LATENCY_CNT 0x000005B0 590 591 /* Buffer 12 Clear All Register -- read/write */ 592 #define PIC_BUF_12_CLEAR_ALL 0x000005B8 593 594 /* Buffer 14 Flush Count with Data Touch Register -- read/write */ 595 #define PIC_BUF_14_FLUSH_CNT_WITH_DATA_TOUCH 0x000005C0 596 597 /* Buffer 14 Flush Count w/o Data Touch Register -- read/write */ 598 #define PIC_BUF_14_FLUSH_CNT_W_O_DATA_TOUCH 0x000005C8 599 600 /* Buffer 14 Request in Flight Count Register -- read/write */ 601 #define PIC_BUF_14_REQ_IN_FLIGHT_CNT 0x000005D0 602 603 /* Buffer 14 Prefetch Request Count Register -- read/write */ 604 #define PIC_BUF_14_PREFETCH_REQ_CNT 0x000005D8 605 606 /* Buffer 14 Total PCI Retry Count Register -- read/write */ 607 #define PIC_BUF_14_TOTAL_PCI_RETRY_CNT 0x000005E0 608 609 /* Buffer 14 Max PCI Retry Count Register -- read/write */ 610 #define PIC_BUF_14_MAX_PCI_RETRY_CNT 0x000005E8 611 612 /* Buffer 14 Max Latency Count Register -- read/write */ 613 #define PIC_BUF_14_MAX_LATENCY_CNT 0x000005F0 614 615 /* Buffer 14 Clear All Register -- read/write */ 616 #define PIC_BUF_14_CLEAR_ALL 0x000005F8 617 618 /* PCIX Read Buffer 0 Address Register -- read-only */ 619 #define PIC_PCIX_READ_BUF_0_ADDR 0x00000A00 620 621 /* PCIX Read Buffer 0 Attribute Register -- read-only */ 622 #define PIC_PCIX_READ_BUF_0_ATTRIBUTE 0x00000A08 623 624 /* PCIX Read Buffer 1 Address Register -- read-only */ 625 #define PIC_PCIX_READ_BUF_1_ADDR 0x00000A10 626 627 /* PCIX Read Buffer 1 Attribute Register -- read-only */ 628 #define PIC_PCIX_READ_BUF_1_ATTRIBUTE 0x00000A18 629 630 /* PCIX Read Buffer 2 Address Register -- read-only */ 631 #define PIC_PCIX_READ_BUF_2_ADDR 0x00000A20 632 633 /* PCIX Read Buffer 2 Attribute Register -- read-only */ 634 #define PIC_PCIX_READ_BUF_2_ATTRIBUTE 0x00000A28 635 636 /* PCIX Read Buffer 3 Address Register -- read-only */ 637 #define PIC_PCIX_READ_BUF_3_ADDR 0x00000A30 638 639 /* PCIX Read Buffer 3 Attribute Register -- read-only */ 640 #define PIC_PCIX_READ_BUF_3_ATTRIBUTE 0x00000A38 641 642 /* PCIX Read Buffer 4 Address Register -- read-only */ 643 #define PIC_PCIX_READ_BUF_4_ADDR 0x00000A40 644 645 /* PCIX Read Buffer 4 Attribute Register -- read-only */ 646 #define PIC_PCIX_READ_BUF_4_ATTRIBUTE 0x00000A48 647 648 /* PCIX Read Buffer 5 Address Register -- read-only */ 649 #define PIC_PCIX_READ_BUF_5_ADDR 0x00000A50 650 651 /* PCIX Read Buffer 5 Attribute Register -- read-only */ 652 #define PIC_PCIX_READ_BUF_5_ATTRIBUTE 0x00000A58 653 654 /* PCIX Read Buffer 6 Address Register -- read-only */ 655 #define PIC_PCIX_READ_BUF_6_ADDR 0x00000A60 656 657 /* PCIX Read Buffer 6 Attribute Register -- read-only */ 658 #define PIC_PCIX_READ_BUF_6_ATTRIBUTE 0x00000A68 659 660 /* PCIX Read Buffer 7 Address Register -- read-only */ 661 #define PIC_PCIX_READ_BUF_7_ADDR 0x00000A70 662 663 /* PCIX Read Buffer 7 Attribute Register -- read-only */ 664 #define PIC_PCIX_READ_BUF_7_ATTRIBUTE 0x00000A78 665 666 /* PCIX Read Buffer 8 Address Register -- read-only */ 667 #define PIC_PCIX_READ_BUF_8_ADDR 0x00000A80 668 669 /* PCIX Read Buffer 8 Attribute Register -- read-only */ 670 #define PIC_PCIX_READ_BUF_8_ATTRIBUTE 0x00000A88 671 672 /* PCIX Read Buffer 9 Address Register -- read-only */ 673 #define PIC_PCIX_READ_BUF_9_ADDR 0x00000A90 674 675 /* PCIX Read Buffer 9 Attribute Register -- read-only */ 676 #define PIC_PCIX_READ_BUF_9_ATTRIBUTE 0x00000A98 677 678 /* PCIX Read Buffer 10 Address Register -- read-only */ 679 #define PIC_PCIX_READ_BUF_10_ADDR 0x00000AA0 680 681 /* PCIX Read Buffer 10 Attribute Register -- read-only */ 682 #define PIC_PCIX_READ_BUF_10_ATTRIBUTE 0x00000AA8 683 684 /* PCIX Read Buffer 11 Address Register -- read-only */ 685 #define PIC_PCIX_READ_BUF_11_ADDR 0x00000AB0 686 687 /* PCIX Read Buffer 11 Attribute Register -- read-only */ 688 #define PIC_PCIX_READ_BUF_11_ATTRIBUTE 0x00000AB8 689 690 /* PCIX Read Buffer 12 Address Register -- read-only */ 691 #define PIC_PCIX_READ_BUF_12_ADDR 0x00000AC0 692 693 /* PCIX Read Buffer 12 Attribute Register -- read-only */ 694 #define PIC_PCIX_READ_BUF_12_ATTRIBUTE 0x00000AC8 695 696 /* PCIX Read Buffer 13 Address Register -- read-only */ 697 #define PIC_PCIX_READ_BUF_13_ADDR 0x00000AD0 698 699 /* PCIX Read Buffer 13 Attribute Register -- read-only */ 700 #define PIC_PCIX_READ_BUF_13_ATTRIBUTE 0x00000AD8 701 702 /* PCIX Read Buffer 14 Address Register -- read-only */ 703 #define PIC_PCIX_READ_BUF_14_ADDR 0x00000AE0 704 705 /* PCIX Read Buffer 14 Attribute Register -- read-only */ 706 #define PIC_PCIX_READ_BUF_14_ATTRIBUTE 0x00000AE8 707 708 /* PCIX Read Buffer 15 Address Register -- read-only */ 709 #define PIC_PCIX_READ_BUF_15_ADDR 0x00000AF0 710 711 /* PCIX Read Buffer 15 Attribute Register -- read-only */ 712 #define PIC_PCIX_READ_BUF_15_ATTRIBUTE 0x00000AF8 713 714 /* PCIX Write Buffer 0 Address Register -- read-only */ 715 #define PIC_PCIX_WRITE_BUF_0_ADDR 0x00000B00 716 717 /* PCIX Write Buffer 0 Attribute Register -- read-only */ 718 #define PIC_PCIX_WRITE_BUF_0_ATTRIBUTE 0x00000B08 719 720 /* PCIX Write Buffer 0 Valid Register -- read-only */ 721 #define PIC_PCIX_WRITE_BUF_0_VALID 0x00000B10 722 723 /* PCIX Write Buffer 1 Address Register -- read-only */ 724 #define PIC_PCIX_WRITE_BUF_1_ADDR 0x00000B20 725 726 /* PCIX Write Buffer 1 Attribute Register -- read-only */ 727 #define PIC_PCIX_WRITE_BUF_1_ATTRIBUTE 0x00000B28 728 729 /* PCIX Write Buffer 1 Valid Register -- read-only */ 730 #define PIC_PCIX_WRITE_BUF_1_VALID 0x00000B30 731 732 /* PCIX Write Buffer 2 Address Register -- read-only */ 733 #define PIC_PCIX_WRITE_BUF_2_ADDR 0x00000B40 734 735 /* PCIX Write Buffer 2 Attribute Register -- read-only */ 736 #define PIC_PCIX_WRITE_BUF_2_ATTRIBUTE 0x00000B48 737 738 /* PCIX Write Buffer 2 Valid Register -- read-only */ 739 #define PIC_PCIX_WRITE_BUF_2_VALID 0x00000B50 740 741 /* PCIX Write Buffer 3 Address Register -- read-only */ 742 #define PIC_PCIX_WRITE_BUF_3_ADDR 0x00000B60 743 744 /* PCIX Write Buffer 3 Attribute Register -- read-only */ 745 #define PIC_PCIX_WRITE_BUF_3_ATTRIBUTE 0x00000B68 746 747 /* PCIX Write Buffer 3 Valid Register -- read-only */ 748 #define PIC_PCIX_WRITE_BUF_3_VALID 0x00000B70 749 750 /* PCIX Write Buffer 4 Address Register -- read-only */ 751 #define PIC_PCIX_WRITE_BUF_4_ADDR 0x00000B80 752 753 /* PCIX Write Buffer 4 Attribute Register -- read-only */ 754 #define PIC_PCIX_WRITE_BUF_4_ATTRIBUTE 0x00000B88 755 756 /* PCIX Write Buffer 4 Valid Register -- read-only */ 757 #define PIC_PCIX_WRITE_BUF_4_VALID 0x00000B90 758 759 /* PCIX Write Buffer 5 Address Register -- read-only */ 760 #define PIC_PCIX_WRITE_BUF_5_ADDR 0x00000BA0 761 762 /* PCIX Write Buffer 5 Attribute Register -- read-only */ 763 #define PIC_PCIX_WRITE_BUF_5_ATTRIBUTE 0x00000BA8 764 765 /* PCIX Write Buffer 5 Valid Register -- read-only */ 766 #define PIC_PCIX_WRITE_BUF_5_VALID 0x00000BB0 767 768 /* PCIX Write Buffer 6 Address Register -- read-only */ 769 #define PIC_PCIX_WRITE_BUF_6_ADDR 0x00000BC0 770 771 /* PCIX Write Buffer 6 Attribute Register -- read-only */ 772 #define PIC_PCIX_WRITE_BUF_6_ATTRIBUTE 0x00000BC8 773 774 /* PCIX Write Buffer 6 Valid Register -- read-only */ 775 #define PIC_PCIX_WRITE_BUF_6_VALID 0x00000BD0 776 777 /* PCIX Write Buffer 7 Address Register -- read-only */ 778 #define PIC_PCIX_WRITE_BUF_7_ADDR 0x00000BE0 779 780 /* PCIX Write Buffer 7 Attribute Register -- read-only */ 781 #define PIC_PCIX_WRITE_BUF_7_ATTRIBUTE 0x00000BE8 782 783 /* PCIX Write Buffer 7 Valid Register -- read-only */ 784 #define PIC_PCIX_WRITE_BUF_7_VALID 0x00000BF0 785 786 /********************************************************************* 787 * misc typedefs 788 * 789 */ 790 typedef uint64_t picreg_t; 791 792 /********************************************************************* 793 * PIC register structures 794 * 795 */ 796 797 /* 798 * Identification Register 799 * 800 * The Identification register is a read only register used by the host CPU 801 * during configuration to determine the type of the widget. The format is 802 * the same as defined in IEEE 1149.1 JTAG Device Identification Register. 803 */ 804 typedef union pic_id_reg_u { 805 picreg_t pic_id_reg_regval; 806 struct { 807 picreg_t : 32; /* 63:32 */ 808 picreg_t rev_num : 4; /* 31:28 */ 809 picreg_t part_num : 16; /* 27:12 */ 810 picreg_t mfg_num : 11; /* 11:1 */ 811 picreg_t : 1; /* 0:0 */ 812 } pic_id_reg_fld_s; 813 } pic_id_reg_u_t; 814 /* 815 * Status Register 816 * 817 * The status register is a read register which holds status information of the 818 * Bus Subsection. 819 */ 820 typedef union pic_stat_reg_u { 821 picreg_t pic_stat_reg_regval; 822 struct { 823 picreg_t : 28; /* 63:36 */ 824 picreg_t pci_x_speed : 2; /* 35:34 */ 825 picreg_t pci_x_active : 1; /* 33:33 */ 826 picreg_t : 1; /* 32:32 */ 827 picreg_t llp_rec_cnt : 8; /* 31:24 */ 828 picreg_t llp_tx_cnt : 8; /* 23:16 */ 829 picreg_t rx_credit_cnt : 4; /* 15:12 */ 830 picreg_t tx_credit_cnt : 4; /* 11:8 */ 831 picreg_t pci_misc_input : 8; /* 7:0 */ 832 } pic_stat_reg_fld_s; 833 } pic_stat_reg_u_t; 834 /* 835 * Upper Address Holding Register Bus Side Errors 836 * 837 * The upper address holding register is a read only register which contains 838 * the upper 16-bits of the address when certain error occurs (see error cases 839 * chapter). Subsequent errors are not logged until the error is cleared. The 840 * last logged value is held until the group is cleared and enabled. 841 */ 842 typedef union pic_upper_bus_err_u { 843 picreg_t pic_upper_bus_err_regval; 844 struct { 845 picreg_t : 32; /* 63:32 */ 846 picreg_t : 16; /* 31:16 */ 847 picreg_t upp_addr : 16; /* 15:0 */ 848 } pic_upper_bus_err_fld_s; 849 } pic_upper_bus_err_u_t; 850 /* 851 * Lower Address Holding Register Bus Side Errors 852 * 853 * The lower address holding register is a read only register which contains 854 * the address which either can be accessed as a word or double word. Sub- 855 * sequent errors are not logged until the error is cleared. The last logged 856 * value is held until the group is cleared and enabled. 857 */ 858 typedef union pic_lower_bus_err_u { 859 picreg_t pic_lower_bus_err_regval; 860 struct { 861 picreg_t : 16; /* 63:48 */ 862 picreg_t upp_addr : 16; /* 47:32 */ 863 picreg_t low_addr : 32; /* 31:0 */ 864 } pic_lower_bus_err_fld_s; 865 } pic_lower_bus_err_u_t; 866 /* 867 * Control Register 868 * 869 * The control register is a read/write register which holds control informa- 870 * tion for the bus subsection. 871 */ 872 typedef union pic_control_reg_u { 873 picreg_t pic_control_reg_regval; 874 struct { 875 picreg_t : 32; /* 63:32 */ 876 picreg_t : 4; /* 31:28 */ 877 picreg_t rst_pin_n : 4; /* 27:24 */ 878 picreg_t : 1; /* 23:23 */ 879 picreg_t mem_swap : 1; /* 22:22 */ 880 picreg_t page_size : 1; /* 21:21 */ 881 picreg_t : 4; /* 20:17 */ 882 picreg_t f_bad_pkt : 1; /* 16:16 */ 883 picreg_t llp_xbar_crd : 4; /* 15:12 */ 884 picreg_t clr_rllp_cnt : 1; /* 11:11 */ 885 picreg_t clr_tllp_cnt : 1; /* 10:10 */ 886 picreg_t sys_end : 1; /* 9:9 */ 887 picreg_t : 3; /* 8:6 */ 888 picreg_t pci_speed : 2; /* 5:4 */ 889 picreg_t widget_id : 4; /* 3:0 */ 890 } pic_control_reg_fld_s; 891 } pic_control_reg_u_t; 892 /* 893 * PCI/PCI-X Request Time-out Value Register 894 * 895 * This register contains the reload value for the response timer. The request 896 * timer counts every 960 nS (32 PCI clocks) 897 */ 898 typedef union pic_pci_req_to_u { 899 picreg_t pic_pci_req_to_regval; 900 struct { 901 picreg_t : 32; /* 63:32 */ 902 picreg_t : 12; /* 31:20 */ 903 picreg_t time_out : 20; /* 19:0 */ 904 } pic_pci_req_to_fld_s; 905 } pic_pci_req_to_u_t; 906 /* 907 * Interrupt Destination Upper Address Register 908 * 909 * The interrupt destination upper address register is a read/write register 910 * containing the upper 16-bits of address of the host to which the interrupt 911 * is targeted. In addition the target ID is also contained in this register for 912 * use in Crosstalk mode. 913 */ 914 typedef union pic_int_desc_upper_u { 915 picreg_t pic_int_desc_upper_regval; 916 struct { 917 picreg_t : 32; /* 63:32 */ 918 picreg_t : 12; /* 31:20 */ 919 picreg_t target_id : 4; /* 19:16 */ 920 picreg_t upp_addr : 16; /* 15:0 */ 921 } pic_int_desc_upper_fld_s; 922 } pic_int_desc_upper_u_t; 923 /* 924 * Interrupt Destination Lower Address Register 925 * 926 * The interrupt destination lower address register is a read/write register 927 * which contains the entire address of the host to which the interrupt is tar- 928 * geted. In addition the target ID is also contained in this register for use in 929 * Crosstalk mode. 930 */ 931 typedef union pic_int_desc_lower_u { 932 picreg_t pic_int_desc_lower_regval; 933 struct { 934 picreg_t : 12; /* 63:52 */ 935 picreg_t target_id : 4; /* 51:48 */ 936 picreg_t upp_addr : 16; /* 47:32 */ 937 picreg_t low_addr : 32; /* 31:0 */ 938 } pic_int_desc_lower_fld_s; 939 } pic_int_desc_lower_u_t; 940 /* 941 * Command Word Holding Register Bus Side Errors 942 * 943 * The command word holding is a read register that holds the command 944 * word of a Crosstalk packet when errors occur on the link side (see error 945 * chapter). Errors are indicated with error bits in the interrupt status regis- 946 * ter. Subsequent errors are not logged until the interrupt is cleared.. 947 */ 948 typedef union pic_cmd_word_bus_err_u { 949 picreg_t pic_cmd_word_bus_err_regval; 950 struct { 951 picreg_t : 32; /* 63:32 */ 952 picreg_t didn : 4; /* 31:28 */ 953 picreg_t sidn : 4; /* 27:24 */ 954 picreg_t pactyp : 4; /* 23:20 */ 955 picreg_t tnum : 5; /* 19:15 */ 956 picreg_t coherent : 1; /* 14:14 */ 957 picreg_t ds : 2; /* 13:12 */ 958 picreg_t gbr : 1; /* 11:11 */ 959 picreg_t vbpm : 1; /* 10:10 */ 960 picreg_t error : 1; /* 9:9 */ 961 picreg_t barrier : 1; /* 8:8 */ 962 picreg_t : 8; /* 7:0 */ 963 } pic_cmd_word_bus_err_fld_s; 964 } pic_cmd_word_bus_err_u_t; 965 /* 966 * LLP Configuration Register 967 * 968 * This register contains the configuration information for the LLP modules 969 * and is only valid on bus 0 side. 970 */ 971 typedef union pic_llp_cfg_u { 972 picreg_t pic_llp_cfg_regval; 973 struct { 974 picreg_t : 32; /* 63:32 */ 975 picreg_t : 6; /* 31:26 */ 976 picreg_t llp_maxretry : 10; /* 25:16 */ 977 picreg_t llp_nulltimeout : 6; /* 15:10 */ 978 picreg_t llp_maxburst : 10; /* 9:0 */ 979 } pic_llp_cfg_fld_s; 980 } pic_llp_cfg_u_t; 981 /* 982 * PCI/PCI-X Target Flush Register 983 * 984 * When read, this register will return a 0x00 after all previous transfers to 985 * the PCI bus subsection have completed. 986 */ 987 988 /* 989 * Command Word Holding Register Link Side Errors 990 * 991 * The command word holding is a read-only register that holds the com- 992 * mand word of a Crosstalk packet when request fifo overflow or unexpect- 993 * ed response errors occur. Errors are indicated with error bits in the 994 * interrupt status register. Subsequent errors are not logged until this inter- 995 * rupt is cleared. 996 */ 997 typedef union pic_cmd_word_link_err_u { 998 picreg_t pic_cmd_word_link_err_regval; 999 struct { 1000 picreg_t : 32; /* 63:32 */ 1001 picreg_t didn : 4; /* 31:28 */ 1002 picreg_t sidn : 4; /* 27:24 */ 1003 picreg_t pactyp : 4; /* 23:20 */ 1004 picreg_t tnum : 5; /* 19:15 */ 1005 picreg_t coherent : 1; /* 14:14 */ 1006 picreg_t ds : 2; /* 13:12 */ 1007 picreg_t gbr : 1; /* 11:11 */ 1008 picreg_t vbpm : 1; /* 10:10 */ 1009 picreg_t error : 1; /* 9:9 */ 1010 picreg_t barrier : 1; /* 8:8 */ 1011 picreg_t : 8; /* 7:0 */ 1012 } pic_cmd_word_link_err_fld_s; 1013 } pic_cmd_word_link_err_u_t; 1014 /* 1015 * PCI Response Buffer Error Upper Address Holding Reg 1016 * 1017 * The response buffer error upper address holding register is a read only 1018 * register which contains the upper 16-bits of the address when error asso- 1019 * ciated with response buffer entries occur. Subsequent errors are not 1020 * logged until the interrupt is cleared. 1021 */ 1022 typedef union pic_pci_rbuf_err_upper_u { 1023 picreg_t pic_pci_rbuf_err_upper_regval; 1024 struct { 1025 picreg_t : 32; /* 63:32 */ 1026 picreg_t : 9; /* 31:23 */ 1027 picreg_t dev_num : 3; /* 22:20 */ 1028 picreg_t buff_num : 4; /* 19:16 */ 1029 picreg_t upp_addr : 16; /* 15:0 */ 1030 } pic_pci_rbuf_err_upper_fld_s; 1031 } pic_pci_rbuf_err_upper_u_t; 1032 /* 1033 * PCI Response Buffer Error Lower Address Holding Reg 1034 * 1035 * The response buffer error lower address holding register is a read only 1036 * register which contains the address of the error associated with response 1037 * buffer entries. Subsequent errors are not logged until the interrupt is 1038 * cleared. 1039 */ 1040 typedef union pic_pci_rbuf_err_lower_u { 1041 picreg_t pic_pci_rbuf_err_lower_regval; 1042 struct { 1043 picreg_t : 9; /* 63:55 */ 1044 picreg_t dev_num : 3; /* 54:52 */ 1045 picreg_t buff_num : 4; /* 51:48 */ 1046 picreg_t upp_addr : 16; /* 47:32 */ 1047 picreg_t low_addr : 32; /* 31:0 */ 1048 } pic_pci_rbuf_err_lower_fld_s; 1049 } pic_pci_rbuf_err_lower_u_t; 1050 /* 1051 * Test Pin Control Register 1052 * 1053 * This register selects the output function and value to the four test pins on 1054 * the PIC . 1055 */ 1056 typedef union pic_test_pin_cntl_u { 1057 picreg_t pic_test_pin_cntl_regval; 1058 struct { 1059 picreg_t : 32; /* 63:32 */ 1060 picreg_t : 8; /* 31:24 */ 1061 picreg_t tdata_out : 8; /* 23:16 */ 1062 picreg_t sel_tpin_7 : 2; /* 15:14 */ 1063 picreg_t sel_tpin_6 : 2; /* 13:12 */ 1064 picreg_t sel_tpin_5 : 2; /* 11:10 */ 1065 picreg_t sel_tpin_4 : 2; /* 9:8 */ 1066 picreg_t sel_tpin_3 : 2; /* 7:6 */ 1067 picreg_t sel_tpin_2 : 2; /* 5:4 */ 1068 picreg_t sel_tpin_1 : 2; /* 3:2 */ 1069 picreg_t sel_tpin_0 : 2; /* 1:0 */ 1070 } pic_test_pin_cntl_fld_s; 1071 } pic_test_pin_cntl_u_t; 1072 /* 1073 * Address Holding Register Link Side Errors 1074 * 1075 * The address holding register is a read only register which contains the ad- 1076 * dress which either can be accessed as a word or double word. Subsequent 1077 * errors are not logged until the error is cleared. The last logged value is 1078 * held until the group is cleared and enabled. 1079 */ 1080 typedef union pic_p_addr_lkerr_u { 1081 picreg_t pic_p_addr_lkerr_regval; 1082 struct { 1083 picreg_t : 16; /* 63:48 */ 1084 picreg_t upp_addr : 16; /* 47:32 */ 1085 picreg_t low_addr : 32; /* 31:0 */ 1086 } pic_p_addr_lkerr_fld_s; 1087 } pic_p_addr_lkerr_u_t; 1088 /* 1089 * PCI Direct Mapping Register 1090 * 1091 * This register is used to relocate a 2 GByte region for PCI to Crosstalk 1092 * transfers. 1093 */ 1094 typedef union pic_p_dir_map_u { 1095 picreg_t pic_p_dir_map_regval; 1096 struct { 1097 picreg_t : 32; /* 63:32 */ 1098 picreg_t : 8; /* 31:24 */ 1099 picreg_t dir_w_id : 4; /* 23:20 */ 1100 picreg_t : 2; /* 19:18 */ 1101 picreg_t dir_add512 : 1; /* 17:17 */ 1102 picreg_t dir_off : 17; /* 16:0 */ 1103 } pic_p_dir_map_fld_s; 1104 } pic_p_dir_map_u_t; 1105 /* 1106 * PCI Page Map Fault Address Register 1107 * 1108 * This register contains the address and device number when a page map 1109 * fault occurred. 1110 */ 1111 typedef union pic_p_map_fault_u { 1112 picreg_t pic_p_map_fault_regval; 1113 struct { 1114 picreg_t : 32; /* 63:32 */ 1115 picreg_t : 10; /* 31:22 */ 1116 picreg_t pci_addr : 18; /* 21:4 */ 1117 picreg_t : 1; /* 3:3 */ 1118 picreg_t pci_dev_num : 3; /* 2:0 */ 1119 } pic_p_map_fault_fld_s; 1120 } pic_p_map_fault_u_t; 1121 /* 1122 * Arbitration Register 1123 * 1124 * This register defines the priority and bus time out timing in PCI bus arbi- 1125 * tration. 1126 */ 1127 typedef union pic_p_arb_u { 1128 picreg_t pic_p_arb_regval; 1129 struct { 1130 picreg_t : 32; /* 63:32 */ 1131 picreg_t : 8; /* 31:24 */ 1132 picreg_t dev_broke : 4; /* 23:20 */ 1133 picreg_t : 2; /* 19:18 */ 1134 picreg_t req_wait_tick : 2; /* 17:16 */ 1135 picreg_t : 4; /* 15:12 */ 1136 picreg_t req_wait_en : 4; /* 11:8 */ 1137 picreg_t disarb : 1; /* 7:7 */ 1138 picreg_t freeze_gnt : 1; /* 6:6 */ 1139 picreg_t : 1; /* 5:5 */ 1140 picreg_t en_bridge_hi : 2; /* 4:3 */ 1141 picreg_t : 1; /* 2:2 */ 1142 picreg_t en_bridge_lo : 2; /* 1:0 */ 1143 } pic_p_arb_fld_s; 1144 } pic_p_arb_u_t; 1145 /* 1146 * Internal Ram Parity Error Register 1147 * 1148 * This register logs information about parity errors on internal ram access. 1149 */ 1150 typedef union pic_p_ram_perr_u { 1151 picreg_t pic_p_ram_perr_regval; 1152 struct { 1153 picreg_t : 6; /* 63:58 */ 1154 picreg_t ate_err_addr : 10; /* 57:48 */ 1155 picreg_t : 7; /* 47:41 */ 1156 picreg_t rd_resp_err_addr : 9; /* 40:32 */ 1157 picreg_t wrt_resp_err_addr : 8; /* 31:24 */ 1158 picreg_t : 2; /* 23:22 */ 1159 picreg_t ate_err : 1; /* 21:21 */ 1160 picreg_t rd_resp_err : 1; /* 20:20 */ 1161 picreg_t wrt_resp_err : 1; /* 19:19 */ 1162 picreg_t dbe_ate : 3; /* 18:16 */ 1163 picreg_t dbe_rd : 8; /* 15:8 */ 1164 picreg_t dbe_wrt : 8; /* 7:0 */ 1165 } pic_p_ram_perr_fld_s; 1166 } pic_p_ram_perr_u_t; 1167 /* 1168 * Time-out Register 1169 * 1170 * This register determines retry hold off and max retries allowed for PIO 1171 * accesses to PCI/PCI-X. 1172 */ 1173 typedef union pic_p_bus_timeout_u { 1174 picreg_t pic_p_bus_timeout_regval; 1175 struct { 1176 picreg_t : 32; /* 63:32 */ 1177 picreg_t : 11; /* 31:21 */ 1178 picreg_t pci_retry_hld : 5; /* 20:16 */ 1179 picreg_t : 6; /* 15:10 */ 1180 picreg_t pci_retry_cnt : 10; /* 9:0 */ 1181 } pic_p_bus_timeout_fld_s; 1182 } pic_p_bus_timeout_u_t; 1183 /* 1184 * PCI/PCI-X Type 1 Configuration Register 1185 * 1186 * This register is use during accesses to the PCI/PCI-X type 1 configuration 1187 * space. The bits in this register are used to supplement the address during 1188 * the configuration cycle to select the correct secondary bus and device. 1189 */ 1190 typedef union pic_type1_cfg_u { 1191 picreg_t pic_type1_cfg_regval; 1192 struct { 1193 picreg_t : 32; /* 63:32 */ 1194 picreg_t : 8; /* 31:24 */ 1195 picreg_t bus_num : 8; /* 23:16 */ 1196 picreg_t dev_num : 5; /* 15:11 */ 1197 picreg_t : 11; /* 10:0 */ 1198 } pic_type1_cfg_fld_s; 1199 } pic_type1_cfg_u_t; 1200 /* 1201 * PCI Bus Error Upper Address Holding Register 1202 * 1203 * This register holds the value of the upper address on the PCI Bus when an 1204 * error occurs. 1205 */ 1206 typedef union pic_p_pci_err_upper_u { 1207 picreg_t pic_p_pci_err_upper_regval; 1208 struct { 1209 picreg_t : 32; /* 63:32 */ 1210 picreg_t : 4; /* 31:28 */ 1211 picreg_t pci_xtalk_did : 4; /* 27:24 */ 1212 picreg_t : 2; /* 23:22 */ 1213 picreg_t pci_dac : 1; /* 21:21 */ 1214 picreg_t pci_dev_master : 1; /* 20:20 */ 1215 picreg_t pci_vdev : 1; /* 19:19 */ 1216 picreg_t pci_dev_num : 3; /* 18:16 */ 1217 picreg_t pci_uaddr_err : 16; /* 15:0 */ 1218 } pic_p_pci_err_upper_fld_s; 1219 } pic_p_pci_err_upper_u_t; 1220 /* 1221 * PCI Bus Error Lower Address Holding Register 1222 * 1223 * This register holds the value of the lower address on the PCI Bus when an 1224 * error occurs. 1225 */ 1226 typedef union pic_p_pci_err_lower_u { 1227 picreg_t pic_p_pci_err_lower_regval; 1228 struct { 1229 picreg_t : 4; /* 63:60 */ 1230 picreg_t pci_xtalk_did : 4; /* 59:56 */ 1231 picreg_t : 2; /* 55:54 */ 1232 picreg_t pci_dac : 1; /* 53:53 */ 1233 picreg_t pci_dev_master : 1; /* 52:52 */ 1234 picreg_t pci_vdev : 1; /* 51:51 */ 1235 picreg_t pci_dev_num : 3; /* 50:48 */ 1236 picreg_t pci_uaddr_err : 16; /* 47:32 */ 1237 picreg_t pci_laddr_err : 32; /* 31:0 */ 1238 } pic_p_pci_err_lower_fld_s; 1239 } pic_p_pci_err_lower_u_t; 1240 /* 1241 * PCI-X Error Address Register 1242 * 1243 * This register contains the address on the PCI-X bus when an error oc- 1244 * curred. 1245 */ 1246 typedef union pic_p_pcix_err_addr_u { 1247 picreg_t pic_p_pcix_err_addr_regval; 1248 struct { 1249 picreg_t pcix_err_addr : 64; /* 63:0 */ 1250 } pic_p_pcix_err_addr_fld_s; 1251 } pic_p_pcix_err_addr_u_t; 1252 /* 1253 * PCI-X Error Attribute Register 1254 * 1255 * This register contains the attribute data on the PCI-X bus when an error 1256 * occurred. 1257 */ 1258 typedef union pic_p_pcix_err_attr_u { 1259 picreg_t pic_p_pcix_err_attr_regval; 1260 struct { 1261 picreg_t : 16; /* 63:48 */ 1262 picreg_t bus_cmd : 4; /* 47:44 */ 1263 picreg_t byte_cnt : 12; /* 43:32 */ 1264 picreg_t : 1; /* 31:31 */ 1265 picreg_t ns : 1; /* 30:30 */ 1266 picreg_t ro : 1; /* 29:29 */ 1267 picreg_t tag : 5; /* 28:24 */ 1268 picreg_t bus_num : 8; /* 23:16 */ 1269 picreg_t dev_num : 5; /* 15:11 */ 1270 picreg_t fun_num : 3; /* 10:8 */ 1271 picreg_t l_byte_cnt : 8; /* 7:0 */ 1272 } pic_p_pcix_err_attr_fld_s; 1273 } pic_p_pcix_err_attr_u_t; 1274 /* 1275 * PCI-X Error Data Register 1276 * 1277 * This register contains the Data on the PCI-X bus when an error occurred. 1278 */ 1279 typedef union pic_p_pcix_err_data_u { 1280 picreg_t pic_p_pcix_err_data_regval; 1281 struct { 1282 picreg_t pcix_err_data : 64; /* 63:0 */ 1283 } pic_p_pcix_err_data_fld_s; 1284 } pic_p_pcix_err_data_u_t; 1285 /* 1286 * PCI-X Read Request Timeout Error Register 1287 * 1288 * This register contains a pointer into the PCI-X read data structure. 1289 */ 1290 typedef union pic_p_pcix_read_req_to_u { 1291 picreg_t pic_p_pcix_read_req_to_regval; 1292 struct { 1293 picreg_t : 55; /* 63:9 */ 1294 picreg_t rd_buff_loc : 5; /* 8:4 */ 1295 picreg_t rd_buff_struct : 4; /* 3:0 */ 1296 } pic_p_pcix_read_req_to_fld_s; 1297 } pic_p_pcix_read_req_to_u_t; 1298 /* 1299 * INT_STATUS Register 1300 * 1301 * This is the current interrupt status register which maintains the current 1302 * status of all the interrupting devices which generated a n interrupt. This 1303 * register is read only and all the bits are active high. A high bit at 1304 * INT_STATE means the corresponding INT_N pin has been asserted 1305 * (low). 1306 */ 1307 typedef union pic_p_int_status_u { 1308 picreg_t pic_p_int_status_regval; 1309 struct { 1310 picreg_t : 22; /* 63:42 */ 1311 picreg_t int_ram_perr : 1; /* 41:41 */ 1312 picreg_t bus_arb_broke : 1; /* 40:40 */ 1313 picreg_t pci_x_req_tout : 1; /* 39:39 */ 1314 picreg_t pci_x_tabort : 1; /* 38:38 */ 1315 picreg_t pci_x_perr : 1; /* 37:37 */ 1316 picreg_t pci_x_serr : 1; /* 36:36 */ 1317 picreg_t pci_x_mretry : 1; /* 35:35 */ 1318 picreg_t pci_x_mtout : 1; /* 34:34 */ 1319 picreg_t pci_x_da_parity : 1; /* 33:33 */ 1320 picreg_t pci_x_ad_parity : 1; /* 32:32 */ 1321 picreg_t : 1; /* 31:31 */ 1322 picreg_t pmu_page_fault : 1; /* 30:30 */ 1323 picreg_t unexpected_resp : 1; /* 29:29 */ 1324 picreg_t bad_xresp_packet : 1; /* 28:28 */ 1325 picreg_t bad_xreq_packet : 1; /* 27:27 */ 1326 picreg_t resp_xtalk_error : 1; /* 26:26 */ 1327 picreg_t req_xtalk_error : 1; /* 25:25 */ 1328 picreg_t invalid_access : 1; /* 24:24 */ 1329 picreg_t unsupported_xop : 1; /* 23:23 */ 1330 picreg_t xreq_fifo_oflow : 1; /* 22:22 */ 1331 picreg_t llp_rec_snerror : 1; /* 21:21 */ 1332 picreg_t llp_rec_cberror : 1; /* 20:20 */ 1333 picreg_t llp_rcty : 1; /* 19:19 */ 1334 picreg_t llp_tx_retry : 1; /* 18:18 */ 1335 picreg_t llp_tcty : 1; /* 17:17 */ 1336 picreg_t : 1; /* 16:16 */ 1337 picreg_t pci_abort : 1; /* 15:15 */ 1338 picreg_t pci_parity : 1; /* 14:14 */ 1339 picreg_t pci_serr : 1; /* 13:13 */ 1340 picreg_t pci_perr : 1; /* 12:12 */ 1341 picreg_t pci_master_tout : 1; /* 11:11 */ 1342 picreg_t pci_retry_cnt : 1; /* 10:10 */ 1343 picreg_t xread_req_tout : 1; /* 9:9 */ 1344 picreg_t : 1; /* 8:8 */ 1345 picreg_t int_state : 8; /* 7:0 */ 1346 } pic_p_int_status_fld_s; 1347 } pic_p_int_status_u_t; 1348 /* 1349 * Interrupt Enable Register 1350 * 1351 * This register enables the reporting of interrupt to the host. Each bit in this 1352 * register corresponds to the same bit in Interrupt Status register. All bits 1353 * are zero after reset. 1354 */ 1355 typedef union pic_p_int_enable_u { 1356 picreg_t pic_p_int_enable_regval; 1357 struct { 1358 picreg_t : 22; /* 63:42 */ 1359 picreg_t en_int_ram_perr : 1; /* 41:41 */ 1360 picreg_t en_bus_arb_broke : 1; /* 40:40 */ 1361 picreg_t en_pci_x_req_tout : 1; /* 39:39 */ 1362 picreg_t en_pci_x_tabort : 1; /* 38:38 */ 1363 picreg_t en_pci_x_perr : 1; /* 37:37 */ 1364 picreg_t en_pci_x_serr : 1; /* 36:36 */ 1365 picreg_t en_pci_x_mretry : 1; /* 35:35 */ 1366 picreg_t en_pci_x_mtout : 1; /* 34:34 */ 1367 picreg_t en_pci_x_da_parity : 1; /* 33:33 */ 1368 picreg_t en_pci_x_ad_parity : 1; /* 32:32 */ 1369 picreg_t : 1; /* 31:31 */ 1370 picreg_t en_pmu_page_fault : 1; /* 30:30 */ 1371 picreg_t en_unexpected_resp : 1; /* 29:29 */ 1372 picreg_t en_bad_xresp_packet : 1; /* 28:28 */ 1373 picreg_t en_bad_xreq_packet : 1; /* 27:27 */ 1374 picreg_t en_resp_xtalk_error : 1; /* 26:26 */ 1375 picreg_t en_req_xtalk_error : 1; /* 25:25 */ 1376 picreg_t en_invalid_access : 1; /* 24:24 */ 1377 picreg_t en_unsupported_xop : 1; /* 23:23 */ 1378 picreg_t en_xreq_fifo_oflow : 1; /* 22:22 */ 1379 picreg_t en_llp_rec_snerror : 1; /* 21:21 */ 1380 picreg_t en_llp_rec_cberror : 1; /* 20:20 */ 1381 picreg_t en_llp_rcty : 1; /* 19:19 */ 1382 picreg_t en_llp_tx_retry : 1; /* 18:18 */ 1383 picreg_t en_llp_tcty : 1; /* 17:17 */ 1384 picreg_t : 1; /* 16:16 */ 1385 picreg_t en_pci_abort : 1; /* 15:15 */ 1386 picreg_t en_pci_parity : 1; /* 14:14 */ 1387 picreg_t en_pci_serr : 1; /* 13:13 */ 1388 picreg_t en_pci_perr : 1; /* 12:12 */ 1389 picreg_t en_pci_master_tout : 1; /* 11:11 */ 1390 picreg_t en_pci_retry_cnt : 1; /* 10:10 */ 1391 picreg_t en_xread_req_tout : 1; /* 9:9 */ 1392 picreg_t : 1; /* 8:8 */ 1393 picreg_t en_int_state : 8; /* 7:0 */ 1394 } pic_p_int_enable_fld_s; 1395 } pic_p_int_enable_u_t; 1396 /* 1397 * Reset Interrupt Register 1398 * 1399 * A write of a "1" clears the bit and rearms the error registers. Writes also 1400 * clear the error view register. 1401 */ 1402 typedef union pic_p_int_rst_u { 1403 picreg_t pic_p_int_rst_regval; 1404 struct { 1405 picreg_t : 22; /* 63:42 */ 1406 picreg_t logv_int_ram_perr : 1; /* 41:41 */ 1407 picreg_t logv_bus_arb_broke : 1; /* 40:40 */ 1408 picreg_t logv_pci_x_req_tout : 1; /* 39:39 */ 1409 picreg_t logv_pci_x_tabort : 1; /* 38:38 */ 1410 picreg_t logv_pci_x_perr : 1; /* 37:37 */ 1411 picreg_t logv_pci_x_serr : 1; /* 36:36 */ 1412 picreg_t logv_pci_x_mretry : 1; /* 35:35 */ 1413 picreg_t logv_pci_x_mtout : 1; /* 34:34 */ 1414 picreg_t logv_pci_x_da_parity : 1; /* 33:33 */ 1415 picreg_t logv_pci_x_ad_parity : 1; /* 32:32 */ 1416 picreg_t : 1; /* 31:31 */ 1417 picreg_t logv_pmu_page_fault : 1; /* 30:30 */ 1418 picreg_t logv_unexpected_resp : 1; /* 29:29 */ 1419 picreg_t logv_bad_xresp_packet : 1; /* 28:28 */ 1420 picreg_t logv_bad_xreq_packet : 1; /* 27:27 */ 1421 picreg_t logv_resp_xtalk_error : 1; /* 26:26 */ 1422 picreg_t logv_req_xtalk_error : 1; /* 25:25 */ 1423 picreg_t logv_invalid_access : 1; /* 24:24 */ 1424 picreg_t logv_unsupported_xop : 1; /* 23:23 */ 1425 picreg_t logv_xreq_fifo_oflow : 1; /* 22:22 */ 1426 picreg_t logv_llp_rec_snerror : 1; /* 21:21 */ 1427 picreg_t logv_llp_rec_cberror : 1; /* 20:20 */ 1428 picreg_t logv_llp_rcty : 1; /* 19:19 */ 1429 picreg_t logv_llp_tx_retry : 1; /* 18:18 */ 1430 picreg_t logv_llp_tcty : 1; /* 17:17 */ 1431 picreg_t : 1; /* 16:16 */ 1432 picreg_t logv_pci_abort : 1; /* 15:15 */ 1433 picreg_t logv_pci_parity : 1; /* 14:14 */ 1434 picreg_t logv_pci_serr : 1; /* 13:13 */ 1435 picreg_t logv_pci_perr : 1; /* 12:12 */ 1436 picreg_t logv_pci_master_tout : 1; /* 11:11 */ 1437 picreg_t logv_pci_retry_cnt : 1; /* 10:10 */ 1438 picreg_t logv_xread_req_tout : 1; /* 9:9 */ 1439 picreg_t : 2; /* 8:7 */ 1440 picreg_t multi_clr : 1; /* 6:6 */ 1441 picreg_t : 6; /* 5:0 */ 1442 } pic_p_int_rst_fld_s; 1443 } pic_p_int_rst_u_t; 1444 1445 /* 1446 * Interrupt Mode Register 1447 * 1448 * This register defines the interrupting mode of the INT_N pins. 1449 */ 1450 typedef union pic_p_int_mode_u { 1451 picreg_t pic_p_int_mode_regval; 1452 struct { 1453 picreg_t : 32; /* 63:32 */ 1454 picreg_t : 24; /* 31:8 */ 1455 picreg_t en_clr_pkt : 8; /* 7:0 */ 1456 } pic_p_int_mode_fld_s; 1457 } pic_p_int_mode_u_t; 1458 /* 1459 * Interrupt Device Select Register 1460 * 1461 * This register associates interrupt pins with devices thus allowing buffer 1462 * management (flushing) when a device interrupt occurs. 1463 */ 1464 typedef union pic_p_int_device_u { 1465 picreg_t pic_p_int_device_regval; 1466 struct { 1467 picreg_t : 32; /* 63:32 */ 1468 picreg_t : 8; /* 31:24 */ 1469 picreg_t int7_dev : 3; /* 23:21 */ 1470 picreg_t int6_dev : 3; /* 20:18 */ 1471 picreg_t int5_dev : 3; /* 17:15 */ 1472 picreg_t int4_dev : 3; /* 14:12 */ 1473 picreg_t int3_dev : 3; /* 11:9 */ 1474 picreg_t int2_dev : 3; /* 8:6 */ 1475 picreg_t int1_dev : 3; /* 5:3 */ 1476 picreg_t int0_dev : 3; /* 2:0 */ 1477 } pic_p_int_device_fld_s; 1478 } pic_p_int_device_u_t; 1479 /* 1480 * Host Error Interrupt Field Register 1481 * 1482 * This register tells which bit location in the host's Interrupt Status register 1483 * to set or reset when any error condition happens. 1484 */ 1485 typedef union pic_p_int_host_err_u { 1486 picreg_t pic_p_int_host_err_regval; 1487 struct { 1488 picreg_t : 32; /* 63:32 */ 1489 picreg_t : 24; /* 31:8 */ 1490 picreg_t bridge_err_fld : 8; /* 7:0 */ 1491 } pic_p_int_host_err_fld_s; 1492 } pic_p_int_host_err_u_t; 1493 /* 1494 * Interrupt (x) Host Address Register 1495 * 1496 * This register allow different host address to be assigned to each interrupt 1497 * pin and the bit in the host. 1498 */ 1499 typedef union pic_p_int_addr_u { 1500 picreg_t pic_p_int_addr_regval; 1501 struct { 1502 picreg_t : 8; /* 63:56 */ 1503 picreg_t int_fld : 8; /* 55:48 */ 1504 picreg_t int_addr : 48; /* 47:0 */ 1505 } pic_p_int_addr_fld_s; 1506 } pic_p_int_addr_u_t; 1507 /* 1508 * Error Interrupt View Register 1509 * 1510 * This register contains the view of which interrupt occur even if they are 1511 * not currently enabled. The group clear is used to clear these bits just like 1512 * the interrupt status register bits. 1513 */ 1514 typedef union pic_p_err_int_view_u { 1515 picreg_t pic_p_err_int_view_regval; 1516 struct { 1517 picreg_t : 22; /* 63:42 */ 1518 picreg_t int_ram_perr : 1; /* 41:41 */ 1519 picreg_t bus_arb_broke : 1; /* 40:40 */ 1520 picreg_t pci_x_req_tout : 1; /* 39:39 */ 1521 picreg_t pci_x_tabort : 1; /* 38:38 */ 1522 picreg_t pci_x_perr : 1; /* 37:37 */ 1523 picreg_t pci_x_serr : 1; /* 36:36 */ 1524 picreg_t pci_x_mretry : 1; /* 35:35 */ 1525 picreg_t pci_x_mtout : 1; /* 34:34 */ 1526 picreg_t pci_x_da_parity : 1; /* 33:33 */ 1527 picreg_t pci_x_ad_parity : 1; /* 32:32 */ 1528 picreg_t : 1; /* 31:31 */ 1529 picreg_t pmu_page_fault : 1; /* 30:30 */ 1530 picreg_t unexpected_resp : 1; /* 29:29 */ 1531 picreg_t bad_xresp_packet : 1; /* 28:28 */ 1532 picreg_t bad_xreq_packet : 1; /* 27:27 */ 1533 picreg_t resp_xtalk_error : 1; /* 26:26 */ 1534 picreg_t req_xtalk_error : 1; /* 25:25 */ 1535 picreg_t invalid_access : 1; /* 24:24 */ 1536 picreg_t unsupported_xop : 1; /* 23:23 */ 1537 picreg_t xreq_fifo_oflow : 1; /* 22:22 */ 1538 picreg_t llp_rec_snerror : 1; /* 21:21 */ 1539 picreg_t llp_rec_cberror : 1; /* 20:20 */ 1540 picreg_t llp_rcty : 1; /* 19:19 */ 1541 picreg_t llp_tx_retry : 1; /* 18:18 */ 1542 picreg_t llp_tcty : 1; /* 17:17 */ 1543 picreg_t : 1; /* 16:16 */ 1544 picreg_t pci_abort : 1; /* 15:15 */ 1545 picreg_t pci_parity : 1; /* 14:14 */ 1546 picreg_t pci_serr : 1; /* 13:13 */ 1547 picreg_t pci_perr : 1; /* 12:12 */ 1548 picreg_t pci_master_tout : 1; /* 11:11 */ 1549 picreg_t pci_retry_cnt : 1; /* 10:10 */ 1550 picreg_t xread_req_tout : 1; /* 9:9 */ 1551 picreg_t : 9; /* 8:0 */ 1552 } pic_p_err_int_view_fld_s; 1553 } pic_p_err_int_view_u_t; 1554 1555 1556 /* 1557 * Multiple Interrupt Register 1558 * 1559 * This register indicates if any interrupt occurs more than once without be- 1560 * ing cleared. 1561 */ 1562 typedef union pic_p_mult_int_u { 1563 picreg_t pic_p_mult_int_regval; 1564 struct { 1565 picreg_t : 22; /* 63:42 */ 1566 picreg_t int_ram_perr : 1; /* 41:41 */ 1567 picreg_t bus_arb_broke : 1; /* 40:40 */ 1568 picreg_t pci_x_req_tout : 1; /* 39:39 */ 1569 picreg_t pci_x_tabort : 1; /* 38:38 */ 1570 picreg_t pci_x_perr : 1; /* 37:37 */ 1571 picreg_t pci_x_serr : 1; /* 36:36 */ 1572 picreg_t pci_x_mretry : 1; /* 35:35 */ 1573 picreg_t pci_x_mtout : 1; /* 34:34 */ 1574 picreg_t pci_x_da_parity : 1; /* 33:33 */ 1575 picreg_t pci_x_ad_parity : 1; /* 32:32 */ 1576 picreg_t : 1; /* 31:31 */ 1577 picreg_t pmu_page_fault : 1; /* 30:30 */ 1578 picreg_t unexpected_resp : 1; /* 29:29 */ 1579 picreg_t bad_xresp_packet : 1; /* 28:28 */ 1580 picreg_t bad_xreq_packet : 1; /* 27:27 */ 1581 picreg_t resp_xtalk_error : 1; /* 26:26 */ 1582 picreg_t req_xtalk_error : 1; /* 25:25 */ 1583 picreg_t invalid_access : 1; /* 24:24 */ 1584 picreg_t unsupported_xop : 1; /* 23:23 */ 1585 picreg_t xreq_fifo_oflow : 1; /* 22:22 */ 1586 picreg_t llp_rec_snerror : 1; /* 21:21 */ 1587 picreg_t llp_rec_cberror : 1; /* 20:20 */ 1588 picreg_t llp_rcty : 1; /* 19:19 */ 1589 picreg_t llp_tx_retry : 1; /* 18:18 */ 1590 picreg_t llp_tcty : 1; /* 17:17 */ 1591 picreg_t : 1; /* 16:16 */ 1592 picreg_t pci_abort : 1; /* 15:15 */ 1593 picreg_t pci_parity : 1; /* 14:14 */ 1594 picreg_t pci_serr : 1; /* 13:13 */ 1595 picreg_t pci_perr : 1; /* 12:12 */ 1596 picreg_t pci_master_tout : 1; /* 11:11 */ 1597 picreg_t pci_retry_cnt : 1; /* 10:10 */ 1598 picreg_t xread_req_tout : 1; /* 9:9 */ 1599 picreg_t : 1; /* 8:8 */ 1600 picreg_t int_state : 8; /* 7:0 */ 1601 } pic_p_mult_int_fld_s; 1602 } pic_p_mult_int_u_t; 1603 /* 1604 * Force Always Interrupt (x) Register 1605 * 1606 * A write to this data independent write only register will force a set inter- 1607 * rupt to occur as if the interrupt line had transitioned. If the interrupt line 1608 * is already active an addition set interrupt packet is set. All buffer flush op- 1609 * erations also occur on this operation. 1610 */ 1611 1612 1613 /* 1614 * Force Interrupt (x) Register 1615 * 1616 * A write to this data independent write only register in conjunction with 1617 * the assertion of the corresponding interrupt line will force a set interrupt 1618 * to occur as if the interrupt line had transitioned. The interrupt line must 1619 * be active for this operation to generate a set packet, otherwise the write 1620 * PIO is ignored. All buffer flush operations also occur when the set packet 1621 * is sent on this operation. 1622 */ 1623 1624 1625 /* 1626 * Device Registers 1627 * 1628 * The Device registers contain device specific and mapping information. 1629 */ 1630 typedef union pic_device_reg_u { 1631 picreg_t pic_device_reg_regval; 1632 struct { 1633 picreg_t : 32; /* 63:32 */ 1634 picreg_t : 2; /* 31:30 */ 1635 picreg_t en_virtual1 : 1; /* 29:29 */ 1636 picreg_t en_error_lock : 1; /* 28:28 */ 1637 picreg_t en_page_chk : 1; /* 27:27 */ 1638 picreg_t force_pci_par : 1; /* 26:26 */ 1639 picreg_t en_virtual0 : 1; /* 25:25 */ 1640 picreg_t : 1; /* 24:24 */ 1641 picreg_t dir_wrt_gen : 1; /* 23:23 */ 1642 picreg_t dev_size : 1; /* 22:22 */ 1643 picreg_t real_time : 1; /* 21:21 */ 1644 picreg_t : 1; /* 20:20 */ 1645 picreg_t swap_direct : 1; /* 19:19 */ 1646 picreg_t prefetch : 1; /* 18:18 */ 1647 picreg_t precise : 1; /* 17:17 */ 1648 picreg_t coherent : 1; /* 16:16 */ 1649 picreg_t barrier : 1; /* 15:15 */ 1650 picreg_t gbr : 1; /* 14:14 */ 1651 picreg_t dev_swap : 1; /* 13:13 */ 1652 picreg_t dev_io_mem : 1; /* 12:12 */ 1653 picreg_t dev_off : 12; /* 11:0 */ 1654 } pic_device_reg_fld_s; 1655 } pic_device_reg_u_t; 1656 /* 1657 * Device (x) Write Request Buffer Flush 1658 * 1659 * When read, this register will return a 0x00 after the write buffer associat- 1660 * ed with the device has been flushed. (PCI Only) 1661 */ 1662 1663 1664 /* 1665 * Even Device Read Response Buffer Register (PCI Only) 1666 * 1667 * This register is use to allocate the read response buffers for the even num- 1668 * bered devices. (0,2) 1669 */ 1670 typedef union pic_p_even_resp_u { 1671 picreg_t pic_p_even_resp_regval; 1672 struct { 1673 picreg_t : 32; /* 63:32 */ 1674 picreg_t buff_14_en : 1; /* 31:31 */ 1675 picreg_t buff_14_vdev : 2; /* 30:29 */ 1676 picreg_t buff_14_pdev : 1; /* 28:28 */ 1677 picreg_t buff_12_en : 1; /* 27:27 */ 1678 picreg_t buff_12_vdev : 2; /* 26:25 */ 1679 picreg_t buff_12_pdev : 1; /* 24:24 */ 1680 picreg_t buff_10_en : 1; /* 23:23 */ 1681 picreg_t buff_10_vdev : 2; /* 22:21 */ 1682 picreg_t buff_10_pdev : 1; /* 20:20 */ 1683 picreg_t buff_8_en : 1; /* 19:19 */ 1684 picreg_t buff_8_vdev : 2; /* 18:17 */ 1685 picreg_t buff_8_pdev : 1; /* 16:16 */ 1686 picreg_t buff_6_en : 1; /* 15:15 */ 1687 picreg_t buff_6_vdev : 2; /* 14:13 */ 1688 picreg_t buff_6_pdev : 1; /* 12:12 */ 1689 picreg_t buff_4_en : 1; /* 11:11 */ 1690 picreg_t buff_4_vdev : 2; /* 10:9 */ 1691 picreg_t buff_4_pdev : 1; /* 8:8 */ 1692 picreg_t buff_2_en : 1; /* 7:7 */ 1693 picreg_t buff_2_vdev : 2; /* 6:5 */ 1694 picreg_t buff_2_pdev : 1; /* 4:4 */ 1695 picreg_t buff_0_en : 1; /* 3:3 */ 1696 picreg_t buff_0_vdev : 2; /* 2:1 */ 1697 picreg_t buff_0_pdev : 1; /* 0:0 */ 1698 } pic_p_even_resp_fld_s; 1699 } pic_p_even_resp_u_t; 1700 /* 1701 * Odd Device Read Response Buffer Register (PCI Only) 1702 * 1703 * This register is use to allocate the read response buffers for the odd num- 1704 * bered devices. (1,3)) 1705 */ 1706 typedef union pic_p_odd_resp_u { 1707 picreg_t pic_p_odd_resp_regval; 1708 struct { 1709 picreg_t : 32; /* 63:32 */ 1710 picreg_t buff_15_en : 1; /* 31:31 */ 1711 picreg_t buff_15_vdev : 2; /* 30:29 */ 1712 picreg_t buff_15_pdev : 1; /* 28:28 */ 1713 picreg_t buff_13_en : 1; /* 27:27 */ 1714 picreg_t buff_13_vdev : 2; /* 26:25 */ 1715 picreg_t buff_13_pdev : 1; /* 24:24 */ 1716 picreg_t buff_11_en : 1; /* 23:23 */ 1717 picreg_t buff_11_vdev : 2; /* 22:21 */ 1718 picreg_t buff_11_pdev : 1; /* 20:20 */ 1719 picreg_t buff_9_en : 1; /* 19:19 */ 1720 picreg_t buff_9_vdev : 2; /* 18:17 */ 1721 picreg_t buff_9_pdev : 1; /* 16:16 */ 1722 picreg_t buff_7_en : 1; /* 15:15 */ 1723 picreg_t buff_7_vdev : 2; /* 14:13 */ 1724 picreg_t buff_7_pdev : 1; /* 12:12 */ 1725 picreg_t buff_5_en : 1; /* 11:11 */ 1726 picreg_t buff_5_vdev : 2; /* 10:9 */ 1727 picreg_t buff_5_pdev : 1; /* 8:8 */ 1728 picreg_t buff_3_en : 1; /* 7:7 */ 1729 picreg_t buff_3_vdev : 2; /* 6:5 */ 1730 picreg_t buff_3_pdev : 1; /* 4:4 */ 1731 picreg_t buff_1_en : 1; /* 3:3 */ 1732 picreg_t buff_1_vdev : 2; /* 2:1 */ 1733 picreg_t buff_1_pdev : 1; /* 0:0 */ 1734 } pic_p_odd_resp_fld_s; 1735 } pic_p_odd_resp_u_t; 1736 /* 1737 * Read Response Buffer Status Register (PCI Only) 1738 * 1739 * This read only register contains the current response buffer status. 1740 */ 1741 typedef union pic_p_resp_status_u { 1742 picreg_t pic_p_resp_status_regval; 1743 struct { 1744 picreg_t : 32; /* 63:32 */ 1745 picreg_t rrb_valid : 16; /* 31:16 */ 1746 picreg_t rrb_inuse : 16; /* 15:0 */ 1747 } pic_p_resp_status_fld_s; 1748 } pic_p_resp_status_u_t; 1749 /* 1750 * Read Response Buffer Clear Register (PCI Only) 1751 * 1752 * A write to this register clears the current contents of the buffer. 1753 */ 1754 typedef union pic_p_resp_clear_u { 1755 picreg_t pic_p_resp_clear_regval; 1756 struct { 1757 picreg_t : 32; /* 63:32 */ 1758 picreg_t : 16; /* 31:16 */ 1759 picreg_t rrb_clear : 16; /* 15:0 */ 1760 } pic_p_resp_clear_fld_s; 1761 } pic_p_resp_clear_u_t; 1762 /* 1763 * PCI Read Response Buffer (x) Upper Address Match 1764 * 1765 * The PCI Bridge read response buffer upper address register is a read only 1766 * register which contains the upper 16-bits of the address and status used to 1767 * select the buffer for a PCI transaction. 1768 */ 1769 typedef union pic_p_buf_upper_addr_match_u { 1770 picreg_t pic_p_buf_upper_addr_match_regval; 1771 struct { 1772 picreg_t : 32; /* 63:32 */ 1773 picreg_t filled : 1; /* 31:31 */ 1774 picreg_t armed : 1; /* 30:30 */ 1775 picreg_t flush : 1; /* 29:29 */ 1776 picreg_t xerr : 1; /* 28:28 */ 1777 picreg_t pkterr : 1; /* 27:27 */ 1778 picreg_t timeout : 1; /* 26:26 */ 1779 picreg_t prefetch : 1; /* 25:25 */ 1780 picreg_t precise : 1; /* 24:24 */ 1781 picreg_t dw_be : 8; /* 23:16 */ 1782 picreg_t upp_addr : 16; /* 15:0 */ 1783 } pic_p_buf_upper_addr_match_fld_s; 1784 } pic_p_buf_upper_addr_match_u_t; 1785 /* 1786 * PCI Read Response Buffer (x) Lower Address Match 1787 * 1788 * The PCI Bridge read response buffer lower address Match register is a 1789 * read only register which contains the address and status used to select the 1790 * buffer for a PCI transaction. 1791 */ 1792 typedef union pic_p_buf_lower_addr_match_u { 1793 picreg_t pic_p_buf_lower_addr_match_regval; 1794 struct { 1795 picreg_t filled : 1; /* 63:63 */ 1796 picreg_t armed : 1; /* 62:62 */ 1797 picreg_t flush : 1; /* 61:61 */ 1798 picreg_t xerr : 1; /* 60:60 */ 1799 picreg_t pkterr : 1; /* 59:59 */ 1800 picreg_t timeout : 1; /* 58:58 */ 1801 picreg_t prefetch : 1; /* 57:57 */ 1802 picreg_t precise : 1; /* 56:56 */ 1803 picreg_t dw_be : 8; /* 55:48 */ 1804 picreg_t upp_addr : 16; /* 47:32 */ 1805 picreg_t low_addr : 32; /* 31:0 */ 1806 } pic_p_buf_lower_addr_match_fld_s; 1807 } pic_p_buf_lower_addr_match_u_t; 1808 /* 1809 * PCI Buffer (x) Flush Count with Data Touch Register 1810 * 1811 * This counter is incremented each time the corresponding response buffer 1812 * is flushed after at least a single data element in the buffer is used. A word 1813 * write to this address clears the count. 1814 */ 1815 typedef union pic_flush_w_touch_u { 1816 picreg_t pic_flush_w_touch_regval; 1817 struct { 1818 picreg_t : 32; /* 63:32 */ 1819 picreg_t : 16; /* 31:16 */ 1820 picreg_t touch_cnt : 16; /* 15:0 */ 1821 } pic_flush_w_touch_fld_s; 1822 } pic_flush_w_touch_u_t; 1823 /* 1824 * PCI Buffer (x) Flush Count w/o Data Touch Register 1825 * 1826 * This counter is incremented each time the corresponding response buffer 1827 * is flushed without any data element in the buffer being used. A word 1828 * write to this address clears the count. 1829 */ 1830 typedef union pic_flush_wo_touch_u { 1831 picreg_t pic_flush_wo_touch_regval; 1832 struct { 1833 picreg_t : 32; /* 63:32 */ 1834 picreg_t : 16; /* 31:16 */ 1835 picreg_t notouch_cnt : 16; /* 15:0 */ 1836 } pic_flush_wo_touch_fld_s; 1837 } pic_flush_wo_touch_u_t; 1838 /* 1839 * PCI Buffer (x) Request in Flight Count Register 1840 * 1841 * This counter is incremented on each bus clock while the request is in- 1842 * flight. A word write to this address clears the count. ] 1843 */ 1844 typedef union pic_inflight_u { 1845 picreg_t pic_inflight_regval; 1846 struct { 1847 picreg_t : 32; /* 63:32 */ 1848 picreg_t : 16; /* 31:16 */ 1849 picreg_t inflight_cnt : 16; /* 15:0 */ 1850 } pic_inflight_fld_s; 1851 } pic_inflight_u_t; 1852 /* 1853 * PCI Buffer (x) Prefetch Request Count Register 1854 * 1855 * This counter is incremented each time the request using this buffer was 1856 * generated from the prefetcher. A word write to this address clears the 1857 * count. 1858 */ 1859 typedef union pic_prefetch_u { 1860 picreg_t pic_prefetch_regval; 1861 struct { 1862 picreg_t : 32; /* 63:32 */ 1863 picreg_t : 16; /* 31:16 */ 1864 picreg_t prefetch_cnt : 16; /* 15:0 */ 1865 } pic_prefetch_fld_s; 1866 } pic_prefetch_u_t; 1867 /* 1868 * PCI Buffer (x) Total PCI Retry Count Register 1869 * 1870 * This counter is incremented each time a PCI bus retry occurs and the ad- 1871 * dress matches the tag for the selected buffer. The buffer must also has this 1872 * request in-flight. A word write to this address clears the count. 1873 */ 1874 typedef union pic_total_pci_retry_u { 1875 picreg_t pic_total_pci_retry_regval; 1876 struct { 1877 picreg_t : 32; /* 63:32 */ 1878 picreg_t : 16; /* 31:16 */ 1879 picreg_t retry_cnt : 16; /* 15:0 */ 1880 } pic_total_pci_retry_fld_s; 1881 } pic_total_pci_retry_u_t; 1882 /* 1883 * PCI Buffer (x) Max PCI Retry Count Register 1884 * 1885 * This counter is contains the maximum retry count for a single request 1886 * which was in-flight for this buffer. A word write to this address clears the 1887 * count. 1888 */ 1889 typedef union pic_max_pci_retry_u { 1890 picreg_t pic_max_pci_retry_regval; 1891 struct { 1892 picreg_t : 32; /* 63:32 */ 1893 picreg_t : 16; /* 31:16 */ 1894 picreg_t max_retry_cnt : 16; /* 15:0 */ 1895 } pic_max_pci_retry_fld_s; 1896 } pic_max_pci_retry_u_t; 1897 /* 1898 * PCI Buffer (x) Max Latency Count Register 1899 * 1900 * This counter is contains the maximum count (in bus clocks) for a single 1901 * request which was in-flight for this buffer. A word write to this address 1902 * clears the count. 1903 */ 1904 typedef union pic_max_latency_u { 1905 picreg_t pic_max_latency_regval; 1906 struct { 1907 picreg_t : 32; /* 63:32 */ 1908 picreg_t : 16; /* 31:16 */ 1909 picreg_t max_latency_cnt : 16; /* 15:0 */ 1910 } pic_max_latency_fld_s; 1911 } pic_max_latency_u_t; 1912 /* 1913 * PCI Buffer (x) Clear All Register 1914 * 1915 * Any access to this register clears all the count values for the (x) registers. 1916 */ 1917 1918 1919 /* 1920 * PCI-X Registers 1921 * 1922 * This register contains the address in the read buffer structure. There are 1923 * 16 read buffer structures. 1924 */ 1925 typedef union pic_rd_buf_addr_u { 1926 picreg_t pic_rd_buf_addr_regval; 1927 struct { 1928 picreg_t pcix_err_addr : 64; /* 63:0 */ 1929 } pic_rd_buf_addr_fld_s; 1930 } pic_rd_buf_addr_u_t; 1931 /* 1932 * PCI-X Read Buffer (x) Attribute Register 1933 * 1934 * This register contains the attribute data in the read buffer structure. There 1935 * are 16 read buffer structures. 1936 */ 1937 typedef union pic_px_read_buf_attr_u { 1938 picreg_t pic_px_read_buf_attr_regval; 1939 struct { 1940 picreg_t : 16; /* 63:48 */ 1941 picreg_t bus_cmd : 4; /* 47:44 */ 1942 picreg_t byte_cnt : 12; /* 43:32 */ 1943 picreg_t entry_valid : 1; /* 31:31 */ 1944 picreg_t ns : 1; /* 30:30 */ 1945 picreg_t ro : 1; /* 29:29 */ 1946 picreg_t tag : 5; /* 28:24 */ 1947 picreg_t bus_num : 8; /* 23:16 */ 1948 picreg_t dev_num : 5; /* 15:11 */ 1949 picreg_t fun_num : 3; /* 10:8 */ 1950 picreg_t : 2; /* 7:6 */ 1951 picreg_t f_buffer_index : 6; /* 5:0 */ 1952 } pic_px_read_buf_attr_fld_s; 1953 } pic_px_read_buf_attr_u_t; 1954 /* 1955 * PCI-X Write Buffer (x) Address Register 1956 * 1957 * This register contains the address in the write buffer structure. There are 1958 * 8 write buffer structures. 1959 */ 1960 typedef union pic_px_write_buf_addr_u { 1961 picreg_t pic_px_write_buf_addr_regval; 1962 struct { 1963 picreg_t pcix_err_addr : 64; /* 63:0 */ 1964 } pic_px_write_buf_addr_fld_s; 1965 } pic_px_write_buf_addr_u_t; 1966 /* 1967 * PCI-X Write Buffer (x) Attribute Register 1968 * 1969 * This register contains the attribute data in the write buffer structure. 1970 * There are 8 write buffer structures. 1971 */ 1972 typedef union pic_px_write_buf_attr_u { 1973 picreg_t pic_px_write_buf_attr_regval; 1974 struct { 1975 picreg_t : 16; /* 63:48 */ 1976 picreg_t bus_cmd : 4; /* 47:44 */ 1977 picreg_t byte_cnt : 12; /* 43:32 */ 1978 picreg_t entry_valid : 1; /* 31:31 */ 1979 picreg_t ns : 1; /* 30:30 */ 1980 picreg_t ro : 1; /* 29:29 */ 1981 picreg_t tag : 5; /* 28:24 */ 1982 picreg_t bus_num : 8; /* 23:16 */ 1983 picreg_t dev_num : 5; /* 15:11 */ 1984 picreg_t fun_num : 3; /* 10:8 */ 1985 picreg_t : 2; /* 7:6 */ 1986 picreg_t f_buffer_index : 6; /* 5:0 */ 1987 } pic_px_write_buf_attr_fld_s; 1988 } pic_px_write_buf_attr_u_t; 1989 /* 1990 * PCI-X Write Buffer (x) Valid Register 1991 * 1992 * This register contains the valid or inuse cache lines for this buffer struc- 1993 * ture. 1994 */ 1995 typedef union pic_px_write_buf_valid_u { 1996 picreg_t pic_px_write_buf_valid_regval; 1997 struct { 1998 picreg_t : 32; /* 63:32 */ 1999 picreg_t wrt_valid_buff : 32; /* 31:0 */ 2000 } pic_px_write_buf_valid_fld_s; 2001 } pic_px_write_buf_valid_u_t; 2002 2003 #endif /* __ASSEMBLY__ */ 2004 #endif /* _ASM_SN_PCI_PIC_H */ 2005