1 /* $Id$ 2 * 3 * This file is subject to the terms and conditions of the GNU General Public 4 * License. See the file "COPYING" in the main directory of this archive 5 * for more details. 6 * 7 * Copyright (C) 1992-1997,2000-2003 Silicon Graphics, Inc. All Rights Reserved. 8 */ 9 10 #ifndef _ASM_SN_KSYS_L1_H 11 #define _ASM_SN_KSYS_L1_H 12 13 #include <linux/config.h> 14 #include <asm/sn/vector.h> 15 #include <asm/sn/addrs.h> 16 #include <asm/atomic.h> 17 #include <asm/sn/sv.h> 18 19 /* L1 Target Addresses */ 20 /* 21 * L1 commands and responses use source/target addresses that are 22 * 32 bits long. These are broken up into multiple bitfields that 23 * specify the type of the target controller (could actually be L2 24 * L3, not just L1), the rack and bay of the target, and the task 25 * id (L1 functionality is divided into several independent "tasks" 26 * that can each receive command requests and transmit responses) 27 */ 28 #define L1_ADDR_TYPE_L1 0x00 /* L1 system controller */ 29 #define L1_ADDR_TYPE_L2 0x01 /* L2 system controller */ 30 #define L1_ADDR_TYPE_L3 0x02 /* L3 system controller */ 31 #define L1_ADDR_TYPE_CBRICK 0x03 /* attached C brick */ 32 #define L1_ADDR_TYPE_IOBRICK 0x04 /* attached I/O brick */ 33 #define L1_ADDR_TASK_SHFT 0 34 #define L1_ADDR_TASK_MASK 0x0000001F 35 #define L1_ADDR_TASK_INVALID 0x00 /* invalid task */ 36 #define L1_ADDR_TASK_IROUTER 0x01 /* iRouter */ 37 #define L1_ADDR_TASK_SYS_MGMT 0x02 /* system management port */ 38 #define L1_ADDR_TASK_CMD 0x03 /* command interpreter */ 39 #define L1_ADDR_TASK_ENV 0x04 /* environmental monitor */ 40 #define L1_ADDR_TASK_BEDROCK 0x05 /* bedrock */ 41 #define L1_ADDR_TASK_GENERAL 0x06 /* general requests */ 42 43 #define L1_ADDR_LOCAL \ 44 (L1_ADDR_TYPE_L1 << L1_ADDR_TYPE_SHFT) | \ 45 (L1_ADDR_RACK_LOCAL << L1_ADDR_RACK_SHFT) | \ 46 (L1_ADDR_BAY_LOCAL << L1_ADDR_BAY_SHFT) 47 48 #define L1_ADDR_LOCALIO \ 49 (L1_ADDR_TYPE_IOBRICK << L1_ADDR_TYPE_SHFT) | \ 50 (L1_ADDR_RACK_LOCAL << L1_ADDR_RACK_SHFT) | \ 51 (L1_ADDR_BAY_LOCAL << L1_ADDR_BAY_SHFT) 52 53 #define L1_ADDR_LOCAL_SHFT L1_ADDR_BAY_SHFT 54 55 /* response argument types */ 56 #define L1_ARG_INT 0x00 /* 4-byte integer (big-endian) */ 57 #define L1_ARG_ASCII 0x01 /* null-terminated ASCII string */ 58 #define L1_ARG_UNKNOWN 0x80 /* unknown data type. The low 59 * 7 bits will contain the data 60 * length. */ 61 62 /* response codes */ 63 #define L1_RESP_OK 0 /* no problems encountered */ 64 #define L1_RESP_IROUTER (- 1) /* iRouter error */ 65 #define L1_RESP_ARGC (-100) /* arg count mismatch */ 66 #define L1_RESP_REQC (-101) /* bad request code */ 67 #define L1_RESP_NAVAIL (-104) /* requested data not available */ 68 #define L1_RESP_ARGVAL (-105) /* arg value out of range */ 69 #define L1_RESP_INVAL (-107) /* requested data invalid */ 70 71 /* L1 general requests */ 72 73 /* request codes */ 74 #define L1_REQ_RDBG 0x0001 /* read debug switches */ 75 #define L1_REQ_RRACK 0x0002 /* read brick rack & bay */ 76 #define L1_REQ_RRBT 0x0003 /* read brick rack, bay & type */ 77 #define L1_REQ_SER_NUM 0x0004 /* read brick serial number */ 78 #define L1_REQ_FW_REV 0x0005 /* read L1 firmware revision */ 79 #define L1_REQ_EEPROM 0x0006 /* read EEPROM info */ 80 #define L1_REQ_EEPROM_FMT 0x0007 /* get EEPROM data format & size */ 81 #define L1_REQ_SYS_SERIAL 0x0008 /* read system serial number */ 82 #define L1_REQ_PARTITION_GET 0x0009 /* read partition id */ 83 #define L1_REQ_PORTSPEED 0x000a /* get ioport speed */ 84 85 #define L1_REQ_CONS_SUBCH 0x1002 /* select this node's console 86 subchannel */ 87 #define L1_REQ_CONS_NODE 0x1003 /* volunteer to be the master 88 (console-hosting) node */ 89 #define L1_REQ_DISP1 0x1004 /* write line 1 of L1 display */ 90 #define L1_REQ_DISP2 0x1005 /* write line 2 of L1 display */ 91 #define L1_REQ_PARTITION_SET 0x1006 /* set partition id */ 92 #define L1_REQ_EVENT_SUBCH 0x1007 /* set the subchannel for system 93 controller event transmission */ 94 95 #define L1_REQ_RESET 0x2000 /* request a full system reset */ 96 #define L1_REQ_PCI_UP 0x2001 /* power up pci slot or bus */ 97 #define L1_REQ_PCI_DOWN 0x2002 /* power down pci slot or bus */ 98 #define L1_REQ_PCI_RESET 0x2003 /* reset pci bus or slot */ 99 100 /* L1 command interpreter requests */ 101 102 /* request codes */ 103 #define L1_REQ_EXEC_CMD 0x0000 /* interpret and execute an ASCII 104 command string */ 105 106 /* brick type response codes */ 107 #define L1_BRICKTYPE_PX 0x23 /* # */ 108 #define L1_BRICKTYPE_PE 0x25 /* % */ 109 #define L1_BRICKTYPE_N_p0 0x26 /* & */ 110 #define L1_BRICKTYPE_IP45 0x34 /* 4 */ 111 #define L1_BRICKTYPE_IP41 0x35 /* 5 */ 112 #define L1_BRICKTYPE_TWISTER 0x36 /* 6 */ /* IP53 & ROUTER */ 113 #define L1_BRICKTYPE_IX 0x3d /* = */ 114 #define L1_BRICKTYPE_IP34 0x61 /* a */ 115 #define L1_BRICKTYPE_C 0x63 /* c */ 116 #define L1_BRICKTYPE_I 0x69 /* i */ 117 #define L1_BRICKTYPE_N 0x6e /* n */ 118 #define L1_BRICKTYPE_OPUS 0x6f /* o */ 119 #define L1_BRICKTYPE_P 0x70 /* p */ 120 #define L1_BRICKTYPE_R 0x72 /* r */ 121 #define L1_BRICKTYPE_CHI_CG 0x76 /* v */ 122 #define L1_BRICKTYPE_X 0x78 /* x */ 123 #define L1_BRICKTYPE_X2 0x79 /* y */ 124 125 /* EEPROM codes (for the "read EEPROM" request) */ 126 /* c brick */ 127 #define L1_EEP_NODE 0x00 /* node board */ 128 #define L1_EEP_PIMM0 0x01 129 #define L1_EEP_PIMM(x) (L1_EEP_PIMM0+(x)) 130 #define L1_EEP_DIMM0 0x03 131 #define L1_EEP_DIMM(x) (L1_EEP_DIMM0+(x)) 132 133 /* other brick types */ 134 #define L1_EEP_POWER 0x00 /* power board */ 135 #define L1_EEP_LOGIC 0x01 /* logic board */ 136 137 /* info area types */ 138 #define L1_EEP_CHASSIS 1 /* chassis info area */ 139 #define L1_EEP_BOARD 2 /* board info area */ 140 #define L1_EEP_IUSE 3 /* internal use area */ 141 #define L1_EEP_SPD 4 /* serial presence detect record */ 142 143 typedef uint32_t l1addr_t; 144 145 #define L1_BUILD_ADDR(addr,at,r,s,t) \ 146 (*(l1addr_t *)(addr) = ((l1addr_t)(at) << L1_ADDR_TYPE_SHFT) | \ 147 ((l1addr_t)(r) << L1_ADDR_RACK_SHFT) | \ 148 ((l1addr_t)(s) << L1_ADDR_BAY_SHFT) | \ 149 ((l1addr_t)(t) << L1_ADDR_TASK_SHFT)) 150 151 #define L1_ADDRESS_TO_TASK(addr,trb,tsk) \ 152 (*(l1addr_t *)(addr) = (l1addr_t)(trb) | \ 153 ((l1addr_t)(tsk) << L1_ADDR_TASK_SHFT)) 154 155 #define L1_DISPLAY_LINE_LENGTH 12 /* L1 display characters/line */ 156 157 #ifdef L1_DISP_2LINES 158 #define L1_DISPLAY_LINES 2 /* number of L1 display lines */ 159 #else 160 #define L1_DISPLAY_LINES 1 /* number of L1 display lines available 161 * to system software */ 162 #endif 163 164 #define bzero(d, n) memset((d), 0, (n)) 165 166 int elsc_display_line(nasid_t nasid, char *line, int lnum); 167 int iobrick_rack_bay_type_get( nasid_t nasid, uint *rack, 168 uint *bay, uint *brick_type ); 169 int iobrick_module_get( nasid_t nasid ); 170 171 172 #endif /* _ASM_SN_KSYS_L1_H */ 173