1 /* 2 * File: mca_asm.h 3 * 4 * Copyright (C) 1999 Silicon Graphics, Inc. 5 * Copyright (C) Vijay Chander (vijay@engr.sgi.com) 6 * Copyright (C) Srinivasa Thirumalachar <sprasad@engr.sgi.com> 7 * Copyright (C) 2000 Hewlett-Packard Co. 8 * Copyright (C) 2000 David Mosberger-Tang <davidm@hpl.hp.com> 9 * Copyright (C) 2002 Intel Corp. 10 * Copyright (C) 2002 Jenna Hall <jenna.s.hall@intel.com> 11 */ 12 #ifndef _ASM_IA64_MCA_ASM_H 13 #define _ASM_IA64_MCA_ASM_H 14 15 #define PSR_IC 13 16 #define PSR_I 14 17 #define PSR_DT 17 18 #define PSR_RT 27 19 #define PSR_MC 35 20 #define PSR_IT 36 21 #define PSR_BN 44 22 23 /* 24 * This macro converts a instruction virtual address to a physical address 25 * Right now for simulation purposes the virtual addresses are 26 * direct mapped to physical addresses. 27 * 1. Lop off bits 61 thru 63 in the virtual address 28 */ 29 #define INST_VA_TO_PA(addr) \ 30 dep addr = 0, addr, 61, 3 31 /* 32 * This macro converts a data virtual address to a physical address 33 * Right now for simulation purposes the virtual addresses are 34 * direct mapped to physical addresses. 35 * 1. Lop off bits 61 thru 63 in the virtual address 36 */ 37 #define DATA_VA_TO_PA(addr) \ 38 dep addr = 0, addr, 61, 3 39 /* 40 * This macro converts a data physical address to a virtual address 41 * Right now for simulation purposes the virtual addresses are 42 * direct mapped to physical addresses. 43 * 1. Put 0x7 in bits 61 thru 63. 44 */ 45 #define DATA_PA_TO_VA(addr,temp) \ 46 mov temp = 0x7 ;; \ 47 dep addr = temp, addr, 61, 3 48 49 /* 50 * This macro jumps to the instruction at the given virtual address 51 * and starts execution in physical mode with all the address 52 * translations turned off. 53 * 1. Save the current psr 54 * 2. Make sure that all the upper 32 bits are off 55 * 56 * 3. Clear the interrupt enable and interrupt state collection bits 57 * in the psr before updating the ipsr and iip. 58 * 59 * 4. Turn off the instruction, data and rse translation bits of the psr 60 * and store the new value into ipsr 61 * Also make sure that the interrupts are disabled. 62 * Ensure that we are in little endian mode. 63 * [psr.{rt, it, dt, i, be} = 0] 64 * 65 * 5. Get the physical address corresponding to the virtual address 66 * of the next instruction bundle and put it in iip. 67 * (Using magic numbers 24 and 40 in the deposint instruction since 68 * the IA64_SDK code directly maps to lower 24bits as physical address 69 * from a virtual address). 70 * 71 * 6. Do an rfi to move the values from ipsr to psr and iip to ip. 72 */ 73 #define PHYSICAL_MODE_ENTER(temp1, temp2, start_addr, old_psr) \ 74 mov old_psr = psr; \ 75 ;; \ 76 dep old_psr = 0, old_psr, 32, 32; \ 77 \ 78 mov ar.rsc = 0 ; \ 79 ;; \ 80 srlz.d; \ 81 mov temp2 = ar.bspstore; \ 82 ;; \ 83 DATA_VA_TO_PA(temp2); \ 84 ;; \ 85 mov temp1 = ar.rnat; \ 86 ;; \ 87 mov ar.bspstore = temp2; \ 88 ;; \ 89 mov ar.rnat = temp1; \ 90 mov temp1 = psr; \ 91 mov temp2 = psr; \ 92 ;; \ 93 \ 94 dep temp2 = 0, temp2, PSR_IC, 2; \ 95 ;; \ 96 mov psr.l = temp2; \ 97 ;; \ 98 srlz.d; \ 99 dep temp1 = 0, temp1, 32, 32; \ 100 ;; \ 101 dep temp1 = 0, temp1, PSR_IT, 1; \ 102 ;; \ 103 dep temp1 = 0, temp1, PSR_DT, 1; \ 104 ;; \ 105 dep temp1 = 0, temp1, PSR_RT, 1; \ 106 ;; \ 107 dep temp1 = 0, temp1, PSR_I, 1; \ 108 ;; \ 109 dep temp1 = 0, temp1, PSR_IC, 1; \ 110 ;; \ 111 dep temp1 = -1, temp1, PSR_MC, 1; \ 112 ;; \ 113 movl temp2 = start_addr; \ 114 mov cr.ipsr = temp1; \ 115 ;; \ 116 INST_VA_TO_PA(temp2); \ 117 ;; \ 118 mov cr.iip = temp2; \ 119 mov cr.ifs = r0; \ 120 DATA_VA_TO_PA(sp); \ 121 DATA_VA_TO_PA(gp); \ 122 ;; \ 123 srlz.i; \ 124 ;; \ 125 nop 1; \ 126 nop 2; \ 127 nop 1; \ 128 nop 2; \ 129 rfi; \ 130 ;; 131 132 /* 133 * This macro jumps to the instruction at the given virtual address 134 * and starts execution in virtual mode with all the address 135 * translations turned on. 136 * 1. Get the old saved psr 137 * 138 * 2. Clear the interrupt state collection bit in the current psr. 139 * 140 * 3. Set the instruction translation bit back in the old psr 141 * Note we have to do this since we are right now saving only the 142 * lower 32-bits of old psr.(Also the old psr has the data and 143 * rse translation bits on) 144 * 145 * 4. Set ipsr to this old_psr with "it" bit set and "bn" = 1. 146 * 147 * 5. Reset the current thread pointer (r13). 148 * 149 * 6. Set iip to the virtual address of the next instruction bundle. 150 * 151 * 7. Do an rfi to move ipsr to psr and iip to ip. 152 */ 153 154 #define VIRTUAL_MODE_ENTER(temp1, temp2, start_addr, old_psr) \ 155 mov temp2 = psr; \ 156 ;; \ 157 mov old_psr = temp2; \ 158 ;; \ 159 dep temp2 = 0, temp2, PSR_IC, 2; \ 160 ;; \ 161 mov psr.l = temp2; \ 162 mov ar.rsc = 0; \ 163 ;; \ 164 srlz.d; \ 165 mov r13 = ar.k6; \ 166 ;; \ 167 DATA_PA_TO_VA(r13,temp1); \ 168 ;; \ 169 mov temp2 = ar.bspstore; \ 170 ;; \ 171 DATA_PA_TO_VA(temp2,temp1); \ 172 ;; \ 173 mov temp1 = ar.rnat; \ 174 ;; \ 175 mov ar.bspstore = temp2; \ 176 ;; \ 177 mov ar.rnat = temp1; \ 178 ;; \ 179 mov temp1 = old_psr; \ 180 ;; \ 181 mov temp2 = 1; \ 182 ;; \ 183 dep temp1 = temp2, temp1, PSR_IC, 1; \ 184 ;; \ 185 dep temp1 = temp2, temp1, PSR_IT, 1; \ 186 ;; \ 187 dep temp1 = temp2, temp1, PSR_DT, 1; \ 188 ;; \ 189 dep temp1 = temp2, temp1, PSR_RT, 1; \ 190 ;; \ 191 dep temp1 = temp2, temp1, PSR_BN, 1; \ 192 ;; \ 193 \ 194 mov cr.ipsr = temp1; \ 195 movl temp2 = start_addr; \ 196 ;; \ 197 mov cr.iip = temp2; \ 198 ;; \ 199 DATA_PA_TO_VA(sp, temp1); \ 200 DATA_PA_TO_VA(gp, temp2); \ 201 srlz.i; \ 202 ;; \ 203 nop 1; \ 204 nop 2; \ 205 nop 1; \ 206 rfi \ 207 ;; 208 209 /* 210 * The following offsets capture the order in which the 211 * RSE related registers from the old context are 212 * saved onto the new stack frame. 213 * 214 * +-----------------------+ 215 * |NDIRTY_WORDS | 216 * | [BSP - BSPSTORE]| 217 * +-----------------------+ 218 * | RNAT | 219 * +-----------------------+ 220 * | BSPSTORE | 221 * +-----------------------+ 222 * | IFS | 223 * +-----------------------+ 224 * | PFS | 225 * +-----------------------+ 226 * | RSC | 227 * +-----------------------+ <-------- Bottom of new stack frame 228 */ 229 #define rse_rsc_offset 0 230 #define rse_pfs_offset (rse_rsc_offset+0x08) 231 #define rse_ifs_offset (rse_pfs_offset+0x08) 232 #define rse_bspstore_offset (rse_ifs_offset+0x08) 233 #define rse_rnat_offset (rse_bspstore_offset+0x08) 234 #define rse_ndirty_words_offset (rse_rnat_offset+0x08) 235 236 /* 237 * rse_switch_context 238 * 239 * 1. Save old RSC onto the new stack frame 240 * 2. Save PFS onto new stack frame 241 * 3. Cover the old frame and start a new frame. 242 * 4. Save IFS onto new stack frame 243 * 5. Save the old BSPSTORE on the new stack frame 244 * 6. Save the old RNAT on the new stack frame 245 * 7. Write BSPSTORE with the new backing store pointer 246 * 8. Read and save the new BSP to calculate the #dirty registers 247 * NOTE: Look at section 6.11 in Intel IA-64 Architecture Software Developer's 248 * Manual, Volume 2, System Architecture. 249 */ 250 #define rse_switch_context(temp,p_stackframe,p_bspstore) \ 251 ;; \ 252 mov temp=ar.rsc;; \ 253 st8 [p_stackframe]=temp,8;; \ 254 mov temp=ar.pfs;; \ 255 st8 [p_stackframe]=temp,8; \ 256 cover ;; \ 257 mov temp=cr.ifs;; \ 258 st8 [p_stackframe]=temp,8;; \ 259 mov temp=ar.bspstore;; \ 260 st8 [p_stackframe]=temp,8;; \ 261 mov temp=ar.rnat;; \ 262 st8 [p_stackframe]=temp,8; \ 263 mov ar.bspstore=p_bspstore;; \ 264 mov temp=ar.bsp;; \ 265 sub temp=temp,p_bspstore;; \ 266 st8 [p_stackframe]=temp,8;; 267 268 /* 269 * rse_return_context 270 * 1. Allocate a zero-sized frame 271 * 2. Store the number of dirty registers RSC.loadrs field 272 * 3. Issue a loadrs to insure that any registers from the interrupted 273 * context which were saved on the new stack frame have been loaded 274 * back into the stacked registers 275 * 4. Restore BSPSTORE 276 * 5. Restore RNAT 277 * 6. Restore PFS 278 * 7. Restore IFS 279 * 8. Restore RSC 280 * 9. Issue an RFI 281 */ 282 #define rse_return_context(psr_mask_reg,temp,p_stackframe) \ 283 ;; \ 284 alloc temp=ar.pfs,0,0,0,0; \ 285 add p_stackframe=rse_ndirty_words_offset,p_stackframe;; \ 286 ld8 temp=[p_stackframe];; \ 287 shl temp=temp,16;; \ 288 mov ar.rsc=temp;; \ 289 loadrs;; \ 290 add p_stackframe=-rse_ndirty_words_offset+rse_bspstore_offset,p_stackframe;;\ 291 ld8 temp=[p_stackframe];; \ 292 mov ar.bspstore=temp;; \ 293 add p_stackframe=-rse_bspstore_offset+rse_rnat_offset,p_stackframe;;\ 294 ld8 temp=[p_stackframe];; \ 295 mov ar.rnat=temp;; \ 296 add p_stackframe=-rse_rnat_offset+rse_pfs_offset,p_stackframe;; \ 297 ld8 temp=[p_stackframe];; \ 298 mov ar.pfs=temp;; \ 299 add p_stackframe=-rse_pfs_offset+rse_ifs_offset,p_stackframe;; \ 300 ld8 temp=[p_stackframe];; \ 301 mov cr.ifs=temp;; \ 302 add p_stackframe=-rse_ifs_offset+rse_rsc_offset,p_stackframe;; \ 303 ld8 temp=[p_stackframe];; \ 304 mov ar.rsc=temp ; \ 305 mov temp=psr;; \ 306 or temp=temp,psr_mask_reg;; \ 307 mov cr.ipsr=temp;; \ 308 mov temp=ip;; \ 309 add temp=0x30,temp;; \ 310 mov cr.iip=temp;; \ 311 srlz.i;; \ 312 rfi;; 313 314 #endif /* _ASM_IA64_MCA_ASM_H */ 315