1 /* 2 * linux/include/asm-arm/hardware/iomd.h 3 * 4 * Copyright (C) 1999 Russell King 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 * 10 * This file contains information out the IOMD ASIC used in the 11 * Acorn RiscPC and subsequently integrated into the CLPS7500 chips. 12 */ 13 #ifndef __ASMARM_HARDWARE_IOMD_H 14 #define __ASMARM_HARDWARE_IOMD_H 15 16 #include <linux/config.h> 17 18 #ifndef __ASSEMBLY__ 19 20 /* 21 * We use __raw_base variants here so that we give the compiler the 22 * chance to keep IOC_BASE in a register. 23 */ 24 #define iomd_readb(off) __raw_base_readb(IOMD_BASE, (off)) 25 #define iomd_readl(off) __raw_base_readl(IOMD_BASE, (off)) 26 #define iomd_writeb(val,off) __raw_base_writeb(val, IOMD_BASE, (off)) 27 #define iomd_writel(val,off) __raw_base_writel(val, IOMD_BASE, (off)) 28 29 #endif 30 31 #if defined(CONFIG_ARCH_RISCSTATION) || defined(CONFIG_ARCH_CLPS7500) 32 #ifndef CONFIG_CPU_7500 33 #define CONFIG_CPU_7500 34 #endif 35 #endif 36 37 #define IOMD_CONTROL (0x000) 38 #define IOMD_KARTTX (0x004) 39 #define IOMD_KARTRX (0x004) 40 #define IOMD_KCTRL (0x008) 41 42 #ifdef CONFIG_CPU_7500 43 #define IOMD_IOLINES (0x00C) 44 #endif 45 46 #define IOMD_IRQSTATA (0x010) 47 #define IOMD_IRQREQA (0x014) 48 #define IOMD_IRQCLRA (0x014) 49 #define IOMD_IRQMASKA (0x018) 50 51 #ifdef CONFIG_CPU_7500 52 #define IOMD_SUSMODE (0x01C) 53 #endif 54 55 #define IOMD_IRQSTATB (0x020) 56 #define IOMD_IRQREQB (0x024) 57 #define IOMD_IRQMASKB (0x028) 58 59 #define IOMD_FIQSTAT (0x030) 60 #define IOMD_FIQREQ (0x034) 61 #define IOMD_FIQMASK (0x038) 62 63 #ifdef CONFIG_CPU_7500 64 #define IOMD_CLKCTL (0x03C) 65 #endif 66 67 #define IOMD_T0CNTL (0x040) 68 #define IOMD_T0LTCHL (0x040) 69 #define IOMD_T0CNTH (0x044) 70 #define IOMD_T0LTCHH (0x044) 71 #define IOMD_T0GO (0x048) 72 #define IOMD_T0LATCH (0x04c) 73 74 #define IOMD_T1CNTL (0x050) 75 #define IOMD_T1LTCHL (0x050) 76 #define IOMD_T1CNTH (0x054) 77 #define IOMD_T1LTCHH (0x054) 78 #define IOMD_T1GO (0x058) 79 #define IOMD_T1LATCH (0x05c) 80 81 #ifdef CONFIG_CPU_7500 82 #define IOMD_IRQSTATC (0x060) 83 #define IOMD_IRQREQC (0x064) 84 #define IOMD_IRQMASKC (0x068) 85 86 #define IOMD_VIDMUX (0x06c) 87 88 #define IOMD_IRQSTATD (0x070) 89 #define IOMD_IRQREQD (0x074) 90 #define IOMD_IRQMASKD (0x078) 91 #endif 92 93 #define IOMD_ROMCR0 (0x080) 94 #define IOMD_ROMCR1 (0x084) 95 #ifdef CONFIG_ARCH_RPC 96 #define IOMD_DRAMCR (0x088) 97 #endif 98 #define IOMD_REFCR (0x08C) 99 100 #define IOMD_FSIZE (0x090) 101 #define IOMD_ID0 (0x094) 102 #define IOMD_ID1 (0x098) 103 #define IOMD_VERSION (0x09C) 104 105 #ifdef CONFIG_ARCH_RPC 106 #define IOMD_MOUSEX (0x0A0) 107 #define IOMD_MOUSEY (0x0A4) 108 #endif 109 110 #ifdef CONFIG_CPU_7500 111 #define IOMD_MSEDAT (0x0A8) 112 #define IOMD_MSECTL (0x0Ac) 113 #endif 114 115 #ifdef CONFIG_ARCH_RPC 116 #define IOMD_DMATCR (0x0C0) 117 #endif 118 #define IOMD_IOTCR (0x0C4) 119 #define IOMD_ECTCR (0x0C8) 120 #ifdef CONFIG_ARCH_RPC 121 #define IOMD_DMAEXT (0x0CC) 122 #endif 123 #ifdef CONFIG_CPU_7500 124 #define IOMD_ASTCR (0x0CC) 125 #define IOMD_DRAMCR (0x0D0) 126 #define IOMD_SELFREF (0x0D4) 127 #define IOMD_ATODICR (0x0E0) 128 #define IOMD_ATODSR (0x0E4) 129 #define IOMD_ATODCC (0x0E8) 130 #define IOMD_ATODCNT1 (0x0EC) 131 #define IOMD_ATODCNT2 (0x0F0) 132 #define IOMD_ATODCNT3 (0x0F4) 133 #define IOMD_ATODCNT4 (0x0F8) 134 #endif 135 136 #ifdef CONFIG_ARCH_RPC 137 #define DMA_EXT_IO0 1 138 #define DMA_EXT_IO1 2 139 #define DMA_EXT_IO2 4 140 #define DMA_EXT_IO3 8 141 142 #define IOMD_IO0CURA (0x100) 143 #define IOMD_IO0ENDA (0x104) 144 #define IOMD_IO0CURB (0x108) 145 #define IOMD_IO0ENDB (0x10C) 146 #define IOMD_IO0CR (0x110) 147 #define IOMD_IO0ST (0x114) 148 149 #define IOMD_IO1CURA (0x120) 150 #define IOMD_IO1ENDA (0x124) 151 #define IOMD_IO1CURB (0x128) 152 #define IOMD_IO1ENDB (0x12C) 153 #define IOMD_IO1CR (0x130) 154 #define IOMD_IO1ST (0x134) 155 156 #define IOMD_IO2CURA (0x140) 157 #define IOMD_IO2ENDA (0x144) 158 #define IOMD_IO2CURB (0x148) 159 #define IOMD_IO2ENDB (0x14C) 160 #define IOMD_IO2CR (0x150) 161 #define IOMD_IO2ST (0x154) 162 163 #define IOMD_IO3CURA (0x160) 164 #define IOMD_IO3ENDA (0x164) 165 #define IOMD_IO3CURB (0x168) 166 #define IOMD_IO3ENDB (0x16C) 167 #define IOMD_IO3CR (0x170) 168 #define IOMD_IO3ST (0x174) 169 #endif 170 171 #define IOMD_SD0CURA (0x180) 172 #define IOMD_SD0ENDA (0x184) 173 #define IOMD_SD0CURB (0x188) 174 #define IOMD_SD0ENDB (0x18C) 175 #define IOMD_SD0CR (0x190) 176 #define IOMD_SD0ST (0x194) 177 178 #ifdef CONFIG_ARCH_RPC 179 #define IOMD_SD1CURA (0x1A0) 180 #define IOMD_SD1ENDA (0x1A4) 181 #define IOMD_SD1CURB (0x1A8) 182 #define IOMD_SD1ENDB (0x1AC) 183 #define IOMD_SD1CR (0x1B0) 184 #define IOMD_SD1ST (0x1B4) 185 #endif 186 187 #define IOMD_CURSCUR (0x1C0) 188 #define IOMD_CURSINIT (0x1C4) 189 190 #define IOMD_VIDCUR (0x1D0) 191 #define IOMD_VIDEND (0x1D4) 192 #define IOMD_VIDSTART (0x1D8) 193 #define IOMD_VIDINIT (0x1DC) 194 #define IOMD_VIDCR (0x1E0) 195 196 #define IOMD_DMASTAT (0x1F0) 197 #define IOMD_DMAREQ (0x1F4) 198 #define IOMD_DMAMASK (0x1F8) 199 200 #define DMA_END_S (1 << 31) 201 #define DMA_END_L (1 << 30) 202 203 #define DMA_CR_C 0x80 204 #define DMA_CR_D 0x40 205 #define DMA_CR_E 0x20 206 207 #define DMA_ST_OFL 4 208 #define DMA_ST_INT 2 209 #define DMA_ST_AB 1 210 211 /* 212 * DMA (MEMC) compatability 213 */ 214 #define HALF_SAM vram_half_sam 215 #define VDMA_ALIGNMENT (HALF_SAM * 2) 216 #define VDMA_XFERSIZE (HALF_SAM) 217 #define VDMA_INIT IOMD_VIDINIT 218 #define VDMA_START IOMD_VIDSTART 219 #define VDMA_END IOMD_VIDEND 220 221 #ifndef __ASSEMBLY__ 222 extern unsigned int vram_half_sam; 223 #define video_set_dma(start,end,offset) \ 224 do { \ 225 outl (SCREEN_START + start, VDMA_START); \ 226 outl (SCREEN_START + end - VDMA_XFERSIZE, VDMA_END); \ 227 if (offset >= end - VDMA_XFERSIZE) \ 228 offset |= 0x40000000; \ 229 outl (SCREEN_START + offset, VDMA_INIT); \ 230 } while (0) 231 #endif 232 233 #endif 234