1 // ---------------------------------------------------------------------------- 2 // ATMEL Microcontroller Software Support - ROUSSET - 3 // ---------------------------------------------------------------------------- 4 // The software is delivered "AS IS" without warranty or condition of any 5 // kind, either express, implied or statutory. This includes without 6 // limitation any warranty or condition with respect to merchantability or 7 // fitness for any particular purpose, or against the infringements of 8 // intellectual property rights of others. 9 // ---------------------------------------------------------------------------- 10 // File Name : AT91RM9200.h 11 // Object : AT91RM9200 definitions 12 // Generated : AT91 SW Application Group 04/16/2003 (12:30:06) 13 // 14 // ---------------------------------------------------------------------------- 15 16 #ifndef AT91RM9200_SYS_H 17 #define AT91RM9200_SYS_H 18 19 #ifndef __ASSEMBLY__ 20 21 // ***************************************************************************** 22 // SOFTWARE API DEFINITION FOR System Peripherals 23 // ***************************************************************************** 24 typedef struct _AT91S_SYS { 25 AT91_REG AIC_SMR[32]; // Source Mode Register 26 AT91_REG AIC_SVR[32]; // Source Vector Register 27 AT91_REG AIC_IVR; // IRQ Vector Register 28 AT91_REG AIC_FVR; // FIQ Vector Register 29 AT91_REG AIC_ISR; // Interrupt Status Register 30 AT91_REG AIC_IPR; // Interrupt Pending Register 31 AT91_REG AIC_IMR; // Interrupt Mask Register 32 AT91_REG AIC_CISR; // Core Interrupt Status Register 33 AT91_REG Reserved0[2]; // 34 AT91_REG AIC_IECR; // Interrupt Enable Command Register 35 AT91_REG AIC_IDCR; // Interrupt Disable Command Register 36 AT91_REG AIC_ICCR; // Interrupt Clear Command Register 37 AT91_REG AIC_ISCR; // Interrupt Set Command Register 38 AT91_REG AIC_EOICR; // End of Interrupt Command Register 39 AT91_REG AIC_SPU; // Spurious Vector Register 40 AT91_REG AIC_DCR; // Debug Control Register (Protect) 41 AT91_REG Reserved1[1]; // 42 AT91_REG AIC_FFER; // Fast Forcing Enable Register 43 AT91_REG AIC_FFDR; // Fast Forcing Disable Register 44 AT91_REG AIC_FFSR; // Fast Forcing Status Register 45 AT91_REG Reserved2[45]; // 46 AT91_REG DBGU_CR; // Control Register 47 AT91_REG DBGU_MR; // Mode Register 48 AT91_REG DBGU_IER; // Interrupt Enable Register 49 AT91_REG DBGU_IDR; // Interrupt Disable Register 50 AT91_REG DBGU_IMR; // Interrupt Mask Register 51 AT91_REG DBGU_CSR; // Channel Status Register 52 AT91_REG DBGU_RHR; // Receiver Holding Register 53 AT91_REG DBGU_THR; // Transmitter Holding Register 54 AT91_REG DBGU_BRGR; // Baud Rate Generator Register 55 AT91_REG Reserved3[7]; // 56 AT91_REG DBGU_C1R; // Chip ID1 Register 57 AT91_REG DBGU_C2R; // Chip ID2 Register 58 AT91_REG DBGU_FNTR; // Force NTRST Register 59 AT91_REG Reserved4[45]; // 60 AT91_REG DBGU_RPR; // Receive Pointer Register 61 AT91_REG DBGU_RCR; // Receive Counter Register 62 AT91_REG DBGU_TPR; // Transmit Pointer Register 63 AT91_REG DBGU_TCR; // Transmit Counter Register 64 AT91_REG DBGU_RNPR; // Receive Next Pointer Register 65 AT91_REG DBGU_RNCR; // Receive Next Counter Register 66 AT91_REG DBGU_TNPR; // Transmit Next Pointer Register 67 AT91_REG DBGU_TNCR; // Transmit Next Counter Register 68 AT91_REG DBGU_PTCR; // PDC Transfer Control Register 69 AT91_REG DBGU_PTSR; // PDC Transfer Status Register 70 AT91_REG Reserved5[54]; // 71 AT91_REG PIOA_PER; // PIO Enable Register 72 AT91_REG PIOA_PDR; // PIO Disable Register 73 AT91_REG PIOA_PSR; // PIO Status Register 74 AT91_REG Reserved6[1]; // 75 AT91_REG PIOA_OER; // Output Enable Register 76 AT91_REG PIOA_ODR; // Output Disable Registerr 77 AT91_REG PIOA_OSR; // Output Status Register 78 AT91_REG Reserved7[1]; // 79 AT91_REG PIOA_IFER; // Input Filter Enable Register 80 AT91_REG PIOA_IFDR; // Input Filter Disable Register 81 AT91_REG PIOA_IFSR; // Input Filter Status Register 82 AT91_REG Reserved8[1]; // 83 AT91_REG PIOA_SODR; // Set Output Data Register 84 AT91_REG PIOA_CODR; // Clear Output Data Register 85 AT91_REG PIOA_ODSR; // Output Data Status Register 86 AT91_REG PIOA_PDSR; // Pin Data Status Register 87 AT91_REG PIOA_IER; // Interrupt Enable Register 88 AT91_REG PIOA_IDR; // Interrupt Disable Register 89 AT91_REG PIOA_IMR; // Interrupt Mask Register 90 AT91_REG PIOA_ISR; // Interrupt Status Register 91 AT91_REG PIOA_MDER; // Multi-driver Enable Register 92 AT91_REG PIOA_MDDR; // Multi-driver Disable Register 93 AT91_REG PIOA_MDSR; // Multi-driver Status Register 94 AT91_REG Reserved9[1]; // 95 AT91_REG PIOA_PPUDR; // Pull-up Disable Register 96 AT91_REG PIOA_PPUER; // Pull-up Enable Register 97 AT91_REG PIOA_PPUSR; // Pad Pull-up Status Register 98 AT91_REG Reserved10[1]; // 99 AT91_REG PIOA_ASR; // Select A Register 100 AT91_REG PIOA_BSR; // Select B Register 101 AT91_REG PIOA_ABSR; // AB Select Status Register 102 AT91_REG Reserved11[9]; // 103 AT91_REG PIOA_OWER; // Output Write Enable Register 104 AT91_REG PIOA_OWDR; // Output Write Disable Register 105 AT91_REG PIOA_OWSR; // Output Write Status Register 106 AT91_REG Reserved12[85]; // 107 AT91_REG PIOB_PER; // PIO Enable Register 108 AT91_REG PIOB_PDR; // PIO Disable Register 109 AT91_REG PIOB_PSR; // PIO Status Register 110 AT91_REG Reserved13[1]; // 111 AT91_REG PIOB_OER; // Output Enable Register 112 AT91_REG PIOB_ODR; // Output Disable Registerr 113 AT91_REG PIOB_OSR; // Output Status Register 114 AT91_REG Reserved14[1]; // 115 AT91_REG PIOB_IFER; // Input Filter Enable Register 116 AT91_REG PIOB_IFDR; // Input Filter Disable Register 117 AT91_REG PIOB_IFSR; // Input Filter Status Register 118 AT91_REG Reserved15[1]; // 119 AT91_REG PIOB_SODR; // Set Output Data Register 120 AT91_REG PIOB_CODR; // Clear Output Data Register 121 AT91_REG PIOB_ODSR; // Output Data Status Register 122 AT91_REG PIOB_PDSR; // Pin Data Status Register 123 AT91_REG PIOB_IER; // Interrupt Enable Register 124 AT91_REG PIOB_IDR; // Interrupt Disable Register 125 AT91_REG PIOB_IMR; // Interrupt Mask Register 126 AT91_REG PIOB_ISR; // Interrupt Status Register 127 AT91_REG PIOB_MDER; // Multi-driver Enable Register 128 AT91_REG PIOB_MDDR; // Multi-driver Disable Register 129 AT91_REG PIOB_MDSR; // Multi-driver Status Register 130 AT91_REG Reserved16[1]; // 131 AT91_REG PIOB_PPUDR; // Pull-up Disable Register 132 AT91_REG PIOB_PPUER; // Pull-up Enable Register 133 AT91_REG PIOB_PPUSR; // Pad Pull-up Status Register 134 AT91_REG Reserved17[1]; // 135 AT91_REG PIOB_ASR; // Select A Register 136 AT91_REG PIOB_BSR; // Select B Register 137 AT91_REG PIOB_ABSR; // AB Select Status Register 138 AT91_REG Reserved18[9]; // 139 AT91_REG PIOB_OWER; // Output Write Enable Register 140 AT91_REG PIOB_OWDR; // Output Write Disable Register 141 AT91_REG PIOB_OWSR; // Output Write Status Register 142 AT91_REG Reserved19[85]; // 143 AT91_REG PIOC_PER; // PIO Enable Register 144 AT91_REG PIOC_PDR; // PIO Disable Register 145 AT91_REG PIOC_PSR; // PIO Status Register 146 AT91_REG Reserved20[1]; // 147 AT91_REG PIOC_OER; // Output Enable Register 148 AT91_REG PIOC_ODR; // Output Disable Registerr 149 AT91_REG PIOC_OSR; // Output Status Register 150 AT91_REG Reserved21[1]; // 151 AT91_REG PIOC_IFER; // Input Filter Enable Register 152 AT91_REG PIOC_IFDR; // Input Filter Disable Register 153 AT91_REG PIOC_IFSR; // Input Filter Status Register 154 AT91_REG Reserved22[1]; // 155 AT91_REG PIOC_SODR; // Set Output Data Register 156 AT91_REG PIOC_CODR; // Clear Output Data Register 157 AT91_REG PIOC_ODSR; // Output Data Status Register 158 AT91_REG PIOC_PDSR; // Pin Data Status Register 159 AT91_REG PIOC_IER; // Interrupt Enable Register 160 AT91_REG PIOC_IDR; // Interrupt Disable Register 161 AT91_REG PIOC_IMR; // Interrupt Mask Register 162 AT91_REG PIOC_ISR; // Interrupt Status Register 163 AT91_REG PIOC_MDER; // Multi-driver Enable Register 164 AT91_REG PIOC_MDDR; // Multi-driver Disable Register 165 AT91_REG PIOC_MDSR; // Multi-driver Status Register 166 AT91_REG Reserved23[1]; // 167 AT91_REG PIOC_PPUDR; // Pull-up Disable Register 168 AT91_REG PIOC_PPUER; // Pull-up Enable Register 169 AT91_REG PIOC_PPUSR; // Pad Pull-up Status Register 170 AT91_REG Reserved24[1]; // 171 AT91_REG PIOC_ASR; // Select A Register 172 AT91_REG PIOC_BSR; // Select B Register 173 AT91_REG PIOC_ABSR; // AB Select Status Register 174 AT91_REG Reserved25[9]; // 175 AT91_REG PIOC_OWER; // Output Write Enable Register 176 AT91_REG PIOC_OWDR; // Output Write Disable Register 177 AT91_REG PIOC_OWSR; // Output Write Status Register 178 AT91_REG Reserved26[85]; // 179 AT91_REG PIOD_PER; // PIO Enable Register 180 AT91_REG PIOD_PDR; // PIO Disable Register 181 AT91_REG PIOD_PSR; // PIO Status Register 182 AT91_REG Reserved27[1]; // 183 AT91_REG PIOD_OER; // Output Enable Register 184 AT91_REG PIOD_ODR; // Output Disable Registerr 185 AT91_REG PIOD_OSR; // Output Status Register 186 AT91_REG Reserved28[1]; // 187 AT91_REG PIOD_IFER; // Input Filter Enable Register 188 AT91_REG PIOD_IFDR; // Input Filter Disable Register 189 AT91_REG PIOD_IFSR; // Input Filter Status Register 190 AT91_REG Reserved29[1]; // 191 AT91_REG PIOD_SODR; // Set Output Data Register 192 AT91_REG PIOD_CODR; // Clear Output Data Register 193 AT91_REG PIOD_ODSR; // Output Data Status Register 194 AT91_REG PIOD_PDSR; // Pin Data Status Register 195 AT91_REG PIOD_IER; // Interrupt Enable Register 196 AT91_REG PIOD_IDR; // Interrupt Disable Register 197 AT91_REG PIOD_IMR; // Interrupt Mask Register 198 AT91_REG PIOD_ISR; // Interrupt Status Register 199 AT91_REG PIOD_MDER; // Multi-driver Enable Register 200 AT91_REG PIOD_MDDR; // Multi-driver Disable Register 201 AT91_REG PIOD_MDSR; // Multi-driver Status Register 202 AT91_REG Reserved30[1]; // 203 AT91_REG PIOD_PPUDR; // Pull-up Disable Register 204 AT91_REG PIOD_PPUER; // Pull-up Enable Register 205 AT91_REG PIOD_PPUSR; // Pad Pull-up Status Register 206 AT91_REG Reserved31[1]; // 207 AT91_REG PIOD_ASR; // Select A Register 208 AT91_REG PIOD_BSR; // Select B Register 209 AT91_REG PIOD_ABSR; // AB Select Status Register 210 AT91_REG Reserved32[9]; // 211 AT91_REG PIOD_OWER; // Output Write Enable Register 212 AT91_REG PIOD_OWDR; // Output Write Disable Register 213 AT91_REG PIOD_OWSR; // Output Write Status Register 214 AT91_REG Reserved33[85]; // 215 AT91_REG PMC_SCER; // System Clock Enable Register 216 AT91_REG PMC_SCDR; // System Clock Disable Register 217 AT91_REG PMC_SCSR; // System Clock Status Register 218 AT91_REG Reserved34[1]; // 219 AT91_REG PMC_PCER; // Peripheral Clock Enable Register 220 AT91_REG PMC_PCDR; // Peripheral Clock Disable Register 221 AT91_REG PMC_PCSR; // Peripheral Clock Status Register 222 AT91_REG Reserved35[1]; // 223 AT91_REG CKGR_MOR; // Main Oscillator Register 224 AT91_REG CKGR_MCFR; // Main Clock Frequency Register 225 AT91_REG CKGR_PLLAR; // PLL A Register 226 AT91_REG CKGR_PLLBR; // PLL B Register 227 AT91_REG PMC_MCKR; // Master Clock Register 228 AT91_REG Reserved36[3]; // 229 AT91_REG PMC_PCKR[8]; // Programmable Clock Register 230 AT91_REG PMC_IER; // Interrupt Enable Register 231 AT91_REG PMC_IDR; // Interrupt Disable Register 232 AT91_REG PMC_SR; // Status Register 233 AT91_REG PMC_IMR; // Interrupt Mask Register 234 AT91_REG Reserved37[36]; // 235 AT91_REG ST_CR; // Control Register 236 AT91_REG ST_PIMR; // Period Interval Mode Register 237 AT91_REG ST_WDMR; // Watchdog Mode Register 238 AT91_REG ST_RTMR; // Real-time Mode Register 239 AT91_REG ST_SR; // Status Register 240 AT91_REG ST_IER; // Interrupt Enable Register 241 AT91_REG ST_IDR; // Interrupt Disable Register 242 AT91_REG ST_IMR; // Interrupt Mask Register 243 AT91_REG ST_RTAR; // Real-time Alarm Register 244 AT91_REG ST_CRTR; // Current Real-time Register 245 AT91_REG Reserved38[54]; // 246 AT91_REG RTC_CR; // Control Register 247 AT91_REG RTC_MR; // Mode Register 248 AT91_REG RTC_TIMR; // Time Register 249 AT91_REG RTC_CALR; // Calendar Register 250 AT91_REG RTC_TIMALR; // Time Alarm Register 251 AT91_REG RTC_CALALR; // Calendar Alarm Register 252 AT91_REG RTC_SR; // Status Register 253 AT91_REG RTC_SCCR; // Status Clear Command Register 254 AT91_REG RTC_IER; // Interrupt Enable Register 255 AT91_REG RTC_IDR; // Interrupt Disable Register 256 AT91_REG RTC_IMR; // Interrupt Mask Register 257 AT91_REG RTC_VER; // Valid Entry Register 258 AT91_REG Reserved39[52]; // 259 AT91_REG MC_RCR; // MC Remap Control Register 260 AT91_REG MC_ASR; // MC Abort Status Register 261 AT91_REG MC_AASR; // MC Abort Address Status Register 262 AT91_REG Reserved40[1]; // 263 AT91_REG MC_PUIA[16]; // MC Protection Unit Area 264 AT91_REG MC_PUP; // MC Protection Unit Peripherals 265 AT91_REG MC_PUER; // MC Protection Unit Enable Register 266 AT91_REG Reserved41[2]; // 267 AT91_REG EBI_CSA; // Chip Select Assignment Register 268 AT91_REG EBI_CFGR; // Configuration Register 269 AT91_REG Reserved42[2]; // 270 AT91_REG EBI_SMC2_CSR[8]; // SMC2 Chip Select Register 271 AT91_REG EBI_SDRC_MR; // SDRAM Controller Mode Register 272 AT91_REG EBI_SDRC_TR; // SDRAM Controller Refresh Timer Register 273 AT91_REG EBI_SDRC_CR; // SDRAM Controller Configuration Register 274 AT91_REG EBI_SDRC_SRR; // SDRAM Controller Self Refresh Register 275 AT91_REG EBI_SDRC_LPR; // SDRAM Controller Low Power Register 276 AT91_REG EBI_SDRC_IER; // SDRAM Controller Interrupt Enable Register 277 AT91_REG EBI_SDRC_IDR; // SDRAM Controller Interrupt Disable Register 278 AT91_REG EBI_SDRC_IMR; // SDRAM Controller Interrupt Mask Register 279 AT91_REG EBI_SDRC_ISR; // SDRAM Controller Interrupt Mask Register 280 AT91_REG Reserved43[3]; // 281 AT91_REG EBI_BFC_MR; // BFC Mode Register 282 } AT91S_SYS, *AT91PS_SYS; 283 284 #else 285 286 /* Offsets from AT91C_BASE_SYS */ 287 #define AIC_SMR (0) // Source Mode Register 288 #define AIC_SVR (128) // Source Vector Register 289 #define AIC_IVR (256) // IRQ Vector Register 290 #define AIC_FVR (260) // FIQ Vector Register 291 #define AIC_ISR (264) // Interrupt Status Register 292 #define AIC_IPR (268) // Interrupt Pending Register 293 #define AIC_IMR (272) // Interrupt Mask Register 294 #define AIC_CISR (276) // Core Interrupt Status Register 295 #define AIC_IECR (288) // Interrupt Enable Command Register 296 #define AIC_IDCR (292) // Interrupt Disable Command Register 297 #define AIC_ICCR (296) // Interrupt Clear Command Register 298 #define AIC_ISCR (300) // Interrupt Set Command Register 299 #define AIC_EOICR (304) // End of Interrupt Command Register 300 #define AIC_SPU (308) // Spurious Vector Register 301 #define AIC_DCR (312) // Debug Control Register (Protect) 302 #define AIC_FFER (320) // Fast Forcing Enable Register 303 #define AIC_FFDR (324) // Fast Forcing Disable Register 304 #define AIC_FFSR (328) // Fast Forcing Status Register 305 306 /* Offsets from AT91C_BASE_SYS */ 307 #define DBGU_CR (0x200 + 0) // Control Register 308 #define DBGU_MR (0x200 + 4) // Mode Register 309 #define DBGU_IER (0x200 + 8) // Interrupt Enable Register 310 #define DBGU_IDR (0x200 + 12) // Interrupt Disable Register 311 #define DBGU_IMR (0x200 + 16) // Interrupt Mask Register 312 #define DBGU_CSR (0x200 + 20) // Channel Status Register 313 #define DBGU_RHR (0x200 + 24) // Receiver Holding Register 314 #define DBGU_THR (0x200 + 28) // Transmitter Holding Register 315 #define DBGU_BRGR (0x200 + 32) // Baud Rate Generator Register 316 #define DBGU_C1R (0x200 + 64) // Chip ID1 Register 317 #define DBGU_C2R (0x200 + 68) // Chip ID2 Register 318 #define DBGU_FNTR (0x200 + 72) // Force NTRST Register 319 #define DBGU_RPR (0x200 + 256) // Receive Pointer Register 320 #define DBGU_RCR (0x200 + 260) // Receive Counter Register 321 #define DBGU_TPR (0x200 + 264) // Transmit Pointer Register 322 #define DBGU_TCR (0x200 + 268) // Transmit Counter Register 323 #define DBGU_RNPR (0x200 + 272) // Receive Next Pointer Register 324 #define DBGU_RNCR (0x200 + 276) // Receive Next Counter Register 325 #define DBGU_TNPR (0x200 + 280) // Transmit Next Pointer Register 326 #define DBGU_TNCR (0x200 + 284) // Transmit Next Counter Register 327 #define DBGU_PTCR (0x200 + 288) // PDC Transfer Control Register 328 #define DBGU_PTSR (0x200 + 292) // PDC Transfer Status Register 329 330 #endif // __ASSEMBLY 331 332 333 // ***************************************************************************** 334 // SOFTWARE API DEFINITION FOR Memory Controller Interface 335 // ***************************************************************************** 336 // -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- 337 #define AT91C_MC_RCB (0x1 << 0) // (MC) Remap Command Bit 338 // -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- 339 #define AT91C_MC_UNDADD (0x1 << 0) // (MC) Undefined Addess Abort Status 340 #define AT91C_MC_MISADD (0x1 << 1) // (MC) Misaligned Addess Abort Status 341 #define AT91C_MC_MPU (0x1 << 2) // (MC) Memory protection Unit Abort Status 342 #define AT91C_MC_ABTSZ (0x3 << 8) // (MC) Abort Size Status 343 #define AT91C_MC_ABTSZ_BYTE (0x0 << 8) // (MC) Byte 344 #define AT91C_MC_ABTSZ_HWORD (0x1 << 8) // (MC) Half-word 345 #define AT91C_MC_ABTSZ_WORD (0x2 << 8) // (MC) Word 346 #define AT91C_MC_ABTTYP (0x3 << 10) // (MC) Abort Type Status 347 #define AT91C_MC_ABTTYP_DATAR (0x0 << 10) // (MC) Data Read 348 #define AT91C_MC_ABTTYP_DATAW (0x1 << 10) // (MC) Data Write 349 #define AT91C_MC_ABTTYP_FETCH (0x2 << 10) // (MC) Code Fetch 350 #define AT91C_MC_MST0 (0x1 << 16) // (MC) Master 0 Abort Source 351 #define AT91C_MC_MST1 (0x1 << 17) // (MC) Master 1 Abort Source 352 #define AT91C_MC_SVMST0 (0x1 << 24) // (MC) Saved Master 0 Abort Source 353 #define AT91C_MC_SVMST1 (0x1 << 25) // (MC) Saved Master 1 Abort Source 354 // -------- MC_PUIA : (MC Offset: 0x10) MC Protection Unit Area -------- 355 #define AT91C_MC_PROT (0x3 << 0) // (MC) Protection 356 #define AT91C_MC_PROT_PNAUNA (0x0) // (MC) Privilege: No Access, User: No Access 357 #define AT91C_MC_PROT_PRWUNA (0x1) // (MC) Privilege: Read/Write, User: No Access 358 #define AT91C_MC_PROT_PRWURO (0x2) // (MC) Privilege: Read/Write, User: Read Only 359 #define AT91C_MC_PROT_PRWURW (0x3) // (MC) Privilege: Read/Write, User: Read/Write 360 #define AT91C_MC_SIZE (0xF << 4) // (MC) Internal Area Size 361 #define AT91C_MC_SIZE_1KB (0x0 << 4) // (MC) Area size 1KByte 362 #define AT91C_MC_SIZE_2KB (0x1 << 4) // (MC) Area size 2KByte 363 #define AT91C_MC_SIZE_4KB (0x2 << 4) // (MC) Area size 4KByte 364 #define AT91C_MC_SIZE_8KB (0x3 << 4) // (MC) Area size 8KByte 365 #define AT91C_MC_SIZE_16KB (0x4 << 4) // (MC) Area size 16KByte 366 #define AT91C_MC_SIZE_32KB (0x5 << 4) // (MC) Area size 32KByte 367 #define AT91C_MC_SIZE_64KB (0x6 << 4) // (MC) Area size 64KByte 368 #define AT91C_MC_SIZE_128KB (0x7 << 4) // (MC) Area size 128KByte 369 #define AT91C_MC_SIZE_256KB (0x8 << 4) // (MC) Area size 256KByte 370 #define AT91C_MC_SIZE_512KB (0x9 << 4) // (MC) Area size 512KByte 371 #define AT91C_MC_SIZE_1MB (0xA << 4) // (MC) Area size 1MByte 372 #define AT91C_MC_SIZE_2MB (0xB << 4) // (MC) Area size 2MByte 373 #define AT91C_MC_SIZE_4MB (0xC << 4) // (MC) Area size 4MByte 374 #define AT91C_MC_SIZE_8MB (0xD << 4) // (MC) Area size 8MByte 375 #define AT91C_MC_SIZE_16MB (0xE << 4) // (MC) Area size 16MByte 376 #define AT91C_MC_SIZE_64MB (0xF << 4) // (MC) Area size 64MByte 377 #define AT91C_MC_BA (0x3FFFF << 10) // (MC) Internal Area Base Address 378 // -------- MC_PUP : (MC Offset: 0x50) MC Protection Unit Peripheral -------- 379 // -------- MC_PUER : (MC Offset: 0x54) MC Protection Unit Area -------- 380 #define AT91C_MC_PUEB (0x1 << 0) // (MC) Protection Unit enable Bit 381 382 383 // ***************************************************************************** 384 // SOFTWARE API DEFINITION FOR Real-time Clock Alarm and Parallel Load Interface 385 // ***************************************************************************** 386 // -------- RTC_CR : (RTC Offset: 0x0) RTC Control Register -------- 387 #define AT91C_RTC_UPDTIM (0x1 << 0) // (RTC) Update Request Time Register 388 #define AT91C_RTC_UPDCAL (0x1 << 1) // (RTC) Update Request Calendar Register 389 #define AT91C_RTC_TIMEVSEL (0x3 << 8) // (RTC) Time Event Selection 390 #define AT91C_RTC_TIMEVSEL_MINUTE (0x0 << 8) // (RTC) Minute change. 391 #define AT91C_RTC_TIMEVSEL_HOUR (0x1 << 8) // (RTC) Hour change. 392 #define AT91C_RTC_TIMEVSEL_DAY24 (0x2 << 8) // (RTC) Every day at midnight. 393 #define AT91C_RTC_TIMEVSEL_DAY12 (0x3 << 8) // (RTC) Every day at noon. 394 #define AT91C_RTC_CALEVSEL (0x3 << 16) // (RTC) Calendar Event Selection 395 #define AT91C_RTC_CALEVSEL_WEEK (0x0 << 16) // (RTC) Week change (every Monday at time 00:00:00). 396 #define AT91C_RTC_CALEVSEL_MONTH (0x1 << 16) // (RTC) Month change (every 01 of each month at time 00:00:00). 397 #define AT91C_RTC_CALEVSEL_YEAR (0x2 << 16) // (RTC) Year change (every January 1 at time 00:00:00). 398 // -------- RTC_MR : (RTC Offset: 0x4) RTC Mode Register -------- 399 #define AT91C_RTC_HRMOD (0x1 << 0) // (RTC) 12-24 hour Mode 400 // -------- RTC_TIMR : (RTC Offset: 0x8) RTC Time Register -------- 401 #define AT91C_RTC_SEC (0x7F << 0) // (RTC) Current Second 402 #define AT91C_RTC_MIN (0x7F << 8) // (RTC) Current Minute 403 #define AT91C_RTC_HOUR (0x3F << 16) // (RTC) Current Hour 404 #define AT91C_RTC_AMPM (0x1 << 22) // (RTC) Ante Meridiem, Post Meridiem Indicator 405 // -------- RTC_CALR : (RTC Offset: 0xc) RTC Calendar Register -------- 406 #define AT91C_RTC_CENT (0x3F << 0) // (RTC) Current Century 407 #define AT91C_RTC_YEAR (0xFF << 8) // (RTC) Current Year 408 #define AT91C_RTC_MONTH (0x1F << 16) // (RTC) Current Month 409 #define AT91C_RTC_DAY (0x7 << 21) // (RTC) Current Day 410 #define AT91C_RTC_DATE (0x3F << 24) // (RTC) Current Date 411 // -------- RTC_TIMALR : (RTC Offset: 0x10) RTC Time Alarm Register -------- 412 #define AT91C_RTC_SECEN (0x1 << 7) // (RTC) Second Alarm Enable 413 #define AT91C_RTC_MINEN (0x1 << 15) // (RTC) Minute Alarm 414 #define AT91C_RTC_HOUREN (0x1 << 23) // (RTC) Current Hour 415 // -------- RTC_CALALR : (RTC Offset: 0x14) RTC Calendar Alarm Register -------- 416 #define AT91C_RTC_MONTHEN (0x1 << 23) // (RTC) Month Alarm Enable 417 #define AT91C_RTC_DATEEN (0x1 << 31) // (RTC) Date Alarm Enable 418 // -------- RTC_SR : (RTC Offset: 0x18) RTC Status Register -------- 419 #define AT91C_RTC_ACKUPD (0x1 << 0) // (RTC) Acknowledge for Update 420 #define AT91C_RTC_ALARM (0x1 << 1) // (RTC) Alarm Flag 421 #define AT91C_RTC_SECEV (0x1 << 2) // (RTC) Second Event 422 #define AT91C_RTC_TIMEV (0x1 << 3) // (RTC) Time Event 423 #define AT91C_RTC_CALEV (0x1 << 4) // (RTC) Calendar event 424 // -------- RTC_SCCR : (RTC Offset: 0x1c) RTC Status Clear Command Register -------- 425 // -------- RTC_IER : (RTC Offset: 0x20) RTC Interrupt Enable Register -------- 426 // -------- RTC_IDR : (RTC Offset: 0x24) RTC Interrupt Disable Register -------- 427 // -------- RTC_IMR : (RTC Offset: 0x28) RTC Interrupt Mask Register -------- 428 // -------- RTC_VER : (RTC Offset: 0x2c) RTC Valid Entry Register -------- 429 #define AT91C_RTC_NVTIM (0x1 << 0) // (RTC) Non valid Time 430 #define AT91C_RTC_NVCAL (0x1 << 1) // (RTC) Non valid Calendar 431 #define AT91C_RTC_NVTIMALR (0x1 << 2) // (RTC) Non valid time Alarm 432 #define AT91C_RTC_NVCALALR (0x1 << 3) // (RTC) Nonvalid Calendar Alarm 433 434 435 // ***************************************************************************** 436 // SOFTWARE API DEFINITION FOR System Timer Interface 437 // ***************************************************************************** 438 // -------- ST_CR : (ST Offset: 0x0) System Timer Control Register -------- 439 #define AT91C_ST_WDRST (0x1 << 0) // (ST) Watchdog Timer Restart 440 // -------- ST_PIMR : (ST Offset: 0x4) System Timer Period Interval Mode Register -------- 441 #define AT91C_ST_PIV (0xFFFF << 0) // (ST) Watchdog Timer Restart 442 // -------- ST_WDMR : (ST Offset: 0x8) System Timer Watchdog Mode Register -------- 443 #define AT91C_ST_WDV (0xFFFF << 0) // (ST) Watchdog Timer Restart 444 #define AT91C_ST_RSTEN (0x1 << 16) // (ST) Reset Enable 445 #define AT91C_ST_EXTEN (0x1 << 17) // (ST) External Signal Assertion Enable 446 // -------- ST_RTMR : (ST Offset: 0xc) System Timer Real-time Mode Register -------- 447 #define AT91C_ST_RTPRES (0xFFFF << 0) // (ST) Real-time Timer Prescaler Value 448 // -------- ST_SR : (ST Offset: 0x10) System Timer Status Register -------- 449 #define AT91C_ST_PITS (0x1 << 0) // (ST) Period Interval Timer Interrupt 450 #define AT91C_ST_WDOVF (0x1 << 1) // (ST) Watchdog Overflow 451 #define AT91C_ST_RTTINC (0x1 << 2) // (ST) Real-time Timer Increment 452 #define AT91C_ST_ALMS (0x1 << 3) // (ST) Alarm Status 453 // -------- ST_IER : (ST Offset: 0x14) System Timer Interrupt Enable Register -------- 454 // -------- ST_IDR : (ST Offset: 0x18) System Timer Interrupt Disable Register -------- 455 // -------- ST_IMR : (ST Offset: 0x1c) System Timer Interrupt Mask Register -------- 456 // -------- ST_RTAR : (ST Offset: 0x20) System Timer Real-time Alarm Register -------- 457 #define AT91C_ST_ALMV (0xFFFFF << 0) // (ST) Alarm Value Value 458 // -------- ST_CRTR : (ST Offset: 0x24) System Timer Current Real-time Register -------- 459 #define AT91C_ST_CRTV (0xFFFFF << 0) // (ST) Current Real-time Value 460 461 462 // ***************************************************************************** 463 // SOFTWARE API DEFINITION FOR Power Management Controler 464 // ***************************************************************************** 465 // -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- 466 #define AT91C_PMC_PCK (0x1 << 0) // (PMC) Processor Clock 467 #define AT91C_PMC_UDP (0x1 << 1) // (PMC) USB Device Port Clock 468 #define AT91C_PMC_MCKUDP (0x1 << 2) // (PMC) USB Device Port Master Clock Automatic Disable on Suspend 469 #define AT91C_PMC_UHP (0x1 << 4) // (PMC) USB Host Port Clock 470 #define AT91C_PMC_PCK0 (0x1 << 8) // (PMC) Programmable Clock Output 471 #define AT91C_PMC_PCK1 (0x1 << 9) // (PMC) Programmable Clock Output 472 #define AT91C_PMC_PCK2 (0x1 << 10) // (PMC) Programmable Clock Output 473 #define AT91C_PMC_PCK3 (0x1 << 11) // (PMC) Programmable Clock Output 474 #define AT91C_PMC_PCK4 (0x1 << 12) // (PMC) Programmable Clock Output 475 #define AT91C_PMC_PCK5 (0x1 << 13) // (PMC) Programmable Clock Output 476 #define AT91C_PMC_PCK6 (0x1 << 14) // (PMC) Programmable Clock Output 477 #define AT91C_PMC_PCK7 (0x1 << 15) // (PMC) Programmable Clock Output 478 // -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register -------- 479 // -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------- 480 // -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- 481 #define AT91C_PMC_CSS (0x3 << 0) // (PMC) Programmable Clock Selection 482 #define AT91C_PMC_CSS_SLOW_CLK (0x0) // (PMC) Slow Clock is selected 483 #define AT91C_PMC_CSS_MAIN_CLK (0x1) // (PMC) Main Clock is selected 484 #define AT91C_PMC_CSS_PLLA_CLK (0x2) // (PMC) Clock from PLL A is selected 485 #define AT91C_PMC_CSS_PLLB_CLK (0x3) // (PMC) Clock from PLL B is selected 486 #define AT91C_PMC_PRES (0x7 << 2) // (PMC) Programmable Clock Prescaler 487 #define AT91C_PMC_PRES_CLK (0x0 << 2) // (PMC) Selected clock 488 #define AT91C_PMC_PRES_CLK_2 (0x1 << 2) // (PMC) Selected clock divided by 2 489 #define AT91C_PMC_PRES_CLK_4 (0x2 << 2) // (PMC) Selected clock divided by 4 490 #define AT91C_PMC_PRES_CLK_8 (0x3 << 2) // (PMC) Selected clock divided by 8 491 #define AT91C_PMC_PRES_CLK_16 (0x4 << 2) // (PMC) Selected clock divided by 16 492 #define AT91C_PMC_PRES_CLK_32 (0x5 << 2) // (PMC) Selected clock divided by 32 493 #define AT91C_PMC_PRES_CLK_64 (0x6 << 2) // (PMC) Selected clock divided by 64 494 #define AT91C_PMC_MDIV (0x3 << 8) // (PMC) Master Clock Division 495 #define AT91C_PMC_MDIV_1 (0x0 << 8) // (PMC) The master clock and the processor clock are the same 496 #define AT91C_PMC_MDIV_2 (0x1 << 8) // (PMC) The processor clock is twice as fast as the master clock 497 #define AT91C_PMC_MDIV_3 (0x2 << 8) // (PMC) The processor clock is three times faster than the master clock 498 #define AT91C_PMC_MDIV_4 (0x3 << 8) // (PMC) The processor clock is four times faster than the master clock 499 // -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register -------- 500 // -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------- 501 #define AT91C_PMC_MOSCS (0x1 << 0) // (PMC) MOSC Status/Enable/Disable/Mask 502 #define AT91C_PMC_LOCKA (0x1 << 1) // (PMC) PLL A Status/Enable/Disable/Mask 503 #define AT91C_PMC_LOCKB (0x1 << 2) // (PMC) PLL B Status/Enable/Disable/Mask 504 #define AT91C_PMC_MCKRDY (0x1 << 3) // (PMC) MCK_RDY Status/Enable/Disable/Mask 505 #define AT91C_PMC_PCK0RDY (0x1 << 8) // (PMC) PCK0_RDY Status/Enable/Disable/Mask 506 #define AT91C_PMC_PCK1RDY (0x1 << 9) // (PMC) PCK1_RDY Status/Enable/Disable/Mask 507 #define AT91C_PMC_PCK2RDY (0x1 << 10) // (PMC) PCK2_RDY Status/Enable/Disable/Mask 508 #define AT91C_PMC_PCK3RDY (0x1 << 11) // (PMC) PCK3_RDY Status/Enable/Disable/Mask 509 #define AT91C_PMC_PCK4RDY (0x1 << 12) // (PMC) PCK4_RDY Status/Enable/Disable/Mask 510 #define AT91C_PMC_PCK5RDY (0x1 << 13) // (PMC) PCK5_RDY Status/Enable/Disable/Mask 511 #define AT91C_PMC_PCK6RDY (0x1 << 14) // (PMC) PCK6_RDY Status/Enable/Disable/Mask 512 #define AT91C_PMC_PCK7RDY (0x1 << 15) // (PMC) PCK7_RDY Status/Enable/Disable/Mask 513 // -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- 514 // -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- 515 // -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register -------- 516 517 518 // ***************************************************************************** 519 // SOFTWARE API DEFINITION FOR Clock Generator Controler 520 // ***************************************************************************** 521 // -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- 522 #define AT91C_CKGR_MOSCEN (0x1 << 0) // (CKGR) Main Oscillator Enable 523 #define AT91C_CKGR_OSCTEST (0x1 << 1) // (CKGR) Oscillator Test 524 #define AT91C_CKGR_OSCOUNT (0xFF << 8) // (CKGR) Main Oscillator Start-up Time 525 // -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- 526 #define AT91C_CKGR_MAINF (0xFFFF << 0) // (CKGR) Main Clock Frequency 527 #define AT91C_CKGR_MAINRDY (0x1 << 16) // (CKGR) Main Clock Ready 528 // -------- CKGR_PLLAR : (CKGR Offset: 0x8) PLL A Register -------- 529 #define AT91C_CKGR_DIVA (0xFF << 0) // (CKGR) Divider Selected 530 #define AT91C_CKGR_DIVA_0 (0x0) // (CKGR) Divider output is 0 531 #define AT91C_CKGR_DIVA_BYPASS (0x1) // (CKGR) Divider is bypassed 532 #define AT91C_CKGR_PLLACOUNT (0x3F << 8) // (CKGR) PLL A Counter 533 #define AT91C_CKGR_OUTA (0x3 << 14) // (CKGR) PLL A Output Frequency Range 534 #define AT91C_CKGR_OUTA_0 (0x0 << 14) // (CKGR) Please refer to the PLLA datasheet 535 #define AT91C_CKGR_OUTA_1 (0x1 << 14) // (CKGR) Please refer to the PLLA datasheet 536 #define AT91C_CKGR_OUTA_2 (0x2 << 14) // (CKGR) Please refer to the PLLA datasheet 537 #define AT91C_CKGR_OUTA_3 (0x3 << 14) // (CKGR) Please refer to the PLLA datasheet 538 #define AT91C_CKGR_MULA (0x7FF << 16) // (CKGR) PLL A Multiplier 539 #define AT91C_CKGR_SRCA (0x1 << 29) // (CKGR) PLL A Source 540 // -------- CKGR_PLLBR : (CKGR Offset: 0xc) PLL B Register -------- 541 #define AT91C_CKGR_DIVB (0xFF << 0) // (CKGR) Divider Selected 542 #define AT91C_CKGR_DIVB_0 (0x0) // (CKGR) Divider output is 0 543 #define AT91C_CKGR_DIVB_BYPASS (0x1) // (CKGR) Divider is bypassed 544 #define AT91C_CKGR_PLLBCOUNT (0x3F << 8) // (CKGR) PLL B Counter 545 #define AT91C_CKGR_OUTB (0x3 << 14) // (CKGR) PLL B Output Frequency Range 546 #define AT91C_CKGR_OUTB_0 (0x0 << 14) // (CKGR) Please refer to the PLLB datasheet 547 #define AT91C_CKGR_OUTB_1 (0x1 << 14) // (CKGR) Please refer to the PLLB datasheet 548 #define AT91C_CKGR_OUTB_2 (0x2 << 14) // (CKGR) Please refer to the PLLB datasheet 549 #define AT91C_CKGR_OUTB_3 (0x3 << 14) // (CKGR) Please refer to the PLLB datasheet 550 #define AT91C_CKGR_MULB (0x7FF << 16) // (CKGR) PLL B Multiplier 551 #define AT91C_CKGR_USB_96M (0x1 << 28) // (CKGR) Divider for USB Ports 552 #define AT91C_CKGR_USB_PLL (0x1 << 29) // (CKGR) PLL Use 553 554 555 // ***************************************************************************** 556 // SOFTWARE API DEFINITION FOR Debug Unit 557 // ***************************************************************************** 558 // -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- 559 // -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register -------- 560 // -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- 561 #define AT91C_DBGU_TXRDY (0x1 << 1) // (DBGU) TXRDY Interrupt 562 #define AT91C_DBGU_TXEMPTY (0x1 << 9) // (DBGU) TXEMPTY Interrupt 563 // -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register -------- 564 // -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register -------- 565 // -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register -------- 566 // -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register -------- 567 #define AT91C_DBGU_FORCE_NTRST (0x1 << 0) // (DBGU) Force NTRST in JTAG 568 569 570 // ***************************************************************************** 571 // SOFTWARE API DEFINITION FOR Peripheral Data Controller 572 // ***************************************************************************** 573 // -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- 574 #define AT91C_PDC_RXTEN (0x1 << 0) // (PDC) Receiver Transfer Enable 575 #define AT91C_PDC_RXTDIS (0x1 << 1) // (PDC) Receiver Transfer Disable 576 #define AT91C_PDC_TXTEN (0x1 << 8) // (PDC) Transmitter Transfer Enable 577 #define AT91C_PDC_TXTDIS (0x1 << 9) // (PDC) Transmitter Transfer Disable 578 // -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- 579 580 581 // ***************************************************************************** 582 // SOFTWARE API DEFINITION FOR Advanced Interrupt Controller 583 // ***************************************************************************** 584 // -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- 585 #define AT91C_AIC_PRIOR (0x7 << 0) // (AIC) Priority Level 586 #define AT91C_AIC_PRIOR_LOWEST (0x0) // (AIC) Lowest priority level 587 #define AT91C_AIC_PRIOR_HIGHEST (0x7) // (AIC) Highest priority level 588 #define AT91C_AIC_SRCTYPE (0x3 << 5) // (AIC) Interrupt Source Type 589 #define AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE (0x0 << 5) // (AIC) Internal Sources Code Label Level Sensitive 590 #define AT91C_AIC_SRCTYPE_INT_EDGE_TRIGGERED (0x1 << 5) // (AIC) Internal Sources Code Label Edge triggered 591 #define AT91C_AIC_SRCTYPE_EXT_HIGH_LEVEL (0x2 << 5) // (AIC) External Sources Code Label High-level Sensitive 592 #define AT91C_AIC_SRCTYPE_EXT_POSITIVE_EDGE (0x3 << 5) // (AIC) External Sources Code Label Positive Edge triggered 593 // -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- 594 #define AT91C_AIC_NFIQ (0x1 << 0) // (AIC) NFIQ Status 595 #define AT91C_AIC_NIRQ (0x1 << 1) // (AIC) NIRQ Status 596 // -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) -------- 597 #define AT91C_AIC_DCR_PROT (0x1 << 0) // (AIC) Protection Mode 598 #define AT91C_AIC_DCR_GMSK (0x1 << 1) // (AIC) General Mask 599 600 601 // ***************************************************************************** 602 // SOFTWARE API DEFINITION FOR External Bus Interface 603 // ***************************************************************************** 604 // -------- EBI_CSA : (EBI Offset: 0x0) Chip Select Assignment Register -------- 605 #define AT91C_EBI_CS0A (0x1 << 0) // (EBI) Chip Select 0 Assignment 606 #define AT91C_EBI_CS0A_SMC (0x0) // (EBI) Chip Select 0 is assigned to the Static Memory Controller. 607 #define AT91C_EBI_CS0A_BFC (0x1) // (EBI) Chip Select 0 is assigned to the Burst Flash Controller. 608 #define AT91C_EBI_CS1A (0x1 << 1) // (EBI) Chip Select 1 Assignment 609 #define AT91C_EBI_CS1A_SMC (0x0 << 1) // (EBI) Chip Select 1 is assigned to the Static Memory Controller. 610 #define AT91C_EBI_CS1A_SDRAMC (0x1 << 1) // (EBI) Chip Select 1 is assigned to the SDRAM Controller. 611 #define AT91C_EBI_CS3A (0x1 << 3) // (EBI) Chip Select 3 Assignment 612 #define AT91C_EBI_CS3A_SMC (0x0 << 3) // (EBI) Chip Select 3 is only assigned to the Static Memory Controller and NCS3 behaves as defined by the SMC2. 613 #define AT91C_EBI_CS3A_SMC_SmartMedia (0x1 << 3) // (EBI) Chip Select 3 is assigned to the Static Memory Controller and the SmartMedia Logic is activated. 614 #define AT91C_EBI_CS4A (0x1 << 4) // (EBI) Chip Select 4 Assignment 615 #define AT91C_EBI_CS4A_SMC (0x0 << 4) // (EBI) Chip Select 4 is assigned to the Static Memory Controller and NCS4,NCS5 and NCS6 behave as defined by the SMC2. 616 #define AT91C_EBI_CS4A_SMC_CompactFlash (0x1 << 4) // (EBI) Chip Select 4 is assigned to the Static Memory Controller and the CompactFlash Logic is activated. 617 // -------- EBI_CFGR : (EBI Offset: 0x4) Configuration Register -------- 618 #define AT91C_EBI_DBPUC (0x1 << 0) // (EBI) Data Bus Pull-Up Configuration 619 #define AT91C_EBI_EBSEN (0x1 << 1) // (EBI) Bus Sharing Enable 620 621 622 // ***************************************************************************** 623 // SOFTWARE API DEFINITION FOR Static Memory Controller 2 Interface 624 // ***************************************************************************** 625 626 // -------- SMC2_CSR : (SMC2 Offset: 0x0) SMC2 Chip Select Register -------- 627 #define AT91C_SMC2_NWS (0x7F << 0) // (SMC2) Number of Wait States 628 #define AT91C_SMC2_WSEN (0x1 << 7) // (SMC2) Wait State Enable 629 #define AT91C_SMC2_TDF (0xF << 8) // (SMC2) Data Float Time 630 #define AT91C_SMC2_BAT (0x1 << 12) // (SMC2) Byte Access Type 631 #define AT91C_SMC2_DBW (0x1 << 13) // (SMC2) Data Bus Width 632 #define AT91C_SMC2_DBW_16 (0x1 << 13) // (SMC2) 16-bit. 633 #define AT91C_SMC2_DBW_8 (0x2 << 13) // (SMC2) 8-bit. 634 #define AT91C_SMC2_DRP (0x1 << 15) // (SMC2) Data Read Protocol 635 #define AT91C_SMC2_ACSS (0x3 << 16) // (SMC2) Address to Chip Select Setup 636 #define AT91C_SMC2_ACSS_STANDARD (0x0 << 16) // (SMC2) Standard, asserted at the beginning of the access and deasserted at the end. 637 #define AT91C_SMC2_ACSS_1_CYCLE (0x1 << 16) // (SMC2) One cycle less at the beginning and the end of the access. 638 #define AT91C_SMC2_ACSS_2_CYCLES (0x2 << 16) // (SMC2) Two cycles less at the beginning and the end of the access. 639 #define AT91C_SMC2_ACSS_3_CYCLES (0x3 << 16) // (SMC2) Three cycles less at the beginning and the end of the access. 640 #define AT91C_SMC2_RWSETUP (0x7 << 24) // (SMC2) Read and Write Signal Setup Time 641 #define AT91C_SMC2_RWHOLD (0x7 << 29) // (SMC2) Read and Write Signal Hold Time 642 643 644 // ***************************************************************************** 645 // SOFTWARE API DEFINITION FOR SDRAM Controller Interface 646 // ***************************************************************************** 647 // -------- SDRC_MR : (SDRC Offset: 0x0) SDRAM Controller Mode Register -------- 648 #define AT91C_SDRC_MODE (0xF << 0) // (SDRC) Mode 649 #define AT91C_SDRC_MODE_NORMAL_CMD (0x0) // (SDRC) Normal Mode 650 #define AT91C_SDRC_MODE_NOP_CMD (0x1) // (SDRC) NOP Command 651 #define AT91C_SDRC_MODE_PRCGALL_CMD (0x2) // (SDRC) All Banks Precharge Command 652 #define AT91C_SDRC_MODE_LMR_CMD (0x3) // (SDRC) Load Mode Register Command 653 #define AT91C_SDRC_MODE_RFSH_CMD (0x4) // (SDRC) Refresh Command 654 #define AT91C_SDRC_DBW (0x1 << 4) // (SDRC) Data Bus Width 655 #define AT91C_SDRC_DBW_32_BITS (0x0 << 4) // (SDRC) 32 Bits datas bus 656 #define AT91C_SDRC_DBW_16_BITS (0x1 << 4) // (SDRC) 16 Bits datas bus 657 // -------- SDRC_TR : (SDRC Offset: 0x4) SDRC Refresh Timer Register -------- 658 #define AT91C_SDRC_COUNT (0xFFF << 0) // (SDRC) Refresh Counter 659 // -------- SDRC_CR : (SDRC Offset: 0x8) SDRAM Configuration Register -------- 660 #define AT91C_SDRC_NC (0x3 << 0) // (SDRC) Number of Column Bits 661 #define AT91C_SDRC_NC_8 (0x0) // (SDRC) 8 Bits 662 #define AT91C_SDRC_NC_9 (0x1) // (SDRC) 9 Bits 663 #define AT91C_SDRC_NC_10 (0x2) // (SDRC) 10 Bits 664 #define AT91C_SDRC_NC_11 (0x3) // (SDRC) 11 Bits 665 #define AT91C_SDRC_NR (0x3 << 2) // (SDRC) Number of Row Bits 666 #define AT91C_SDRC_NR_11 (0x0 << 2) // (SDRC) 11 Bits 667 #define AT91C_SDRC_NR_12 (0x1 << 2) // (SDRC) 12 Bits 668 #define AT91C_SDRC_NR_13 (0x2 << 2) // (SDRC) 13 Bits 669 #define AT91C_SDRC_NB (0x1 << 4) // (SDRC) Number of Banks 670 #define AT91C_SDRC_NB_2_BANKS (0x0 << 4) // (SDRC) 2 banks 671 #define AT91C_SDRC_NB_4_BANKS (0x1 << 4) // (SDRC) 4 banks 672 #define AT91C_SDRC_CAS (0x3 << 5) // (SDRC) CAS Latency 673 #define AT91C_SDRC_CAS_2 (0x2 << 5) // (SDRC) 2 cycles 674 #define AT91C_SDRC_TWR (0xF << 7) // (SDRC) Number of Write Recovery Time Cycles 675 #define AT91C_SDRC_TRC (0xF << 11) // (SDRC) Number of RAS Cycle Time Cycles 676 #define AT91C_SDRC_TRP (0xF << 15) // (SDRC) Number of RAS Precharge Time Cycles 677 #define AT91C_SDRC_TRCD (0xF << 19) // (SDRC) Number of RAS to CAS Delay Cycles 678 #define AT91C_SDRC_TRAS (0xF << 23) // (SDRC) Number of RAS Active Time Cycles 679 #define AT91C_SDRC_TXSR (0xF << 27) // (SDRC) Number of Command Recovery Time Cycles 680 // -------- SDRC_SRR : (SDRC Offset: 0xc) SDRAM Controller Self-refresh Register -------- 681 #define AT91C_SDRC_SRCB (0x1 << 0) // (SDRC) Self-refresh Command Bit 682 // -------- SDRC_LPR : (SDRC Offset: 0x10) SDRAM Controller Low-power Register -------- 683 #define AT91C_SDRC_LPCB (0x1 << 0) // (SDRC) Low-power Command Bit 684 // -------- SDRC_IER : (SDRC Offset: 0x14) SDRAM Controller Interrupt Enable Register -------- 685 #define AT91C_SDRC_RES (0x1 << 0) // (SDRC) Refresh Error Status 686 // -------- SDRC_IDR : (SDRC Offset: 0x18) SDRAM Controller Interrupt Disable Register -------- 687 // -------- SDRC_IMR : (SDRC Offset: 0x1c) SDRAM Controller Interrupt Mask Register -------- 688 // -------- SDRC_ISR : (SDRC Offset: 0x20) SDRAM Controller Interrupt Status Register -------- 689 690 691 // ***************************************************************************** 692 // SOFTWARE API DEFINITION FOR Burst Flash Controller Interface 693 // ***************************************************************************** 694 // -------- BFC_MR : (BFC Offset: 0x0) BFC Mode Register -------- 695 #define AT91C_BFC_BFCOM (0x3 << 0) // (BFC) Burst Flash Controller Operating Mode 696 #define AT91C_BFC_BFCOM_DISABLED (0x0) // (BFC) NPCS0 is driven by the SMC or remains high. 697 #define AT91C_BFC_BFCOM_ASYNC (0x1) // (BFC) Asynchronous 698 #define AT91C_BFC_BFCOM_BURST_READ (0x2) // (BFC) Burst Read 699 #define AT91C_BFC_BFCC (0x3 << 2) // (BFC) Burst Flash Controller Operating Mode 700 #define AT91C_BFC_BFCC_MCK (0x1 << 2) // (BFC) Master Clock. 701 #define AT91C_BFC_BFCC_MCK_DIV_2 (0x2 << 2) // (BFC) Master Clock divided by 2. 702 #define AT91C_BFC_BFCC_MCK_DIV_4 (0x3 << 2) // (BFC) Master Clock divided by 4. 703 #define AT91C_BFC_AVL (0xF << 4) // (BFC) Address Valid Latency 704 #define AT91C_BFC_PAGES (0x7 << 8) // (BFC) Page Size 705 #define AT91C_BFC_PAGES_NO_PAGE (0x0 << 8) // (BFC) No page handling. 706 #define AT91C_BFC_PAGES_16 (0x1 << 8) // (BFC) 16 bytes page size. 707 #define AT91C_BFC_PAGES_32 (0x2 << 8) // (BFC) 32 bytes page size. 708 #define AT91C_BFC_PAGES_64 (0x3 << 8) // (BFC) 64 bytes page size. 709 #define AT91C_BFC_PAGES_128 (0x4 << 8) // (BFC) 128 bytes page size. 710 #define AT91C_BFC_PAGES_256 (0x5 << 8) // (BFC) 256 bytes page size. 711 #define AT91C_BFC_PAGES_512 (0x6 << 8) // (BFC) 512 bytes page size. 712 #define AT91C_BFC_PAGES_1024 (0x7 << 8) // (BFC) 1024 bytes page size. 713 #define AT91C_BFC_OEL (0x3 << 12) // (BFC) Output Enable Latency 714 #define AT91C_BFC_BAAEN (0x1 << 16) // (BFC) Burst Address Advance Enable 715 #define AT91C_BFC_BFOEH (0x1 << 17) // (BFC) Burst Flash Output Enable Handling 716 #define AT91C_BFC_MUXEN (0x1 << 18) // (BFC) Multiplexed Bus Enable 717 #define AT91C_BFC_RDYEN (0x1 << 19) // (BFC) Ready Enable Mode 718 719 #endif 720