1 /*
2 * include/asm-alpha/dma.h
3 *
4 * This is essentially the same as the i386 DMA stuff, as the AlphaPCs
5 * use ISA-compatible dma. The only extension is support for high-page
6 * registers that allow to set the top 8 bits of a 32-bit DMA address.
7 * This register should be written last when setting up a DMA address
8 * as this will also enable DMA across 64 KB boundaries.
9 */
10
11 /* $Id: dma.h,v 1.7 1992/12/14 00:29:34 root Exp root $
12 * linux/include/asm/dma.h: Defines for using and allocating dma channels.
13 * Written by Hennus Bergman, 1992.
14 * High DMA channel support & info by Hannu Savolainen
15 * and John Boyd, Nov. 1992.
16 */
17
18 #ifndef _ASM_DMA_H
19 #define _ASM_DMA_H
20
21 #include <linux/config.h>
22 #include <linux/spinlock.h>
23 #include <asm/io.h>
24
25 #define dma_outb outb
26 #define dma_inb inb
27
28 /*
29 * NOTES about DMA transfers:
30 *
31 * controller 1: channels 0-3, byte operations, ports 00-1F
32 * controller 2: channels 4-7, word operations, ports C0-DF
33 *
34 * - ALL registers are 8 bits only, regardless of transfer size
35 * - channel 4 is not used - cascades 1 into 2.
36 * - channels 0-3 are byte - addresses/counts are for physical bytes
37 * - channels 5-7 are word - addresses/counts are for physical words
38 * - transfers must not cross physical 64K (0-3) or 128K (5-7) boundaries
39 * - transfer count loaded to registers is 1 less than actual count
40 * - controller 2 offsets are all even (2x offsets for controller 1)
41 * - page registers for 5-7 don't use data bit 0, represent 128K pages
42 * - page registers for 0-3 use bit 0, represent 64K pages
43 *
44 * DMA transfers are limited to the lower 16MB of _physical_ memory.
45 * Note that addresses loaded into registers must be _physical_ addresses,
46 * not logical addresses (which may differ if paging is active).
47 *
48 * Address mapping for channels 0-3:
49 *
50 * A23 ... A16 A15 ... A8 A7 ... A0 (Physical addresses)
51 * | ... | | ... | | ... |
52 * | ... | | ... | | ... |
53 * | ... | | ... | | ... |
54 * P7 ... P0 A7 ... A0 A7 ... A0
55 * | Page | Addr MSB | Addr LSB | (DMA registers)
56 *
57 * Address mapping for channels 5-7:
58 *
59 * A23 ... A17 A16 A15 ... A9 A8 A7 ... A1 A0 (Physical addresses)
60 * | ... | \ \ ... \ \ \ ... \ \
61 * | ... | \ \ ... \ \ \ ... \ (not used)
62 * | ... | \ \ ... \ \ \ ... \
63 * P7 ... P1 (0) A7 A6 ... A0 A7 A6 ... A0
64 * | Page | Addr MSB | Addr LSB | (DMA registers)
65 *
66 * Again, channels 5-7 transfer _physical_ words (16 bits), so addresses
67 * and counts _must_ be word-aligned (the lowest address bit is _ignored_ at
68 * the hardware level, so odd-byte transfers aren't possible).
69 *
70 * Transfer count (_not # bytes_) is limited to 64K, represented as actual
71 * count - 1 : 64K => 0xFFFF, 1 => 0x0000. Thus, count is always 1 or more,
72 * and up to 128K bytes may be transferred on channels 5-7 in one operation.
73 *
74 */
75
76 #define MAX_DMA_CHANNELS 8
77
78 /*
79 ISA DMA limitations on Alpha platforms,
80
81 These may be due to SIO (PCI<->ISA bridge) chipset limitation, or
82 just a wiring limit.
83 */
84
85 /* The maximum address for ISA DMA transfer on Alpha XL, due to an
86 hardware SIO limitation, is 64MB.
87 */
88 #define ALPHA_XL_MAX_DMA_ADDRESS (IDENT_ADDR+0x04000000UL)
89
90 /* The maximum address for ISA DMA transfer on RUFFIAN and NAUTILUS,
91 due to an hardware SIO limitation, is 16MB.
92 */
93 #define ALPHA_RUFFIAN_MAX_DMA_ADDRESS (IDENT_ADDR+0x01000000UL)
94 #define ALPHA_NAUTILUS_MAX_DMA_ADDRESS (IDENT_ADDR+0x01000000UL)
95
96 /* The maximum address for ISA DMA transfer on SABLE, and some ALCORs,
97 due to an hardware SIO chip limitation, is 2GB.
98 */
99 #define ALPHA_SABLE_MAX_DMA_ADDRESS (IDENT_ADDR+0x80000000UL)
100 #define ALPHA_ALCOR_MAX_DMA_ADDRESS (IDENT_ADDR+0x80000000UL)
101
102 /*
103 Maximum address for all the others is the complete 32-bit bus
104 address space.
105 */
106 #define ALPHA_MAX_DMA_ADDRESS (IDENT_ADDR+0x100000000UL)
107
108 #ifdef CONFIG_ALPHA_GENERIC
109 # define MAX_DMA_ADDRESS (alpha_mv.max_dma_address)
110 #else
111 # if defined(CONFIG_ALPHA_XL)
112 # define MAX_DMA_ADDRESS ALPHA_XL_MAX_DMA_ADDRESS
113 # elif defined(CONFIG_ALPHA_RUFFIAN)
114 # define MAX_DMA_ADDRESS ALPHA_RUFFIAN_MAX_DMA_ADDRESS
115 # elif defined(CONFIG_ALPHA_NAUTILUS)
116 # define MAX_DMA_ADDRESS ALPHA_NAUTILUS_MAX_DMA_ADDRESS
117 # elif defined(CONFIG_ALPHA_SABLE)
118 # define MAX_DMA_ADDRESS ALPHA_SABLE_MAX_DMA_ADDRESS
119 # elif defined(CONFIG_ALPHA_ALCOR)
120 # define MAX_DMA_ADDRESS ALPHA_ALCOR_MAX_DMA_ADDRESS
121 # else
122 # define MAX_DMA_ADDRESS ALPHA_MAX_DMA_ADDRESS
123 # endif
124 #endif
125
126 /* 8237 DMA controllers */
127 #define IO_DMA1_BASE 0x00 /* 8 bit slave DMA, channels 0..3 */
128 #define IO_DMA2_BASE 0xC0 /* 16 bit master DMA, ch 4(=slave input)..7 */
129
130 /* DMA controller registers */
131 #define DMA1_CMD_REG 0x08 /* command register (w) */
132 #define DMA1_STAT_REG 0x08 /* status register (r) */
133 #define DMA1_REQ_REG 0x09 /* request register (w) */
134 #define DMA1_MASK_REG 0x0A /* single-channel mask (w) */
135 #define DMA1_MODE_REG 0x0B /* mode register (w) */
136 #define DMA1_CLEAR_FF_REG 0x0C /* clear pointer flip-flop (w) */
137 #define DMA1_TEMP_REG 0x0D /* Temporary Register (r) */
138 #define DMA1_RESET_REG 0x0D /* Master Clear (w) */
139 #define DMA1_CLR_MASK_REG 0x0E /* Clear Mask */
140 #define DMA1_MASK_ALL_REG 0x0F /* all-channels mask (w) */
141 #define DMA1_EXT_MODE_REG (0x400 | DMA1_MODE_REG)
142
143 #define DMA2_CMD_REG 0xD0 /* command register (w) */
144 #define DMA2_STAT_REG 0xD0 /* status register (r) */
145 #define DMA2_REQ_REG 0xD2 /* request register (w) */
146 #define DMA2_MASK_REG 0xD4 /* single-channel mask (w) */
147 #define DMA2_MODE_REG 0xD6 /* mode register (w) */
148 #define DMA2_CLEAR_FF_REG 0xD8 /* clear pointer flip-flop (w) */
149 #define DMA2_TEMP_REG 0xDA /* Temporary Register (r) */
150 #define DMA2_RESET_REG 0xDA /* Master Clear (w) */
151 #define DMA2_CLR_MASK_REG 0xDC /* Clear Mask */
152 #define DMA2_MASK_ALL_REG 0xDE /* all-channels mask (w) */
153 #define DMA2_EXT_MODE_REG (0x400 | DMA2_MODE_REG)
154
155 #define DMA_ADDR_0 0x00 /* DMA address registers */
156 #define DMA_ADDR_1 0x02
157 #define DMA_ADDR_2 0x04
158 #define DMA_ADDR_3 0x06
159 #define DMA_ADDR_4 0xC0
160 #define DMA_ADDR_5 0xC4
161 #define DMA_ADDR_6 0xC8
162 #define DMA_ADDR_7 0xCC
163
164 #define DMA_CNT_0 0x01 /* DMA count registers */
165 #define DMA_CNT_1 0x03
166 #define DMA_CNT_2 0x05
167 #define DMA_CNT_3 0x07
168 #define DMA_CNT_4 0xC2
169 #define DMA_CNT_5 0xC6
170 #define DMA_CNT_6 0xCA
171 #define DMA_CNT_7 0xCE
172
173 #define DMA_PAGE_0 0x87 /* DMA page registers */
174 #define DMA_PAGE_1 0x83
175 #define DMA_PAGE_2 0x81
176 #define DMA_PAGE_3 0x82
177 #define DMA_PAGE_5 0x8B
178 #define DMA_PAGE_6 0x89
179 #define DMA_PAGE_7 0x8A
180
181 #define DMA_HIPAGE_0 (0x400 | DMA_PAGE_0)
182 #define DMA_HIPAGE_1 (0x400 | DMA_PAGE_1)
183 #define DMA_HIPAGE_2 (0x400 | DMA_PAGE_2)
184 #define DMA_HIPAGE_3 (0x400 | DMA_PAGE_3)
185 #define DMA_HIPAGE_4 (0x400 | DMA_PAGE_4)
186 #define DMA_HIPAGE_5 (0x400 | DMA_PAGE_5)
187 #define DMA_HIPAGE_6 (0x400 | DMA_PAGE_6)
188 #define DMA_HIPAGE_7 (0x400 | DMA_PAGE_7)
189
190 #define DMA_MODE_READ 0x44 /* I/O to memory, no autoinit, increment, single mode */
191 #define DMA_MODE_WRITE 0x48 /* memory to I/O, no autoinit, increment, single mode */
192 #define DMA_MODE_CASCADE 0xC0 /* pass thru DREQ->HRQ, DACK<-HLDA only */
193
194 #define DMA_AUTOINIT 0x10
195
196 extern spinlock_t dma_spin_lock;
197
claim_dma_lock(void)198 static __inline__ unsigned long claim_dma_lock(void)
199 {
200 unsigned long flags;
201 spin_lock_irqsave(&dma_spin_lock, flags);
202 return flags;
203 }
204
release_dma_lock(unsigned long flags)205 static __inline__ void release_dma_lock(unsigned long flags)
206 {
207 spin_unlock_irqrestore(&dma_spin_lock, flags);
208 }
209
210 /* enable/disable a specific DMA channel */
enable_dma(unsigned int dmanr)211 static __inline__ void enable_dma(unsigned int dmanr)
212 {
213 if (dmanr<=3)
214 dma_outb(dmanr, DMA1_MASK_REG);
215 else
216 dma_outb(dmanr & 3, DMA2_MASK_REG);
217 }
218
disable_dma(unsigned int dmanr)219 static __inline__ void disable_dma(unsigned int dmanr)
220 {
221 if (dmanr<=3)
222 dma_outb(dmanr | 4, DMA1_MASK_REG);
223 else
224 dma_outb((dmanr & 3) | 4, DMA2_MASK_REG);
225 }
226
227 /* Clear the 'DMA Pointer Flip Flop'.
228 * Write 0 for LSB/MSB, 1 for MSB/LSB access.
229 * Use this once to initialize the FF to a known state.
230 * After that, keep track of it. :-)
231 * --- In order to do that, the DMA routines below should ---
232 * --- only be used while interrupts are disabled! ---
233 */
clear_dma_ff(unsigned int dmanr)234 static __inline__ void clear_dma_ff(unsigned int dmanr)
235 {
236 if (dmanr<=3)
237 dma_outb(0, DMA1_CLEAR_FF_REG);
238 else
239 dma_outb(0, DMA2_CLEAR_FF_REG);
240 }
241
242 /* set mode (above) for a specific DMA channel */
set_dma_mode(unsigned int dmanr,char mode)243 static __inline__ void set_dma_mode(unsigned int dmanr, char mode)
244 {
245 if (dmanr<=3)
246 dma_outb(mode | dmanr, DMA1_MODE_REG);
247 else
248 dma_outb(mode | (dmanr&3), DMA2_MODE_REG);
249 }
250
251 /* set extended mode for a specific DMA channel */
set_dma_ext_mode(unsigned int dmanr,char ext_mode)252 static __inline__ void set_dma_ext_mode(unsigned int dmanr, char ext_mode)
253 {
254 if (dmanr<=3)
255 dma_outb(ext_mode | dmanr, DMA1_EXT_MODE_REG);
256 else
257 dma_outb(ext_mode | (dmanr&3), DMA2_EXT_MODE_REG);
258 }
259
260 /* Set only the page register bits of the transfer address.
261 * This is used for successive transfers when we know the contents of
262 * the lower 16 bits of the DMA current address register.
263 */
set_dma_page(unsigned int dmanr,unsigned int pagenr)264 static __inline__ void set_dma_page(unsigned int dmanr, unsigned int pagenr)
265 {
266 switch(dmanr) {
267 case 0:
268 dma_outb(pagenr, DMA_PAGE_0);
269 dma_outb((pagenr >> 8), DMA_HIPAGE_0);
270 break;
271 case 1:
272 dma_outb(pagenr, DMA_PAGE_1);
273 dma_outb((pagenr >> 8), DMA_HIPAGE_1);
274 break;
275 case 2:
276 dma_outb(pagenr, DMA_PAGE_2);
277 dma_outb((pagenr >> 8), DMA_HIPAGE_2);
278 break;
279 case 3:
280 dma_outb(pagenr, DMA_PAGE_3);
281 dma_outb((pagenr >> 8), DMA_HIPAGE_3);
282 break;
283 case 5:
284 dma_outb(pagenr & 0xfe, DMA_PAGE_5);
285 dma_outb((pagenr >> 8), DMA_HIPAGE_5);
286 break;
287 case 6:
288 dma_outb(pagenr & 0xfe, DMA_PAGE_6);
289 dma_outb((pagenr >> 8), DMA_HIPAGE_6);
290 break;
291 case 7:
292 dma_outb(pagenr & 0xfe, DMA_PAGE_7);
293 dma_outb((pagenr >> 8), DMA_HIPAGE_7);
294 break;
295 }
296 }
297
298
299 /* Set transfer address & page bits for specific DMA channel.
300 * Assumes dma flipflop is clear.
301 */
set_dma_addr(unsigned int dmanr,unsigned int a)302 static __inline__ void set_dma_addr(unsigned int dmanr, unsigned int a)
303 {
304 if (dmanr <= 3) {
305 dma_outb( a & 0xff, ((dmanr&3)<<1) + IO_DMA1_BASE );
306 dma_outb( (a>>8) & 0xff, ((dmanr&3)<<1) + IO_DMA1_BASE );
307 } else {
308 dma_outb( (a>>1) & 0xff, ((dmanr&3)<<2) + IO_DMA2_BASE );
309 dma_outb( (a>>9) & 0xff, ((dmanr&3)<<2) + IO_DMA2_BASE );
310 }
311 set_dma_page(dmanr, a>>16); /* set hipage last to enable 32-bit mode */
312 }
313
314
315 /* Set transfer size (max 64k for DMA1..3, 128k for DMA5..7) for
316 * a specific DMA channel.
317 * You must ensure the parameters are valid.
318 * NOTE: from a manual: "the number of transfers is one more
319 * than the initial word count"! This is taken into account.
320 * Assumes dma flip-flop is clear.
321 * NOTE 2: "count" represents _bytes_ and must be even for channels 5-7.
322 */
set_dma_count(unsigned int dmanr,unsigned int count)323 static __inline__ void set_dma_count(unsigned int dmanr, unsigned int count)
324 {
325 count--;
326 if (dmanr <= 3) {
327 dma_outb( count & 0xff, ((dmanr&3)<<1) + 1 + IO_DMA1_BASE );
328 dma_outb( (count>>8) & 0xff, ((dmanr&3)<<1) + 1 + IO_DMA1_BASE );
329 } else {
330 dma_outb( (count>>1) & 0xff, ((dmanr&3)<<2) + 2 + IO_DMA2_BASE );
331 dma_outb( (count>>9) & 0xff, ((dmanr&3)<<2) + 2 + IO_DMA2_BASE );
332 }
333 }
334
335
336 /* Get DMA residue count. After a DMA transfer, this
337 * should return zero. Reading this while a DMA transfer is
338 * still in progress will return unpredictable results.
339 * If called before the channel has been used, it may return 1.
340 * Otherwise, it returns the number of _bytes_ left to transfer.
341 *
342 * Assumes DMA flip-flop is clear.
343 */
get_dma_residue(unsigned int dmanr)344 static __inline__ int get_dma_residue(unsigned int dmanr)
345 {
346 unsigned int io_port = (dmanr<=3)? ((dmanr&3)<<1) + 1 + IO_DMA1_BASE
347 : ((dmanr&3)<<2) + 2 + IO_DMA2_BASE;
348
349 /* using short to get 16-bit wrap around */
350 unsigned short count;
351
352 count = 1 + dma_inb(io_port);
353 count += dma_inb(io_port) << 8;
354
355 return (dmanr<=3)? count : (count<<1);
356 }
357
358
359 /* These are in kernel/dma.c: */
360 extern int request_dma(unsigned int dmanr, const char * device_id); /* reserve a DMA channel */
361 extern void free_dma(unsigned int dmanr); /* release it again */
362 #define KERNEL_HAVE_CHECK_DMA
363 extern int check_dma(unsigned int dmanr);
364
365 /* From PCI */
366
367 #ifdef CONFIG_PCI
368 extern int isa_dma_bridge_buggy;
369 #else
370 #define isa_dma_bridge_buggy (0)
371 #endif
372
373
374 #endif /* _ASM_DMA_H */
375