1 #ifndef __ALPHA_MCPCIA__H__
2 #define __ALPHA_MCPCIA__H__
3
4 /* Define to experiment with fitting everything into one 128MB HAE window.
5 One window per bus, that is. */
6 #define MCPCIA_ONE_HAE_WINDOW 1
7
8 #include <linux/types.h>
9 #include <linux/pci.h>
10 #include <asm/compiler.h>
11
12 /*
13 * MCPCIA is the internal name for a core logic chipset which provides
14 * PCI access for the RAWHIDE family of systems.
15 *
16 * This file is based on:
17 *
18 * RAWHIDE System Programmer's Manual
19 * 16-May-96
20 * Rev. 1.4
21 *
22 */
23
24 /*------------------------------------------------------------------------**
25 ** **
26 ** I/O procedures **
27 ** **
28 ** inport[b|w|t|l], outport[b|w|t|l] 8:16:24:32 IO xfers **
29 ** inportbxt: 8 bits only **
30 ** inport: alias of inportw **
31 ** outport: alias of outportw **
32 ** **
33 ** inmem[b|w|t|l], outmem[b|w|t|l] 8:16:24:32 ISA memory xfers **
34 ** inmembxt: 8 bits only **
35 ** inmem: alias of inmemw **
36 ** outmem: alias of outmemw **
37 ** **
38 **------------------------------------------------------------------------*/
39
40
41 /* MCPCIA ADDRESS BIT DEFINITIONS
42 *
43 * 3333 3333 3322 2222 2222 1111 1111 11
44 * 9876 5432 1098 7654 3210 9876 5432 1098 7654 3210
45 * ---- ---- ---- ---- ---- ---- ---- ---- ---- ----
46 * 1 000
47 * ---- ---- ---- ---- ---- ---- ---- ---- ---- ----
48 * | |\|
49 * | Byte Enable --+ |
50 * | Transfer Length --+
51 * +-- IO space, not cached
52 *
53 * Byte Transfer
54 * Enable Length Transfer Byte Address
55 * adr<6:5> adr<4:3> Length Enable Adder
56 * ---------------------------------------------
57 * 00 00 Byte 1110 0x000
58 * 01 00 Byte 1101 0x020
59 * 10 00 Byte 1011 0x040
60 * 11 00 Byte 0111 0x060
61 *
62 * 00 01 Word 1100 0x008
63 * 01 01 Word 1001 0x028 <= Not supported in this code.
64 * 10 01 Word 0011 0x048
65 *
66 * 00 10 Tribyte 1000 0x010
67 * 01 10 Tribyte 0001 0x030
68 *
69 * 10 11 Longword 0000 0x058
70 *
71 * Note that byte enables are asserted low.
72 *
73 */
74
75 #define MCPCIA_MID(m) ((unsigned long)(m) << 33)
76
77 /* Dodge has PCI0 and PCI1 at MID 4 and 5 respectively.
78 Durango adds PCI2 and PCI3 at MID 6 and 7 respectively. */
79 #define MCPCIA_HOSE2MID(h) ((h) + 4)
80
81 #define MCPCIA_MEM_MASK 0x07ffffff /* SPARSE Mem region mask is 27 bits */
82
83 /*
84 * Memory spaces:
85 */
86 #define MCPCIA_SPARSE(m) (IDENT_ADDR + 0xf000000000UL + MCPCIA_MID(m))
87 #define MCPCIA_DENSE(m) (IDENT_ADDR + 0xf100000000UL + MCPCIA_MID(m))
88 #define MCPCIA_IO(m) (IDENT_ADDR + 0xf180000000UL + MCPCIA_MID(m))
89 #define MCPCIA_CONF(m) (IDENT_ADDR + 0xf1c0000000UL + MCPCIA_MID(m))
90 #define MCPCIA_CSR(m) (IDENT_ADDR + 0xf1e0000000UL + MCPCIA_MID(m))
91 #define MCPCIA_IO_IACK(m) (IDENT_ADDR + 0xf1f0000000UL + MCPCIA_MID(m))
92 #define MCPCIA_DENSE_IO(m) (IDENT_ADDR + 0xe1fc000000UL + MCPCIA_MID(m))
93 #define MCPCIA_DENSE_CONF(m) (IDENT_ADDR + 0xe1fe000000UL + MCPCIA_MID(m))
94
95 /*
96 * General Registers
97 */
98 #define MCPCIA_REV(m) (MCPCIA_CSR(m) + 0x000)
99 #define MCPCIA_WHOAMI(m) (MCPCIA_CSR(m) + 0x040)
100 #define MCPCIA_PCI_LAT(m) (MCPCIA_CSR(m) + 0x080)
101 #define MCPCIA_CAP_CTRL(m) (MCPCIA_CSR(m) + 0x100)
102 #define MCPCIA_HAE_MEM(m) (MCPCIA_CSR(m) + 0x400)
103 #define MCPCIA_HAE_IO(m) (MCPCIA_CSR(m) + 0x440)
104 #define _MCPCIA_IACK_SC(m) (MCPCIA_CSR(m) + 0x480)
105 #define MCPCIA_HAE_DENSE(m) (MCPCIA_CSR(m) + 0x4C0)
106
107 /*
108 * Interrupt Control registers
109 */
110 #define MCPCIA_INT_CTL(m) (MCPCIA_CSR(m) + 0x500)
111 #define MCPCIA_INT_REQ(m) (MCPCIA_CSR(m) + 0x540)
112 #define MCPCIA_INT_TARG(m) (MCPCIA_CSR(m) + 0x580)
113 #define MCPCIA_INT_ADR(m) (MCPCIA_CSR(m) + 0x5C0)
114 #define MCPCIA_INT_ADR_EXT(m) (MCPCIA_CSR(m) + 0x600)
115 #define MCPCIA_INT_MASK0(m) (MCPCIA_CSR(m) + 0x640)
116 #define MCPCIA_INT_MASK1(m) (MCPCIA_CSR(m) + 0x680)
117 #define MCPCIA_INT_ACK0(m) (MCPCIA_CSR(m) + 0x10003f00)
118 #define MCPCIA_INT_ACK1(m) (MCPCIA_CSR(m) + 0x10003f40)
119
120 /*
121 * Performance Monitor registers
122 */
123 #define MCPCIA_PERF_MON(m) (MCPCIA_CSR(m) + 0x300)
124 #define MCPCIA_PERF_CONT(m) (MCPCIA_CSR(m) + 0x340)
125
126 /*
127 * Diagnostic Registers
128 */
129 #define MCPCIA_CAP_DIAG(m) (MCPCIA_CSR(m) + 0x700)
130 #define MCPCIA_TOP_OF_MEM(m) (MCPCIA_CSR(m) + 0x7C0)
131
132 /*
133 * Error registers
134 */
135 #define MCPCIA_MC_ERR0(m) (MCPCIA_CSR(m) + 0x800)
136 #define MCPCIA_MC_ERR1(m) (MCPCIA_CSR(m) + 0x840)
137 #define MCPCIA_CAP_ERR(m) (MCPCIA_CSR(m) + 0x880)
138 #define MCPCIA_PCI_ERR1(m) (MCPCIA_CSR(m) + 0x1040)
139 #define MCPCIA_MDPA_STAT(m) (MCPCIA_CSR(m) + 0x4000)
140 #define MCPCIA_MDPA_SYN(m) (MCPCIA_CSR(m) + 0x4040)
141 #define MCPCIA_MDPA_DIAG(m) (MCPCIA_CSR(m) + 0x4080)
142 #define MCPCIA_MDPB_STAT(m) (MCPCIA_CSR(m) + 0x8000)
143 #define MCPCIA_MDPB_SYN(m) (MCPCIA_CSR(m) + 0x8040)
144 #define MCPCIA_MDPB_DIAG(m) (MCPCIA_CSR(m) + 0x8080)
145
146 /*
147 * PCI Address Translation Registers.
148 */
149 #define MCPCIA_SG_TBIA(m) (MCPCIA_CSR(m) + 0x1300)
150 #define MCPCIA_HBASE(m) (MCPCIA_CSR(m) + 0x1340)
151
152 #define MCPCIA_W0_BASE(m) (MCPCIA_CSR(m) + 0x1400)
153 #define MCPCIA_W0_MASK(m) (MCPCIA_CSR(m) + 0x1440)
154 #define MCPCIA_T0_BASE(m) (MCPCIA_CSR(m) + 0x1480)
155
156 #define MCPCIA_W1_BASE(m) (MCPCIA_CSR(m) + 0x1500)
157 #define MCPCIA_W1_MASK(m) (MCPCIA_CSR(m) + 0x1540)
158 #define MCPCIA_T1_BASE(m) (MCPCIA_CSR(m) + 0x1580)
159
160 #define MCPCIA_W2_BASE(m) (MCPCIA_CSR(m) + 0x1600)
161 #define MCPCIA_W2_MASK(m) (MCPCIA_CSR(m) + 0x1640)
162 #define MCPCIA_T2_BASE(m) (MCPCIA_CSR(m) + 0x1680)
163
164 #define MCPCIA_W3_BASE(m) (MCPCIA_CSR(m) + 0x1700)
165 #define MCPCIA_W3_MASK(m) (MCPCIA_CSR(m) + 0x1740)
166 #define MCPCIA_T3_BASE(m) (MCPCIA_CSR(m) + 0x1780)
167
168 /* Hack! Only words for bus 0. */
169
170 #if !MCPCIA_ONE_HAE_WINDOW
171 #define MCPCIA_HAE_ADDRESS MCPCIA_HAE_MEM(4)
172 #endif
173 #define MCPCIA_IACK_SC _MCPCIA_IACK_SC(4)
174
175 /*
176 * The canonical non-remaped I/O and MEM addresses have these values
177 * subtracted out. This is arranged so that folks manipulating ISA
178 * devices can use their familiar numbers and have them map to bus 0.
179 */
180
181 #define MCPCIA_IO_BIAS MCPCIA_IO(4)
182 #define MCPCIA_MEM_BIAS MCPCIA_DENSE(4)
183
184 /* Offset between ram physical addresses and pci64 DAC bus addresses. */
185 #define MCPCIA_DAC_OFFSET (1UL << 40)
186
187 /*
188 * Data structure for handling MCPCIA machine checks:
189 */
190 struct el_MCPCIA_uncorrected_frame_mcheck {
191 struct el_common header;
192 struct el_common_EV5_uncorrectable_mcheck procdata;
193 };
194
195
196 #ifdef __KERNEL__
197
198 #ifndef __EXTERN_INLINE
199 #define __EXTERN_INLINE extern inline
200 #define __IO_EXTERN_INLINE
201 #endif
202
203 /*
204 * I/O functions:
205 *
206 * MCPCIA, the RAWHIDE family PCI/memory support chipset for the EV5 (21164)
207 * and EV56 (21164a) processors, can use either a sparse address mapping
208 * scheme, or the so-called byte-word PCI address space, to get at PCI memory
209 * and I/O.
210 *
211 * Unfortunately, we can't use BWIO with EV5, so for now, we always use SPARSE.
212 */
213
214 #define vucp volatile unsigned char *
215 #define vusp volatile unsigned short *
216 #define vip volatile int *
217 #define vuip volatile unsigned int *
218 #define vulp volatile unsigned long *
219
mcpcia_inb(unsigned long in_addr)220 __EXTERN_INLINE u8 mcpcia_inb(unsigned long in_addr)
221 {
222 unsigned long addr, hose, result;
223
224 addr = in_addr & 0xffffUL;
225 hose = in_addr & ~0xffffUL;
226
227 /* ??? I wish I could get rid of this. But there's no ioremap
228 equivalent for I/O space. PCI I/O can be forced into the
229 correct hose's I/O region, but that doesn't take care of
230 legacy ISA crap. */
231 hose += MCPCIA_IO_BIAS;
232
233 result = *(vip) ((addr << 5) + hose + 0x00);
234 return __kernel_extbl(result, addr & 3);
235 }
236
mcpcia_outb(u8 b,unsigned long in_addr)237 __EXTERN_INLINE void mcpcia_outb(u8 b, unsigned long in_addr)
238 {
239 unsigned long addr, hose, w;
240
241 addr = in_addr & 0xffffUL;
242 hose = in_addr & ~0xffffUL;
243 hose += MCPCIA_IO_BIAS;
244
245 w = __kernel_insbl(b, addr & 3);
246 *(vuip) ((addr << 5) + hose + 0x00) = w;
247 mb();
248 }
249
mcpcia_inw(unsigned long in_addr)250 __EXTERN_INLINE u16 mcpcia_inw(unsigned long in_addr)
251 {
252 unsigned long addr, hose, result;
253
254 addr = in_addr & 0xffffUL;
255 hose = in_addr & ~0xffffUL;
256 hose += MCPCIA_IO_BIAS;
257
258 result = *(vip) ((addr << 5) + hose + 0x08);
259 return __kernel_extwl(result, addr & 3);
260 }
261
mcpcia_outw(u16 b,unsigned long in_addr)262 __EXTERN_INLINE void mcpcia_outw(u16 b, unsigned long in_addr)
263 {
264 unsigned long addr, hose, w;
265
266 addr = in_addr & 0xffffUL;
267 hose = in_addr & ~0xffffUL;
268 hose += MCPCIA_IO_BIAS;
269
270 w = __kernel_inswl(b, addr & 3);
271 *(vuip) ((addr << 5) + hose + 0x08) = w;
272 mb();
273 }
274
mcpcia_inl(unsigned long in_addr)275 __EXTERN_INLINE u32 mcpcia_inl(unsigned long in_addr)
276 {
277 unsigned long addr, hose;
278
279 addr = in_addr & 0xffffUL;
280 hose = in_addr & ~0xffffUL;
281 hose += MCPCIA_IO_BIAS;
282
283 return *(vuip) ((addr << 5) + hose + 0x18);
284 }
285
mcpcia_outl(u32 b,unsigned long in_addr)286 __EXTERN_INLINE void mcpcia_outl(u32 b, unsigned long in_addr)
287 {
288 unsigned long addr, hose;
289
290 addr = in_addr & 0xffffUL;
291 hose = in_addr & ~0xffffUL;
292 hose += MCPCIA_IO_BIAS;
293
294 *(vuip) ((addr << 5) + hose + 0x18) = b;
295 mb();
296 }
297
298
299 /*
300 * Memory functions. 64-bit and 32-bit accesses are done through
301 * dense memory space, everything else through sparse space.
302 *
303 * For reading and writing 8 and 16 bit quantities we need to
304 * go through one of the three sparse address mapping regions
305 * and use the HAE_MEM CSR to provide some bits of the address.
306 * The following few routines use only sparse address region 1
307 * which gives 1Gbyte of accessible space which relates exactly
308 * to the amount of PCI memory mapping *into* system address space.
309 * See p 6-17 of the specification but it looks something like this:
310 *
311 * 21164 Address:
312 *
313 * 3 2 1
314 * 9876543210987654321098765432109876543210
315 * 1ZZZZ0.PCI.QW.Address............BBLL
316 *
317 * ZZ = SBZ
318 * BB = Byte offset
319 * LL = Transfer length
320 *
321 * PCI Address:
322 *
323 * 3 2 1
324 * 10987654321098765432109876543210
325 * HHH....PCI.QW.Address........ 00
326 *
327 * HHH = 31:29 HAE_MEM CSR
328 *
329 */
330
mcpcia_ioremap(unsigned long addr,unsigned long size)331 __EXTERN_INLINE unsigned long mcpcia_ioremap(unsigned long addr,
332 unsigned long size
333 __attribute__((unused)))
334 {
335 return addr + MCPCIA_MEM_BIAS;
336 }
337
mcpcia_iounmap(unsigned long addr)338 __EXTERN_INLINE void mcpcia_iounmap(unsigned long addr)
339 {
340 return;
341 }
342
mcpcia_is_ioaddr(unsigned long addr)343 __EXTERN_INLINE int mcpcia_is_ioaddr(unsigned long addr)
344 {
345 return addr >= MCPCIA_SPARSE(0);
346 }
347
mcpcia_readb(unsigned long in_addr)348 __EXTERN_INLINE u8 mcpcia_readb(unsigned long in_addr)
349 {
350 unsigned long addr = in_addr & 0xffffffffUL;
351 unsigned long hose = in_addr & ~0xffffffffUL;
352 unsigned long result, work;
353
354 #if !MCPCIA_ONE_HAE_WINDOW
355 unsigned long msb;
356 msb = addr & ~MCPCIA_MEM_MASK;
357 set_hae(msb);
358 #endif
359 addr = addr & MCPCIA_MEM_MASK;
360
361 hose = hose - MCPCIA_DENSE(4) + MCPCIA_SPARSE(4);
362 work = ((addr << 5) + hose + 0x00);
363 result = *(vip) work;
364 return __kernel_extbl(result, addr & 3);
365 }
366
mcpcia_readw(unsigned long in_addr)367 __EXTERN_INLINE u16 mcpcia_readw(unsigned long in_addr)
368 {
369 unsigned long addr = in_addr & 0xffffffffUL;
370 unsigned long hose = in_addr & ~0xffffffffUL;
371 unsigned long result, work;
372
373 #if !MCPCIA_ONE_HAE_WINDOW
374 unsigned long msb;
375 msb = addr & ~MCPCIA_MEM_MASK;
376 set_hae(msb);
377 #endif
378 addr = addr & MCPCIA_MEM_MASK;
379
380 hose = hose - MCPCIA_DENSE(4) + MCPCIA_SPARSE(4);
381 work = ((addr << 5) + hose + 0x08);
382 result = *(vip) work;
383 return __kernel_extwl(result, addr & 3);
384 }
385
mcpcia_writeb(u8 b,unsigned long in_addr)386 __EXTERN_INLINE void mcpcia_writeb(u8 b, unsigned long in_addr)
387 {
388 unsigned long addr = in_addr & 0xffffffffUL;
389 unsigned long hose = in_addr & ~0xffffffffUL;
390 unsigned long w;
391
392 #if !MCPCIA_ONE_HAE_WINDOW
393 unsigned long msb;
394 msb = addr & ~MCPCIA_MEM_MASK;
395 set_hae(msb);
396 #endif
397 addr = addr & MCPCIA_MEM_MASK;
398
399 w = __kernel_insbl(b, in_addr & 3);
400 hose = hose - MCPCIA_DENSE(4) + MCPCIA_SPARSE(4);
401 *(vuip) ((addr << 5) + hose + 0x00) = w;
402 }
403
mcpcia_writew(u16 b,unsigned long in_addr)404 __EXTERN_INLINE void mcpcia_writew(u16 b, unsigned long in_addr)
405 {
406 unsigned long addr = in_addr & 0xffffffffUL;
407 unsigned long hose = in_addr & ~0xffffffffUL;
408 unsigned long w;
409
410 #if !MCPCIA_ONE_HAE_WINDOW
411 unsigned long msb;
412 msb = addr & ~MCPCIA_MEM_MASK;
413 set_hae(msb);
414 #endif
415 addr = addr & MCPCIA_MEM_MASK;
416
417 w = __kernel_inswl(b, in_addr & 3);
418 hose = hose - MCPCIA_DENSE(4) + MCPCIA_SPARSE(4);
419 *(vuip) ((addr << 5) + hose + 0x08) = w;
420 }
421
mcpcia_readl(unsigned long addr)422 __EXTERN_INLINE u32 mcpcia_readl(unsigned long addr)
423 {
424 return (*(vuip)addr) & 0xffffffff;
425 }
426
mcpcia_readq(unsigned long addr)427 __EXTERN_INLINE u64 mcpcia_readq(unsigned long addr)
428 {
429 return *(vulp)addr;
430 }
431
mcpcia_writel(u32 b,unsigned long addr)432 __EXTERN_INLINE void mcpcia_writel(u32 b, unsigned long addr)
433 {
434 *(vuip)addr = b;
435 }
436
mcpcia_writeq(u64 b,unsigned long addr)437 __EXTERN_INLINE void mcpcia_writeq(u64 b, unsigned long addr)
438 {
439 *(vulp)addr = b;
440 }
441
442 #undef vucp
443 #undef vusp
444 #undef vip
445 #undef vuip
446 #undef vulp
447
448 #ifdef __WANT_IO_DEF
449
450 #define __inb(p) mcpcia_inb((unsigned long)(p))
451 #define __inw(p) mcpcia_inw((unsigned long)(p))
452 #define __inl(p) mcpcia_inl((unsigned long)(p))
453 #define __outb(x,p) mcpcia_outb((x),(unsigned long)(p))
454 #define __outw(x,p) mcpcia_outw((x),(unsigned long)(p))
455 #define __outl(x,p) mcpcia_outl((x),(unsigned long)(p))
456 #define __readb(a) mcpcia_readb((unsigned long)(a))
457 #define __readw(a) mcpcia_readw((unsigned long)(a))
458 #define __readl(a) mcpcia_readl((unsigned long)(a))
459 #define __readq(a) mcpcia_readq((unsigned long)(a))
460 #define __writeb(x,a) mcpcia_writeb((x),(unsigned long)(a))
461 #define __writew(x,a) mcpcia_writew((x),(unsigned long)(a))
462 #define __writel(x,a) mcpcia_writel((x),(unsigned long)(a))
463 #define __writeq(x,a) mcpcia_writeq((x),(unsigned long)(a))
464 #define __ioremap(a,s) mcpcia_ioremap((unsigned long)(a),(s))
465 #define __iounmap(a) mcpcia_iounmap((unsigned long)(a))
466 #define __is_ioaddr(a) mcpcia_is_ioaddr((unsigned long)(a))
467
468 #define __raw_readl(a) __readl(a)
469 #define __raw_readq(a) __readq(a)
470 #define __raw_writel(v,a) __writel((v),(a))
471 #define __raw_writeq(v,a) __writeq((v),(a))
472
473 #endif /* __WANT_IO_DEF */
474
475 #ifdef __IO_EXTERN_INLINE
476 #undef __EXTERN_INLINE
477 #undef __IO_EXTERN_INLINE
478 #endif
479
480 #endif /* __KERNEL__ */
481
482 #endif /* __ALPHA_MCPCIA__H__ */
483