1 /* 2 * linux/drivers/video/sstfb.h -- voodoo graphics frame buffer 3 * 4 * Copyright (c) 2000,2001 Ghozlane Toumi <gtoumi@messel.emse.fr> 5 * 6 * Created 28 Aug 2001 by Ghozlane Toumi 7 * 8 * $Id: sstfb.h,v 1.1.4.1 2001/08/29 01:30:38 ghoz Exp $ 9 */ 10 11 12 #ifndef _SSTFB_H_ 13 #define _SSTFB_H_ 14 15 /* 16 * 17 * Debug Stuff 18 * 19 */ 20 21 #ifdef SST_DEBUG 22 # define dprintk(X...) printk(KERN_DEBUG "sstfb: " X) 23 #else 24 # define dprintk(X...) 25 # undef SST_DEBUG_REG 26 # undef SST_DEBUG_FUNC 27 # undef SST_DEBUG_VAR 28 # undef SST_DEBUG_IOCTL 29 #endif 30 31 #if (SST_DEBUG_REG > 0) 32 # define r_dprintk(X...) dprintk(X) 33 #else 34 # define r_dprintk(X...) 35 #endif 36 #if (SST_DEBUG_REG > 1) 37 # define r_ddprintk(X...) dprintk(" " X) 38 #else 39 # define r_ddprintk(X...) 40 #endif 41 42 #if (SST_DEBUG_FUNC > 0) 43 # define f_dprintk(X...) dprintk(X) 44 #else 45 # define f_dprintk(X...) 46 #endif 47 #if (SST_DEBUG_FUNC > 1) 48 # define f_ddprintk(X...) dprintk(" " X) 49 #else 50 # define f_ddprintk(X...) 51 #endif 52 #if (SST_DEBUG_FUNC > 2) 53 # define f_dddprintk(X...) dprintk(" " X) 54 #else 55 # define f_dddprintk(X...) 56 #endif 57 58 #if (SST_DEBUG_VAR > 0) 59 # define v_dprintk(X...) dprintk(X) 60 # define print_var(V, X...) \ 61 { \ 62 dprintk(X); \ 63 printk(" :\n"); \ 64 sst_dbg_print_var(V); \ 65 } 66 #else 67 # define v_dprintk(X...) 68 # define print_var(X,Y...) 69 #endif 70 71 #define eprintk(X...) printk(KERN_ERR "sstfb: " X) 72 #define iprintk(X...) printk(KERN_INFO "sstfb: " X) 73 #define wprintk(X...) printk(KERN_WARNING "sstfb: " X) 74 75 #define BIT(x) (1ul<<(x)) 76 #define PS2KHZ(a) (1000000000UL/(a)) /* picoseconds to KHz */ 77 #define KHZ2PS(a) (1000000000UL/(a)) 78 #define POW2(x) (1ul<<(x)) 79 80 #ifndef ABS 81 # define ABS(x) (((x)<0)?-(x):(x)) 82 #endif 83 84 //void Dump_regs(void); 85 86 /* 87 * 88 * Const 89 * 90 */ 91 92 /* pci stuff */ 93 #define PCI_INIT_ENABLE 0x40 94 # define PCI_EN_INIT_WR BIT(0) 95 # define PCI_EN_FIFO_WR BIT(1) 96 # define PCI_REMAP_DAC BIT(2) 97 #define PCI_VCLK_ENABLE 0xc0 /* enable video */ 98 #define PCI_VCLK_DISABLE 0xe0 99 100 /* register offsets from memBaseAddr */ 101 #define STATUS 0x0000 102 # define STATUS_FBI_BUSY BIT(7) 103 #define FBZMODE 0x0110 104 # define EN_CLIPPING BIT(0) /* enable clipping */ 105 # define EN_RGB_WRITE BIT(9) /* enable writes to rgb area */ 106 # define EN_ALPHA_WRITE BIT(10) 107 # define ENGINE_INVERT_Y BIT(17) /* invert Y origin (pipe) */ 108 #define LFBMODE 0x0114 109 # define LFB_565 0 /* bits 3:0 .16 bits RGB */ 110 # define LFB_888 4 /* 24 bits RGB */ 111 # define LFB_8888 5 /* 32 bits ARGB */ 112 # define WR_BUFF_FRONT 0 /* write buf select (front) */ 113 # define WR_BUFF_BACK (1 << 4) /* back */ 114 # define RD_BUFF_FRONT 0 /* read buff select (front) */ 115 # define RD_BUFF_BACK (1 << 6) /* back */ 116 # define EN_PXL_PIPELINE BIT(8) /* pixel pipeline (clip..)*/ 117 # define LFB_WORD_SWIZZLE_WR BIT(11) /* enable write-wordswap (big-endian) */ 118 # define LFB_BYTE_SWIZZLE_WR BIT(12) /* enable write-byteswap (big-endian) */ 119 # define LFB_INVERT_Y BIT(13) /* invert Y origin (LFB) */ 120 # define LFB_WORD_SWIZZLE_RD BIT(15) /* enable read-wordswap (big-endian) */ 121 # define LFB_BYTE_SWIZZLE_RD BIT(16) /* enable read-byteswap (big-endian) */ 122 #define CLIP_LEFT_RIGHT 0x0118 123 #define CLIP_LOWY_HIGHY 0x011c 124 #define NOPCMD 0x0120 125 #define FASTFILLCMD 0x0124 126 #define SWAPBUFFCMD 0x0128 127 #define FBIINIT4 0x0200 /* misc controls */ 128 # define FAST_PCI_READS 0 /* 1 waitstate */ 129 # define SLOW_PCI_READS BIT(0) /* 2 ws */ 130 # define LFB_READ_AHEAD BIT(1) 131 #define BACKPORCH 0x0208 132 #define VIDEODIMENSIONS 0x020c 133 #define FBIINIT0 0x0210 /* misc+fifo controls */ 134 # define EN_VGA_PASSTHROUGH BIT(0) 135 # define FBI_RESET BIT(1) 136 # define FIFO_RESET BIT(2) 137 #define FBIINIT1 0x0214 /* PCI + video controls */ 138 # define VIDEO_MASK 0x8080010f /* masks video related bits V1+V2*/ 139 # define FAST_PCI_WRITES 0 /* 0 ws */ 140 # define SLOW_PCI_WRITES BIT(1) /* 1 ws */ 141 # define EN_LFB_READ BIT(3) 142 # define TILES_IN_X_SHIFT 4 143 # define VIDEO_RESET BIT(8) 144 # define EN_BLANKING BIT(12) 145 # define EN_DATA_OE BIT(13) 146 # define EN_BLANK_OE BIT(14) 147 # define EN_HVSYNC_OE BIT(15) 148 # define EN_DCLK_OE BIT(16) 149 # define SEL_INPUT_VCLK_2X 0 /* bit 17 */ 150 # define SEL_INPUT_VCLK_SLAVE BIT(17) 151 # define SEL_SOURCE_VCLK_SLAVE 0 /* bits 21:20 */ 152 # define SEL_SOURCE_VCLK_2X_DIV2 (0x01 << 20) 153 # define SEL_SOURCE_VCLK_2X_SEL (0x02 << 20) 154 # define EN_24BPP BIT(22) 155 # define TILES_IN_X_MSB_SHIFT 24 /* v2 */ 156 # define VCLK_2X_SEL_DEL_SHIFT 27 /* vclk out delay 0,4,6,8ns */ 157 # define VCLK_DEL_SHIFT 29 /* vclk in delay */ 158 #define FBIINIT2 0x0218 /* Dram controls */ 159 # define EN_FAST_RAS_READ BIT(5) 160 # define EN_DRAM_OE BIT(6) 161 # define EN_FAST_RD_AHEAD_WR BIT(7) 162 # define VIDEO_OFFSET_SHIFT 11 /* unit: #rows tile 64x16/2 */ 163 # define SWAP_DACVSYNC 0 164 # define SWAP_DACDATA0 (1 << 9) 165 # define SWAP_FIFO_STALL (2 << 9) 166 # define EN_RD_AHEAD_FIFO BIT(21) 167 # define EN_DRAM_REFRESH BIT(22) 168 # define DRAM_REFRESH_16 (0x30 << 23) /* dram 16 ms */ 169 #define DAC_READ FBIINIT2 /* in remap mode */ 170 #define FBIINIT3 0x021c /* fbi controls */ 171 # define DISABLE_TEXTURE BIT(6) 172 # define Y_SWAP_ORIGIN_SHIFT 22 /* Y swap substraction value */ 173 #define HSYNC 0x0220 174 #define VSYNC 0x0224 175 #define DAC_DATA 0x022c 176 # define DAC_READ_CMD BIT(11) /* set read dacreg mode */ 177 #define FBIINIT5 0x0244 /* v2 specific */ 178 # define FBIINIT5_MASK 0xfa40ffff /* mask video bits*/ 179 # define HDOUBLESCAN BIT(20) 180 # define VDOUBLESCAN BIT(21) 181 # define HSYNC_HIGH BIT(23) 182 # define VSYNC_HIGH BIT(24) 183 # define INTERLACE BIT(26) 184 #define FBIINIT6 0x0248 /* v2 specific */ 185 # define TILES_IN_X_LSB_SHIFT 30 /* v2 */ 186 #define FBIINIT7 0x024c /* v2 specific */ 187 188 /* Dac Registers */ 189 #define DACREG_WMA 0x0 /* pixel write mode address */ 190 #define DACREG_LUT 0x01 /* color value */ 191 #define DACREG_RMR 0x02 /* pixel mask */ 192 #define DACREG_RMA 0x03 /* pixel read mode address */ 193 /*Dac registers in indexed mode (TI, ATT dacs) */ 194 #define DACREG_ADDR_I DACREG_WMA 195 #define DACREG_DATA_I DACREG_RMR 196 #define DACREG_RMR_I 0x00 197 #define DACREG_CR0_I 0x01 198 # define DACREG_CR0_EN_INDEXED BIT(0) /* enable indexec mode */ 199 # define DACREG_CR0_8BIT BIT(1) /* set dac to 8 bits/read */ 200 # define DACREG_CR0_PWDOWN BIT(3) /* powerdown dac */ 201 # define DACREG_CR0_16BPP 0x30 /* mode 3 */ 202 # define DACREG_CR0_24BPP 0x50 /* mode 5 */ 203 #define DACREG_CR1_I 0x05 204 #define DACREG_CC_I 0x06 205 # define DACREG_CC_CLKA BIT(7) /* clk A controled by regs */ 206 # define DACREG_CC_CLKA_C (2<<4) /* clk A uses reg C */ 207 # define DACREG_CC_CLKB BIT(3) /* clk B controled by regs */ 208 # define DACREG_CC_CLKB_D 3 /* clkB uses reg D */ 209 #define DACREG_AC0_I 0x48 /* clock A reg C */ 210 #define DACREG_AC1_I 0x49 211 #define DACREG_BD0_I 0x6c /* clock B reg D */ 212 #define DACREG_BD1_I 0x6d 213 214 /* identification constants */ 215 #define DACREG_MIR_TI 0x97 216 #define DACREG_DIR_TI 0x09 217 #define DACREG_MIR_ATT 0x84 218 #define DACREG_DIR_ATT 0x09 219 /* ics dac specific registers*/ 220 #define DACREG_ICS_PLLWMA 0x04 /* PLL write mode address */ 221 #define DACREG_ICS_PLLDATA 0x05 /* PLL data /parameter */ 222 #define DACREG_ICS_CMD 0x06 /* command */ 223 # define DACREG_ICS_CMD_16BPP 0x50 /* ics color mode 6 (16bpp bypass)*/ 224 # define DACREG_ICS_CMD_24BPP 0x70 /* ics color mode 7 (24bpp bypass)*/ 225 # define DACREG_ICS_CMD_PWDOWN BIT(0) /* powerdown dac */ 226 #define DACREG_ICS_PLLRMA 0x07 /* PLL read mode address */ 227 /* 228 * pll parameter register: 229 * indexed : write addr to PLLWMA, write data in PLLDATA. 230 * for reads use PLLRMA . 231 * 8 freq registers (0-7) for video clock (CLK0) 232 * 2 freq registers (a-b) for graphic clock (CLK1) 233 */ 234 #define DACREG_ICS_PLL_CLK0_1_INI 0x55 /* initial pll M value for freq f1 */ 235 #define DACREG_ICS_PLL_CLK0_7_INI 0x71 /* f7 */ 236 #define DACREG_ICS_PLL_CLK1_B_INI 0x79 /* fb */ 237 #define DACREG_ICS_PLL_CTRL 0x0e 238 # define DACREG_ICS_CLK0 BIT(5) 239 # define DACREG_ICS_CLK0_0 0 240 # define DACREG_ICS_CLK1_A 0 /* bit4 */ 241 242 /* sst default init registers */ 243 #define FBIINIT0_DEFAULT EN_VGA_PASSTHROUGH 244 245 #define FBIINIT1_DEFAULT \ 246 ( \ 247 FAST_PCI_WRITES \ 248 /* SLOW_PCI_WRITES*/ \ 249 | VIDEO_RESET \ 250 | 10 << TILES_IN_X_SHIFT\ 251 | SEL_SOURCE_VCLK_2X_SEL\ 252 | EN_LFB_READ \ 253 ) 254 255 #define FBIINIT2_DEFAULT \ 256 ( \ 257 SWAP_DACVSYNC \ 258 | EN_DRAM_OE \ 259 | DRAM_REFRESH_16 \ 260 | EN_DRAM_REFRESH \ 261 | EN_FAST_RAS_READ \ 262 | EN_RD_AHEAD_FIFO \ 263 | EN_FAST_RD_AHEAD_WR \ 264 ) 265 266 #define FBIINIT3_DEFAULT \ 267 ( DISABLE_TEXTURE ) 268 269 #define FBIINIT4_DEFAULT \ 270 ( \ 271 FAST_PCI_READS \ 272 /* SLOW_PCI_READS*/ \ 273 | LFB_READ_AHEAD \ 274 ) 275 /* Careful with this one : writing back the data just read will trash the DAC 276 reading some fields give logic value on pins, but setting this field will 277 set the source signal driving the pin. conclusion : just use the default 278 as a base before writing back . 279 */ 280 #define FBIINIT6_DEFAULT (0x0) 281 282 /* 283 * 284 * Misc Const 285 * 286 */ 287 288 /* used to know witch clock to set */ 289 enum { 290 VID_CLOCK=0, 291 GFX_CLOCK=1, 292 }; 293 294 /* freq max */ 295 #define DAC_FREF 14318 /* DAC reference freq (Khz) */ 296 #define VCO_MAX 260000 297 298 /* 299 * driver structs 300 */ 301 302 struct pll_timing { 303 unsigned int m; 304 unsigned int n; 305 unsigned int p; 306 }; 307 308 struct sstfb_info; 309 310 struct dac_switch { 311 char * name; 312 int (*detect) (struct sstfb_info *sst_info); 313 int (*set_pll) (struct sstfb_info *sst_info, const struct pll_timing *t, const int clock); 314 void (*set_vidmod) (struct sstfb_info *sst_info, const int bpp); 315 }; 316 317 struct sst_spec { 318 char * name; 319 int default_gfx_clock; /* 50000 for voodoo1, 75000 for voodoo2 */ 320 int max_gfxclk; /* ! in Mhz ie 60 for voodoo 1 */ 321 }; 322 323 struct sstfb_par { 324 unsigned int bpp; 325 unsigned int xDim; /* xres */ 326 unsigned int hSyncOn; /* hsync_len */ 327 unsigned int hSyncOff; /* left_margin + xres + right_margin */ 328 unsigned int hBackPorch;/* left_margin */ 329 unsigned int yDim; 330 unsigned int vSyncOn; 331 unsigned int vSyncOff; 332 unsigned int vBackPorch; 333 unsigned int freq; /* freq in kHz */ 334 struct pll_timing pll; 335 unsigned int tiles_in_X;/* num of tiles in X res */ 336 unsigned int vmode; /* doublescan/interlaced */ 337 unsigned int sync; /* H/V sync polarity */ 338 unsigned int valid; /* par is correct (fool proof) */ 339 }; 340 341 struct sstfb_info { 342 struct fb_info info; 343 struct sstfb_par current_par; 344 struct pci_dev * dev; 345 346 struct { 347 unsigned long base; /* physical */ 348 unsigned long vbase; /* virtual (CPU view) */ 349 unsigned long len; 350 } video; /* fb memory info */ 351 struct { 352 unsigned long base; 353 unsigned long vbase; 354 } mmio; /* registers memory info */ 355 356 struct dac_switch dac_sw; /* dac specific functions */ 357 358 int type; 359 u8 revision; 360 361 /* status */ 362 /*XXX int configured; 363 int indexed_mode; 364 int vgapass; 365 int clipping; */ 366 int gfx_clock; 367 368 int currcon; 369 struct display disp; /* current display */ 370 struct { u_int red, green, blue, transp; } palette[16]; 371 372 union { 373 #ifdef FBCON_HAS_CFB16 374 u16 cfb16[16]; 375 #endif 376 #ifdef EN_24_32_BPP 377 #if defined (FBCON_HAS_CFB24) || defined(FBCON_HAS_CFB32) 378 u32 cfb32[16]; 379 #endif 380 #endif 381 } fbcon_cmap; 382 383 }; 384 385 386 #endif /* _SSTFB_H_ */ 387