1 /*
2  *
3  * Hardware accelerated Matrox Millennium I, II, Mystique, G100, G200 and G400
4  *
5  * (c) 1998-2002 Petr Vandrovec <vandrove@vc.cvut.cz>
6  *
7  * Portions Copyright (c) 2001 Matrox Graphics Inc.
8  *
9  * Version: 1.66 2002/10/14
10  *
11  * MTRR stuff: 1998 Tom Rini <trini@kernel.crashing.org>
12  *
13  * Contributors: "menion?" <menion@mindless.com>
14  *                     Betatesting, fixes, ideas
15  *
16  *               "Kurt Garloff" <garloff@suse.de>
17  *                     Betatesting, fixes, ideas, videomodes, videomodes timmings
18  *
19  *               "Tom Rini" <trini@kernel.crashing.org>
20  *                     MTRR stuff, PPC cleanups, betatesting, fixes, ideas
21  *
22  *               "Bibek Sahu" <scorpio@dodds.net>
23  *                     Access device through readb|w|l and write b|w|l
24  *                     Extensive debugging stuff
25  *
26  *               "Daniel Haun" <haund@usa.net>
27  *                     Testing, hardware cursor fixes
28  *
29  *               "Scott Wood" <sawst46+@pitt.edu>
30  *                     Fixes
31  *
32  *               "Gerd Knorr" <kraxel@goldbach.isdn.cs.tu-berlin.de>
33  *                     Betatesting
34  *
35  *               "Kelly French" <targon@hazmat.com>
36  *               "Fernando Herrera" <fherrera@eurielec.etsit.upm.es>
37  *                     Betatesting, bug reporting
38  *
39  *               "Pablo Bianucci" <pbian@pccp.com.ar>
40  *                     Fixes, ideas, betatesting
41  *
42  *               "Inaky Perez Gonzalez" <inaky@peloncho.fis.ucm.es>
43  *                     Fixes, enhandcements, ideas, betatesting
44  *
45  *               "Ryuichi Oikawa" <roikawa@rr.iiij4u.or.jp>
46  *                     PPC betatesting, PPC support, backward compatibility
47  *
48  *               "Paul Womar" <Paul@pwomar.demon.co.uk>
49  *               "Owen Waller" <O.Waller@ee.qub.ac.uk>
50  *                     PPC betatesting
51  *
52  *               "Thomas Pornin" <pornin@bolet.ens.fr>
53  *                     Alpha betatesting
54  *
55  *               "Pieter van Leuven" <pvl@iae.nl>
56  *               "Ulf Jaenicke-Roessler" <ujr@physik.phy.tu-dresden.de>
57  *                     G100 testing
58  *
59  *               "H. Peter Arvin" <hpa@transmeta.com>
60  *                     Ideas
61  *
62  *               "Cort Dougan" <cort@cs.nmt.edu>
63  *                     CHRP fixes and PReP cleanup
64  *
65  *               "Mark Vojkovich" <mvojkovi@ucsd.edu>
66  *                     G400 support
67  *
68  *               "David C. Hansen" <haveblue@us.ibm.com>
69  *                     Fixes
70  *
71  * (following author is not in any relation with this code, but his code
72  *  is included in this driver)
73  *
74  * Based on framebuffer driver for VBE 2.0 compliant graphic boards
75  *     (c) 1998 Gerd Knorr <kraxel@cs.tu-berlin.de>
76  *
77  * (following author is not in any relation with this code, but his ideas
78  *  were used when writting this driver)
79  *
80  *		 FreeVBE/AF (Matrox), "Shawn Hargreaves" <shawn@talula.demon.co.uk>
81  *
82  */
83 
84 /* make checkconfig does not check includes for this... */
85 #include <linux/config.h>
86 
87 #include "matroxfb_misc.h"
88 #include <linux/interrupt.h>
89 #include <linux/matroxfb.h>
90 
matroxfb_createcursorshape(WPMINFO struct display * p,int vmode)91 void matroxfb_createcursorshape(WPMINFO struct display* p, int vmode) {
92 	unsigned int h;
93 	unsigned int cu, cd;
94 
95 	h = fontheight(p);
96 
97 	if (vmode & FB_VMODE_DOUBLE)
98 		h *= 2;
99 	cd = h;
100 	if (cd >= 10)
101 		cd--;
102 	switch (ACCESS_FBINFO(cursor.type) = (p->conp->vc_cursor_type & CUR_HWMASK)) {
103 		case CUR_NONE:
104 				cu = cd;
105 				break;
106 		case CUR_UNDERLINE:
107 				cu = cd - 2;
108 				break;
109 		case CUR_LOWER_THIRD:
110 				cu = (h * 2) / 3;
111 				break;
112 		case CUR_LOWER_HALF:
113 				cu = h / 2;
114 				break;
115 		case CUR_TWO_THIRDS:
116 				cu = h / 3;
117 				break;
118 		case CUR_BLOCK:
119 		default:
120 				cu = 0;
121 				cd = h;
122 				break;
123 	}
124 	ACCESS_FBINFO(cursor.w) = fontwidth(p);
125 	ACCESS_FBINFO(cursor.u) = cu;
126 	ACCESS_FBINFO(cursor.d) = cd;
127 }
128 
matroxfb_DAC_out(CPMINFO int reg,int val)129 void matroxfb_DAC_out(CPMINFO int reg, int val) {
130 	DBG_REG("outDAC");
131 	mga_outb(M_RAMDAC_BASE+M_X_INDEX, reg);
132 	mga_outb(M_RAMDAC_BASE+M_X_DATAREG, val);
133 }
134 
matroxfb_DAC_in(CPMINFO int reg)135 int matroxfb_DAC_in(CPMINFO int reg) {
136 	DBG_REG("inDAC");
137 	mga_outb(M_RAMDAC_BASE+M_X_INDEX, reg);
138 	return mga_inb(M_RAMDAC_BASE+M_X_DATAREG);
139 }
140 
matroxfb_var2my(struct fb_var_screeninfo * var,struct my_timming * mt)141 void matroxfb_var2my(struct fb_var_screeninfo* var, struct my_timming* mt) {
142 	unsigned int pixclock = var->pixclock;
143 
144 	DBG("var2my")
145 
146 	if (!pixclock) pixclock = 10000;	/* 10ns = 100MHz */
147 	mt->pixclock = 1000000000 / pixclock;
148 	if (mt->pixclock < 1) mt->pixclock = 1;
149 	mt->mnp = -1;
150 	mt->dblscan = var->vmode & FB_VMODE_DOUBLE;
151 	mt->interlaced = var->vmode & FB_VMODE_INTERLACED;
152 	mt->HDisplay = var->xres;
153 	mt->HSyncStart = mt->HDisplay + var->right_margin;
154 	mt->HSyncEnd = mt->HSyncStart + var->hsync_len;
155 	mt->HTotal = mt->HSyncEnd + var->left_margin;
156 	mt->VDisplay = var->yres;
157 	mt->VSyncStart = mt->VDisplay + var->lower_margin;
158 	mt->VSyncEnd = mt->VSyncStart + var->vsync_len;
159 	mt->VTotal = mt->VSyncEnd + var->upper_margin;
160 	mt->sync = var->sync;
161 }
162 
matroxfb_PLL_calcclock(const struct matrox_pll_features * pll,unsigned int freq,unsigned int fmax,unsigned int * in,unsigned int * feed,unsigned int * post)163 int matroxfb_PLL_calcclock(const struct matrox_pll_features* pll, unsigned int freq, unsigned int fmax,
164 		unsigned int* in, unsigned int* feed, unsigned int* post) {
165 	unsigned int bestdiff = ~0;
166 	unsigned int bestvco = 0;
167 	unsigned int fxtal = pll->ref_freq;
168 	unsigned int fwant;
169 	unsigned int p;
170 
171 	DBG("PLL_calcclock")
172 
173 	fwant = freq;
174 
175 #ifdef DEBUG
176 	printk(KERN_ERR "post_shift_max: %d\n", pll->post_shift_max);
177 	printk(KERN_ERR "ref_freq: %d\n", pll->ref_freq);
178 	printk(KERN_ERR "freq: %d\n", freq);
179 	printk(KERN_ERR "vco_freq_min: %d\n", pll->vco_freq_min);
180 	printk(KERN_ERR "in_div_min: %d\n", pll->in_div_min);
181 	printk(KERN_ERR "in_div_max: %d\n", pll->in_div_max);
182 	printk(KERN_ERR "feed_div_min: %d\n", pll->feed_div_min);
183 	printk(KERN_ERR "feed_div_max: %d\n", pll->feed_div_max);
184 	printk(KERN_ERR "fmax: %d\n", fmax);
185 #endif
186 	for (p = 1; p <= pll->post_shift_max; p++) {
187 		if (fwant * 2 > fmax)
188 			break;
189 		fwant *= 2;
190 	}
191 	if (fwant < pll->vco_freq_min) fwant = pll->vco_freq_min;
192 	if (fwant > fmax) fwant = fmax;
193 	for (; p-- > 0; fwant >>= 1, bestdiff >>= 1) {
194 		unsigned int m;
195 
196 		if (fwant < pll->vco_freq_min) break;
197 		for (m = pll->in_div_min; m <= pll->in_div_max; m++) {
198 			unsigned int diff, fvco;
199 			unsigned int n;
200 
201 			n = (fwant * (m + 1) + (fxtal >> 1)) / fxtal - 1;
202 			if (n > pll->feed_div_max)
203 				break;
204 			if (n < pll->feed_div_min)
205 				n = pll->feed_div_min;
206 			fvco = (fxtal * (n + 1)) / (m + 1);
207 			if (fvco < fwant)
208 				diff = fwant - fvco;
209 			else
210 				diff = fvco - fwant;
211 			if (diff < bestdiff) {
212 				bestdiff = diff;
213 				*post = p;
214 				*in = m;
215 				*feed = n;
216 				bestvco = fvco;
217 			}
218 		}
219 	}
220 	dprintk(KERN_ERR "clk: %02X %02X %02X %d %d %d\n", *in, *feed, *post, fxtal, bestvco, fwant);
221 	return bestvco;
222 }
223 
matroxfb_vgaHWinit(WPMINFO struct my_timming * m,struct display * p)224 int matroxfb_vgaHWinit(WPMINFO struct my_timming* m, struct display* p) {
225 	unsigned int hd, hs, he, hbe, ht;
226 	unsigned int vd, vs, ve, vt, lc;
227 	unsigned int wd;
228 	unsigned int divider;
229 	int i;
230 	int text = p->type == FB_TYPE_TEXT;
231 	int fwidth;
232 	struct matrox_hw_state * const hw = &ACCESS_FBINFO(hw);
233 
234 	if (text) {
235 		fwidth = fontwidth(p);
236 		if (!fwidth) fwidth = 8;
237 	} else
238 		fwidth = 8;
239 
240 	DBG("vgaHWinit")
241 
242 	hw->SEQ[0] = 0x00;
243 	if (fwidth == 9)
244 		hw->SEQ[1] = 0x00;
245 	else
246 		hw->SEQ[1] = 0x01;	/* or 0x09 */
247 	hw->SEQ[2] = 0x0F;	/* bitplanes */
248 	hw->SEQ[3] = 0x00;
249 	if (text)
250 		hw->SEQ[4] = 0x02;
251 	else
252 		hw->SEQ[4] = 0x0E;
253 	/* CRTC 0..7, 9, 16..19, 21, 22 are reprogrammed by Matrox Millennium code... Hope that by MGA1064 too */
254 	if (m->dblscan) {
255 		m->VTotal <<= 1;
256 		m->VDisplay <<= 1;
257 		m->VSyncStart <<= 1;
258 		m->VSyncEnd <<= 1;
259 	}
260 	if (m->interlaced) {
261 		m->VTotal >>= 1;
262 		m->VDisplay >>= 1;
263 		m->VSyncStart >>= 1;
264 		m->VSyncEnd >>= 1;
265 	}
266 
267 	/* GCTL is ignored when not using 0xA0000 aperture */
268 	hw->GCTL[0] = 0x00;
269 	hw->GCTL[1] = 0x00;
270 	hw->GCTL[2] = 0x00;
271 	hw->GCTL[3] = 0x00;
272 	hw->GCTL[4] = 0x00;
273 	if (text) {
274 		hw->GCTL[5] = 0x10;
275 		hw->GCTL[6] = 0x02;
276 	} else {
277 		hw->GCTL[5] = 0x40;
278 		hw->GCTL[6] = 0x05;
279 	}
280 	hw->GCTL[7] = 0x0F;
281 	hw->GCTL[8] = 0xFF;
282 
283 	/* Whole ATTR is ignored in PowerGraphics mode */
284 	for (i = 0; i < 16; i++)
285 		hw->ATTR[i] = i;
286 	if (text) {
287 		hw->ATTR[16] = 0x04;
288 	} else {
289 		hw->ATTR[16] = 0x41;
290 	}
291 	hw->ATTR[17] = 0xFF;
292 	hw->ATTR[18] = 0x0F;
293 	if (fwidth == 9)
294 		hw->ATTR[19] = 0x08;
295 	else
296 		hw->ATTR[19] = 0x00;
297 	hw->ATTR[20] = 0x00;
298 
299 	if (text) {
300 		hd = m->HDisplay / fwidth;
301 		hs = m->HSyncStart / fwidth;
302 		he = m->HSyncEnd / fwidth;
303 		ht = m->HTotal / fwidth;
304 		divider = 8;
305 	} else {
306 		hd = m->HDisplay >> 3;
307 		hs = m->HSyncStart >> 3;
308 		he = m->HSyncEnd >> 3;
309 		ht = m->HTotal >> 3;
310 		/* standard timmings are in 8pixels, but for interleaved we cannot */
311 		/* do it for 4bpp (because of (4bpp >> 1(interleaved))/4 == 0) */
312 		/* using 16 or more pixels per unit can save us */
313 		divider = ACCESS_FBINFO(curr.final_bppShift);
314 	}
315 	while (divider & 3) {
316 		hd >>= 1;
317 		hs >>= 1;
318 		he >>= 1;
319 		ht >>= 1;
320 		divider <<= 1;
321 	}
322 	divider = divider / 4;
323 	/* divider can be from 1 to 8 */
324 	while (divider > 8) {
325 		hd <<= 1;
326 		hs <<= 1;
327 		he <<= 1;
328 		ht <<= 1;
329 		divider >>= 1;
330 	}
331 	hd = hd - 1;
332 	hs = hs - 1;
333 	he = he - 1;
334 	ht = ht - 1;
335 	vd = m->VDisplay - 1;
336 	vs = m->VSyncStart - 1;
337 	ve = m->VSyncEnd - 1;
338 	vt = m->VTotal - 2;
339 	lc = vd;
340 	/* G200 cannot work with (ht & 7) == 6 */
341 	if (((ht & 0x07) == 0x06) || ((ht & 0x0F) == 0x04))
342 		ht++;
343 	if (text) {
344 		hbe = ht - 1;
345 		wd = p->var.xres_virtual / (fwidth * 2);
346 	} else {
347 		hbe = ht;
348 		wd = p->var.xres_virtual * ACCESS_FBINFO(curr.final_bppShift) / 64;
349 	}
350 
351 	hw->CRTCEXT[0] = 0;
352 	hw->CRTCEXT[5] = 0;
353 	if (m->interlaced) {
354 		hw->CRTCEXT[0] = 0x80;
355 		hw->CRTCEXT[5] = (hs + he - ht) >> 1;
356 		if (!m->dblscan)
357 			wd <<= 1;
358 		vt &= ~1;
359 	}
360 	hw->CRTCEXT[0] |=  (wd & 0x300) >> 4;
361 	hw->CRTCEXT[1] = (((ht - 4) & 0x100) >> 8) |
362 			  ((hd      & 0x100) >> 7) | /* blanking */
363 			  ((hs      & 0x100) >> 6) | /* sync start */
364 			   (hbe     & 0x040);	 /* end hor. blanking */
365 	/* FIXME: Enable vidrst only on G400, and only if TV-out is used */
366 	if (ACCESS_FBINFO(outputs[1]).src == MATROXFB_SRC_CRTC1)
367 		hw->CRTCEXT[1] |= 0x88;		/* enable horizontal and vertical vidrst */
368 	hw->CRTCEXT[2] =  ((vt & 0xC00) >> 10) |
369 			  ((vd & 0x400) >>  8) |	/* disp end */
370 			  ((vd & 0xC00) >>  7) |	/* vblanking start */
371 			  ((vs & 0xC00) >>  5) |
372 			  ((lc & 0x400) >>  3);
373 	if (text)
374 		hw->CRTCEXT[3] = 0x00;
375 	else
376 		hw->CRTCEXT[3] = (divider - 1) | 0x80;
377 	hw->CRTCEXT[4] = 0;
378 
379 	hw->CRTC[0] = ht-4;
380 	hw->CRTC[1] = hd;
381 	hw->CRTC[2] = hd;
382 	hw->CRTC[3] = (hbe & 0x1F) | 0x80;
383 	hw->CRTC[4] = hs;
384 	hw->CRTC[5] = ((hbe & 0x20) << 2) | (he & 0x1F);
385 	if (text)
386 		hw->CRTC[5] |= 0x60;	/* delay sync for 3 clocks (to same picture position on MGA and VGA) */
387 	hw->CRTC[6] = vt & 0xFF;
388 	hw->CRTC[7] = ((vt & 0x100) >> 8) |
389 		      ((vd & 0x100) >> 7) |
390 		      ((vs & 0x100) >> 6) |
391 		      ((vd & 0x100) >> 5) |
392 		      ((lc & 0x100) >> 4) |
393 		      ((vt & 0x200) >> 4) |
394 		      ((vd & 0x200) >> 3) |
395 		      ((vs & 0x200) >> 2);
396 	hw->CRTC[8] = 0x00;
397 	hw->CRTC[9] = ((vd & 0x200) >> 4) |
398 		      ((lc & 0x200) >> 3);
399 	if (text)
400 		hw->CRTC[9] |= fontheight(p) - 1;
401 	if (m->dblscan && !m->interlaced)
402 		hw->CRTC[9] |= 0x80;
403 	for (i = 10; i < 16; i++)
404 		hw->CRTC[i] = 0x00;
405 	hw->CRTC[16] = vs /* & 0xFF */;
406 	hw->CRTC[17] = (ve & 0x0F) | 0x20;
407 	hw->CRTC[18] = vd /* & 0xFF */;
408 	hw->CRTC[19] = wd /* & 0xFF */;
409 	hw->CRTC[20] = 0x00;
410 	hw->CRTC[21] = vd /* & 0xFF */;
411 	hw->CRTC[22] = (vt + 1) /* & 0xFF */;
412 	if (text) {
413 		if (ACCESS_FBINFO(devflags.textmode) == 1)
414 			hw->CRTC[23] = 0xC3;
415 		else
416 			hw->CRTC[23] = 0xA3;
417 		if (ACCESS_FBINFO(devflags.textmode) == 4)
418 			hw->CRTC[20] = 0x5F;
419 		else
420 			hw->CRTC[20] = 0x1F;
421 	} else
422 		hw->CRTC[23] = 0xC3;
423 	hw->CRTC[24] = lc;
424 	return 0;
425 };
426 
matroxfb_vgaHWrestore(WPMINFO2)427 void matroxfb_vgaHWrestore(WPMINFO2) {
428 	int i;
429 	struct matrox_hw_state * const hw = &ACCESS_FBINFO(hw);
430 	CRITFLAGS
431 
432 	DBG("vgaHWrestore")
433 
434 	dprintk(KERN_INFO "MiscOutReg: %02X\n", hw->MiscOutReg);
435 	dprintk(KERN_INFO "SEQ regs:   ");
436 	for (i = 0; i < 5; i++)
437 		dprintk("%02X:", hw->SEQ[i]);
438 	dprintk("\n");
439 	dprintk(KERN_INFO "GDC regs:   ");
440 	for (i = 0; i < 9; i++)
441 		dprintk("%02X:", hw->GCTL[i]);
442 	dprintk("\n");
443 	dprintk(KERN_INFO "CRTC regs: ");
444 	for (i = 0; i < 25; i++)
445 		dprintk("%02X:", hw->CRTC[i]);
446 	dprintk("\n");
447 	dprintk(KERN_INFO "ATTR regs: ");
448 	for (i = 0; i < 21; i++)
449 		dprintk("%02X:", hw->ATTR[i]);
450 	dprintk("\n");
451 
452 	CRITBEGIN
453 
454 	mga_inb(M_ATTR_RESET);
455 	mga_outb(M_ATTR_INDEX, 0);
456 	mga_outb(M_MISC_REG, hw->MiscOutReg);
457 	for (i = 1; i < 5; i++)
458 		mga_setr(M_SEQ_INDEX, i, hw->SEQ[i]);
459 	mga_setr(M_CRTC_INDEX, 17, hw->CRTC[17] & 0x7F);
460 	for (i = 0; i < 25; i++)
461 		mga_setr(M_CRTC_INDEX, i, hw->CRTC[i]);
462 	for (i = 0; i < 9; i++)
463 		mga_setr(M_GRAPHICS_INDEX, i, hw->GCTL[i]);
464 	for (i = 0; i < 21; i++) {
465 		mga_inb(M_ATTR_RESET);
466 		mga_outb(M_ATTR_INDEX, i);
467 		mga_outb(M_ATTR_INDEX, hw->ATTR[i]);
468 	}
469 	mga_outb(M_PALETTE_MASK, 0xFF);
470 	mga_outb(M_DAC_REG, 0x00);
471 	for (i = 0; i < 768; i++)
472 		mga_outb(M_DAC_VAL, hw->DACpal[i]);
473 	mga_inb(M_ATTR_RESET);
474 	mga_outb(M_ATTR_INDEX, 0x20);
475 
476 	CRITEND
477 }
478 
matroxfb_fastfont_init(struct matrox_fb_info * minfo)479 void matroxfb_fastfont_init(struct matrox_fb_info* minfo){
480 	unsigned int size;
481 
482 	size = ACCESS_FBINFO(fastfont.size);
483 	ACCESS_FBINFO(fastfont.size) = 0;
484 	if (size) {
485 		unsigned int end = ACCESS_FBINFO(video.len_usable);
486 
487 		if (size < end) {
488 			unsigned int start;
489 
490 			start = (end - size) & PAGE_MASK;
491 			if (start >= 0x00100000) {
492 				ACCESS_FBINFO(video.len_usable) = start;
493 				ACCESS_FBINFO(fastfont.mgabase) = start * 8;
494 				ACCESS_FBINFO(fastfont.vbase) = ACCESS_FBINFO(video.vbase);
495 				vaddr_add(&ACCESS_FBINFO(fastfont.vbase), start);
496 				ACCESS_FBINFO(fastfont.size) = end - start;
497 			}
498 		}
499 	}
500 }
501 
502 #ifndef FNTCHARCNT
503 #define FNTCHARCNT(fd)	(((int *)(fd))[-3])
504 #endif
505 
matrox_text_loadfont(WPMINFO struct display * p)506 int matrox_text_loadfont(WPMINFO struct display* p) {
507 	unsigned int fsize;
508 	unsigned int width;
509 	vaddr_t dst;
510 	unsigned int i;
511 	u_int8_t* font;
512 	CRITFLAGS
513 
514 	if (!p || !p->fontdata)
515 		return 0;
516 	width = fontwidth(p);
517 	fsize = p->userfont?FNTCHARCNT(p->fontdata):256;
518 
519 	dst = ACCESS_FBINFO(video.vbase);
520 	i = 2;
521 	font = (u_int8_t*)p->fontdata;
522 
523 	CRITBEGIN
524 
525 	mga_setr(M_SEQ_INDEX, 0x02, 0x04);
526 	while (fsize--) {
527 		int l;
528 
529 		for (l = 0; l < fontheight(p); l++) {
530 			mga_writeb(dst, i, *font++);
531 			if (fontwidth(p) > 8) font++;
532 			i += ACCESS_FBINFO(devflags.vgastep);
533 		}
534 		i += (32 - fontheight(p)) * ACCESS_FBINFO(devflags.vgastep);
535 	}
536 	mga_setr(M_SEQ_INDEX, 0x02, 0x03);
537 
538 	CRITEND
539 
540 	return 1;
541 }
542 
matroxfb_fastfont_tryset(WPMINFO struct display * p)543 int matroxfb_fastfont_tryset(WPMINFO struct display* p) {
544 	unsigned int fsize;
545 	unsigned int width;
546 	CRITFLAGS
547 
548 	if (!p || !p->fontdata)
549 		return 0;
550 	width = fontwidth(p);
551 	if (width > 32)
552 		return 0;
553 	fsize = (p->userfont?FNTCHARCNT(p->fontdata):256) * fontheight(p);
554 	if (((fsize * width + 31) / 32) * 4 > ACCESS_FBINFO(fastfont.size))
555 		return 0;
556 
557 	CRITBEGIN
558 
559 	mga_outl(M_OPMODE, M_OPMODE_8BPP);
560 	if (width <= 8) {
561 		if (width == 8)
562 			mga_memcpy_toio(ACCESS_FBINFO(fastfont.vbase), 0, p->fontdata, fsize);
563 		else {
564 			vaddr_t dst;
565 			unsigned int i;
566 			u_int8_t* font;
567 			u_int32_t mask, valid, reg;
568 
569 			dst = ACCESS_FBINFO(fastfont.vbase);
570 			font = (u_int8_t*)p->fontdata;
571 			mask = ~0 << (8 - width);
572 			valid = 0;
573 			reg = 0;
574 			i = 0;
575 			while (fsize--) {
576 				reg |= (*font++ & mask) << (8 - valid);
577 				valid += width;
578 				if (valid >= 8) {
579 					mga_writeb(dst, i++, reg >> 8);
580 					reg = reg << 8;
581 					valid -= 8;
582 				}
583 			}
584 			if (valid)
585 				mga_writeb(dst, i, reg >> 8);
586 		}
587 	} else if (width <= 16) {
588 		if (width == 16)
589 			mga_memcpy_toio(ACCESS_FBINFO(fastfont.vbase), 0, p->fontdata, fsize*2);
590 		else {
591 			vaddr_t dst;
592 			u_int16_t* font;
593 			u_int32_t mask, valid, reg;
594 			unsigned int i;
595 
596 			dst = ACCESS_FBINFO(fastfont.vbase);
597 			font = (u_int16_t*)p->fontdata;
598 			mask = ~0 << (16 - width);
599 			valid = 0;
600 			reg = 0;
601 			i = 0;
602 			while (fsize--) {
603 				reg |= (ntohs(*font++) & mask) << (16 - valid);
604 				valid += width;
605 				if (valid >= 16) {
606 					mga_writew(dst, i, htons(reg >> 16));
607 					i += 2;
608 					reg = reg << 16;
609 					valid -= 16;
610 				}
611 			}
612 			if (valid)
613 				mga_writew(dst, i, htons(reg >> 16));
614 		}
615 	} else {
616 		if (width == 32)
617 			mga_memcpy_toio(ACCESS_FBINFO(fastfont.vbase), 0, p->fontdata, fsize*4);
618 		else {
619 			vaddr_t dst;
620 			u_int32_t* font;
621 			u_int32_t mask, valid, reg;
622 			unsigned int i;
623 
624 			dst = ACCESS_FBINFO(fastfont.vbase);
625 			font = (u_int32_t*)p->fontdata;
626 			mask = ~0 << (32 - width);
627 			valid = 0;
628 			reg = 0;
629 			i = 0;
630 			while (fsize--) {
631 				reg |= (ntohl(*font) & mask) >> valid;
632 				valid += width;
633 				if (valid >= 32) {
634 					mga_writel(dst, i, htonl(reg));
635 					i += 4;
636 					valid -= 32;
637 					if (valid)
638 						reg = (ntohl(*font) & mask) << (width - valid);
639 					else
640 						reg = 0;
641 				}
642 				font++;
643 			}
644 			if (valid)
645 				mga_writel(dst, i, htonl(reg));
646 		}
647 	}
648 	mga_outl(M_OPMODE, ACCESS_FBINFO(accel.m_opmode));
649 
650 	CRITEND
651 
652 	return 1;
653 }
654 
get_pins(unsigned char * pins,struct matrox_bios * bd)655 static void get_pins(unsigned char* pins, struct matrox_bios* bd) {
656 	unsigned int b0 = readb(pins);
657 
658 	if (b0 == 0x2E && readb(pins+1) == 0x41) {
659 		unsigned int pins_len = readb(pins+2);
660 		unsigned int i;
661 		unsigned char cksum;
662 		unsigned char* dst = bd->pins;
663 
664 		if (pins_len < 3 || pins_len > 128) {
665 			return;
666 		}
667 		*dst++ = 0x2E;
668 		*dst++ = 0x41;
669 		*dst++ = pins_len;
670 		cksum = 0x2E + 0x41 + pins_len;
671 		for (i = 3; i < pins_len; i++) {
672 			cksum += *dst++ = readb(pins+i);
673 		}
674 		if (cksum) {
675 			return;
676 		}
677 		bd->pins_len = pins_len;
678 	} else if (b0 == 0x40 && readb(pins+1) == 0x00) {
679 		unsigned int i;
680 		unsigned char* dst = bd->pins;
681 
682 		*dst++ = 0x40;
683 		*dst++ = 0;
684 		for (i = 2; i < 0x40; i++) {
685 			*dst++ = readb(pins+i);
686 		}
687 		bd->pins_len = 0x40;
688 	}
689 }
690 
get_bios_version(unsigned char * vbios,struct matrox_bios * bd)691 static void get_bios_version(unsigned char* vbios, struct matrox_bios* bd) {
692 	unsigned int pcir_offset;
693 
694 	pcir_offset = readb(vbios + 24) | (readb(vbios + 25) << 8);
695 	if (pcir_offset >= 26 && pcir_offset < 0xFFE0 &&
696 	    readb(vbios + pcir_offset    ) == 'P' &&
697 	    readb(vbios + pcir_offset + 1) == 'C' &&
698 	    readb(vbios + pcir_offset + 2) == 'I' &&
699 	    readb(vbios + pcir_offset + 3) == 'R') {
700 		unsigned char h;
701 
702 		h = readb(vbios + pcir_offset + 0x12);
703 		bd->version.vMaj = (h >> 4) & 0xF;
704 		bd->version.vMin = h & 0xF;
705 		bd->version.vRev = readb(vbios + pcir_offset + 0x13);
706 	} else {
707 		unsigned char h;
708 
709 		h = readb(vbios + 5);
710 		bd->version.vMaj = (h >> 4) & 0xF;
711 		bd->version.vMin = h & 0xF;
712 		bd->version.vRev = 0;
713 	}
714 }
715 
get_bios_output(unsigned char * vbios,struct matrox_bios * bd)716 static void get_bios_output(unsigned char* vbios, struct matrox_bios* bd) {
717 	unsigned char b;
718 
719 	b = readb(vbios + 0x7FF1);
720 	if (b == 0xFF) {
721 		b = 0;
722 	}
723 	bd->output.state = b;
724 }
725 
get_bios_tvout(unsigned char * vbios,struct matrox_bios * bd)726 static void get_bios_tvout(unsigned char* vbios, struct matrox_bios* bd) {
727 	unsigned int i;
728 
729 	/* Check for 'IBM .*(V....TVO' string - it means TVO BIOS */
730 	bd->output.tvout = 0;
731 	if (readb(vbios + 0x1D) != 'I' ||
732 	    readb(vbios + 0x1E) != 'B' ||
733 	    readb(vbios + 0x1F) != 'M' ||
734 	    readb(vbios + 0x20) != ' ') {
735 	    	return;
736 	}
737 	for (i = 0x2D; i < 0x2D + 128; i++) {
738 		unsigned char b = readb(vbios + i);
739 
740 		if (b == '(' && readb(vbios + i + 1) == 'V') {
741 			if (readb(vbios + i + 6) == 'T' &&
742 			    readb(vbios + i + 7) == 'V' &&
743 			    readb(vbios + i + 8) == 'O') {
744 				bd->output.tvout = 1;
745 			}
746 			return;
747 		}
748 		if (b == 0)
749 			break;
750 	}
751 }
752 
parse_bios(unsigned char * vbios,struct matrox_bios * bd)753 static void parse_bios(unsigned char* vbios, struct matrox_bios* bd) {
754 	unsigned int pins_offset;
755 
756 	if (readb(vbios) != 0x55 || readb(vbios + 1) != 0xAA) {
757 		return;
758 	}
759 	bd->bios_valid = 1;
760 	get_bios_version(vbios, bd);
761 	get_bios_output(vbios, bd);
762 	get_bios_tvout(vbios, bd);
763 	pins_offset = readb(vbios + 0x7FFC) | (readb(vbios + 0x7FFD) << 8);
764 	if (pins_offset <= 0xFF80) {
765 		get_pins(vbios + pins_offset, bd);
766 	}
767 }
768 
769 #define get_u16(x) (le16_to_cpu(get_unaligned((__u16*)(x))))
770 #define get_u32(x) (le32_to_cpu(get_unaligned((__u32*)(x))))
parse_pins1(WPMINFO const struct matrox_bios * bd)771 static int parse_pins1(WPMINFO const struct matrox_bios* bd) {
772 	unsigned int maxdac;
773 
774 	switch (bd->pins[22]) {
775 		case 0:		maxdac = 175000; break;
776 		case 1:		maxdac = 220000; break;
777 		default:	maxdac = 240000; break;
778 	}
779 	if (get_u16(bd->pins + 24)) {
780 		maxdac = get_u16(bd->pins + 24) * 10;
781 	}
782 	MINFO->limits.pixel.vcomax = maxdac;
783 	MINFO->values.pll.system = get_u16(bd->pins + 28) ? get_u16(bd->pins + 28) * 10 : 50000;
784 	/* ignore 4MB, 8MB, module clocks */
785 	MINFO->features.pll.ref_freq = 14318;
786 	MINFO->values.reg.mctlwtst	= 0x00030101;
787 	return 0;
788 }
789 
default_pins1(WPMINFO2)790 static void default_pins1(WPMINFO2) {
791 	/* Millennium */
792 	MINFO->limits.pixel.vcomax	= 220000;
793 	MINFO->values.pll.system	=  50000;
794 	MINFO->features.pll.ref_freq	=  14318;
795 	MINFO->values.reg.mctlwtst	= 0x00030101;
796 }
797 
parse_pins2(WPMINFO const struct matrox_bios * bd)798 static int parse_pins2(WPMINFO const struct matrox_bios* bd) {
799 	MINFO->limits.pixel.vcomax	=
800 	MINFO->limits.system.vcomax	= (bd->pins[41] == 0xFF) ? 230000 : ((bd->pins[41] + 100) * 1000);
801 	MINFO->values.reg.mctlwtst	= ((bd->pins[51] & 0x01) ? 0x00000001 : 0) |
802 					  ((bd->pins[51] & 0x02) ? 0x00000100 : 0) |
803 					  ((bd->pins[51] & 0x04) ? 0x00010000 : 0) |
804 					  ((bd->pins[51] & 0x08) ? 0x00020000 : 0);
805 	MINFO->values.pll.system	= (bd->pins[43] == 0xFF) ? 50000 : ((bd->pins[43] + 100) * 1000);
806 	MINFO->features.pll.ref_freq	= 14318;
807 	return 0;
808 }
809 
default_pins2(WPMINFO2)810 static void default_pins2(WPMINFO2) {
811 	/* Millennium II, Mystique */
812 	MINFO->limits.pixel.vcomax	=
813 	MINFO->limits.system.vcomax	= 230000;
814 	MINFO->values.reg.mctlwtst	= 0x00030101;
815 	MINFO->values.pll.system	=  50000;
816 	MINFO->features.pll.ref_freq	=  14318;
817 }
818 
parse_pins3(WPMINFO const struct matrox_bios * bd)819 static int parse_pins3(WPMINFO const struct matrox_bios* bd) {
820 	MINFO->limits.pixel.vcomax	=
821 	MINFO->limits.system.vcomax	= (bd->pins[36] == 0xFF) ? 230000			: ((bd->pins[36] + 100) * 1000);
822 	MINFO->values.reg.mctlwtst	= get_u32(bd->pins + 48) == 0xFFFFFFFF ? 0x01250A21	: get_u32(bd->pins + 48);
823 	/* memory config */
824 	MINFO->values.reg.memrdbk	= ((bd->pins[57] << 21) & 0x1E000000) |
825 					  ((bd->pins[57] << 22) & 0x00C00000) |
826 					  ((bd->pins[56] <<  1) & 0x000001E0) |
827 					  ( bd->pins[56]        & 0x0000000F);
828 	MINFO->values.reg.opt		= (bd->pins[54] & 7) << 10;
829 	MINFO->values.reg.opt2		= bd->pins[58] << 12;
830 	MINFO->features.pll.ref_freq	= (bd->pins[52] & 0x20) ? 14318 : 27000;
831 	return 0;
832 }
833 
default_pins3(WPMINFO2)834 static void default_pins3(WPMINFO2) {
835 	/* G100, G200 */
836 	MINFO->limits.pixel.vcomax	=
837 	MINFO->limits.system.vcomax	= 230000;
838 	MINFO->values.reg.mctlwtst	= 0x01250A21;
839 	MINFO->values.reg.memrdbk	= 0x00000000;
840 	MINFO->values.reg.opt		= 0x00000C00;
841 	MINFO->values.reg.opt2		= 0x00000000;
842 	MINFO->features.pll.ref_freq	=  27000;
843 }
844 
parse_pins4(WPMINFO const struct matrox_bios * bd)845 static int parse_pins4(WPMINFO const struct matrox_bios* bd) {
846 	MINFO->limits.pixel.vcomax	= (bd->pins[ 39] == 0xFF) ? 230000			: bd->pins[ 39] * 4000;
847 	MINFO->limits.system.vcomax	= (bd->pins[ 38] == 0xFF) ? MINFO->limits.pixel.vcomax	: bd->pins[ 38] * 4000;
848 	MINFO->values.reg.mctlwtst	= get_u32(bd->pins + 71);
849 	MINFO->values.reg.memrdbk	= ((bd->pins[87] << 21) & 0x1E000000) |
850 					  ((bd->pins[87] << 22) & 0x00C00000) |
851 					  ((bd->pins[86] <<  1) & 0x000001E0) |
852 					  ( bd->pins[86]        & 0x0000000F);
853 	MINFO->values.reg.opt		= ((bd->pins[53] << 15) & 0x00400000) |
854 					  ((bd->pins[53] << 22) & 0x10000000) |
855 					  ((bd->pins[53] <<  7) & 0x00001C00);
856 	MINFO->values.reg.opt3		= get_u32(bd->pins + 67);
857 	MINFO->values.pll.system	= (bd->pins[ 65] == 0xFF) ? 200000 			: bd->pins[ 65] * 4000;
858 	MINFO->features.pll.ref_freq	= (bd->pins[ 92] & 0x01) ? 14318 : 27000;
859 	return 0;
860 }
861 
default_pins4(WPMINFO2)862 static void default_pins4(WPMINFO2) {
863 	/* G400 */
864 	MINFO->limits.pixel.vcomax	=
865 	MINFO->limits.system.vcomax	= 252000;
866 	MINFO->values.reg.mctlwtst	= 0x04A450A1;
867 	MINFO->values.reg.memrdbk	= 0x000000E7;
868 	MINFO->values.reg.opt		= 0x10000400;
869 	MINFO->values.reg.opt3		= 0x0190A419;
870 	MINFO->values.pll.system	= 200000;
871 	MINFO->features.pll.ref_freq	= 27000;
872 }
873 
parse_pins5(WPMINFO const struct matrox_bios * bd)874 static int parse_pins5(WPMINFO const struct matrox_bios* bd) {
875 	unsigned int mult;
876 
877 	mult = bd->pins[4]?8000:6000;
878 
879 	MINFO->limits.pixel.vcomax	= (bd->pins[ 38] == 0xFF) ? 600000			: bd->pins[ 38] * mult;
880 	MINFO->limits.system.vcomax	= (bd->pins[ 36] == 0xFF) ? MINFO->limits.pixel.vcomax	: bd->pins[ 36] * mult;
881 	MINFO->limits.video.vcomax	= (bd->pins[ 37] == 0xFF) ? MINFO->limits.system.vcomax	: bd->pins[ 37] * mult;
882 	MINFO->limits.pixel.vcomin	= (bd->pins[123] == 0xFF) ? 256000			: bd->pins[123] * mult;
883 	MINFO->limits.system.vcomin	= (bd->pins[121] == 0xFF) ? MINFO->limits.pixel.vcomin	: bd->pins[121] * mult;
884 	MINFO->limits.video.vcomin	= (bd->pins[122] == 0xFF) ? MINFO->limits.system.vcomin	: bd->pins[122] * mult;
885 	MINFO->values.pll.system	=
886 	MINFO->values.pll.video		= (bd->pins[ 92] == 0xFF) ? 284000			: bd->pins[ 92] * 4000;
887 	MINFO->values.reg.opt		= get_u32(bd->pins+ 48);
888 	MINFO->values.reg.opt2		= get_u32(bd->pins+ 52);
889 	MINFO->values.reg.opt3		= get_u32(bd->pins+ 94);
890 	MINFO->values.reg.mctlwtst	= get_u32(bd->pins+ 98);
891 	MINFO->values.reg.memmisc	= get_u32(bd->pins+102);
892 	MINFO->values.reg.memrdbk	= get_u32(bd->pins+106);
893 	MINFO->features.pll.ref_freq	= (bd->pins[110] & 0x01) ? 14318 : 27000;
894 	MINFO->values.memory.ddr	= (bd->pins[114] & 0x60) == 0x20;
895 	MINFO->values.memory.dll	= (bd->pins[115] & 0x02) != 0;
896 	MINFO->values.memory.emrswen	= (bd->pins[115] & 0x01) != 0;
897 	MINFO->values.reg.maccess	= MINFO->values.memory.emrswen ? 0x00004000 : 0x00000000;
898 	if (bd->pins[115] & 4) {
899 		MINFO->values.reg.mctlwtst_core = MINFO->values.reg.mctlwtst;
900 	} else {
901 		u_int32_t wtst_xlat[] = { 0, 1, 5, 6, 7, 5, 2, 3 };
902 		MINFO->values.reg.mctlwtst_core = (MINFO->values.reg.mctlwtst & ~7) |
903 		                                  wtst_xlat[MINFO->values.reg.mctlwtst & 7];
904 	}
905 	return 0;
906 }
907 
default_pins5(WPMINFO2)908 static void default_pins5(WPMINFO2) {
909 	/* Mine 16MB G450 with SDRAM DDR */
910 	MINFO->limits.pixel.vcomax	=
911 	MINFO->limits.system.vcomax	=
912 	MINFO->limits.video.vcomax	= 600000;
913 	MINFO->limits.pixel.vcomin	=
914 	MINFO->limits.system.vcomin	=
915 	MINFO->limits.video.vcomin	= 256000;
916 	MINFO->values.pll.system	=
917 	MINFO->values.pll.video		= 284000;
918 	MINFO->values.reg.opt		= 0x404A1160;
919 	MINFO->values.reg.opt2		= 0x0000AC00;
920 	MINFO->values.reg.opt3		= 0x0090A409;
921 	MINFO->values.reg.mctlwtst_core	=
922 	MINFO->values.reg.mctlwtst	= 0x0C81462B;
923 	MINFO->values.reg.memmisc	= 0x80000004;
924 	MINFO->values.reg.memrdbk	= 0x01001103;
925 	MINFO->features.pll.ref_freq	= 27000;
926 	MINFO->values.memory.ddr	= 1;
927 	MINFO->values.memory.dll	= 1;
928 	MINFO->values.memory.emrswen	= 1;
929 	MINFO->values.reg.maccess	= 0x00004000;
930 }
931 
matroxfb_set_limits(WPMINFO const struct matrox_bios * bd)932 static int matroxfb_set_limits(WPMINFO const struct matrox_bios* bd) {
933 	unsigned int pins_version;
934 	static const unsigned int pinslen[] = { 64, 64, 64, 128, 128 };
935 
936 	switch (ACCESS_FBINFO(chip)) {
937 		case MGA_2064:	default_pins1(PMINFO2); break;
938 		case MGA_2164:
939 		case MGA_1064:
940 		case MGA_1164:	default_pins2(PMINFO2); break;
941 		case MGA_G100:
942 		case MGA_G200:	default_pins3(PMINFO2); break;
943 		case MGA_G400:	default_pins4(PMINFO2); break;
944 		case MGA_G450:
945 		case MGA_G550:	default_pins5(PMINFO2); break;
946 	}
947 	if (!bd->bios_valid) {
948 		printk(KERN_INFO "matroxfb: Your Matrox device does not have BIOS\n");
949 		return -1;
950 	}
951 	if (bd->pins_len < 64) {
952 		printk(KERN_INFO "matroxfb: BIOS on your Matrox device does not contain powerup info\n");
953 		return -1;
954 	}
955 	if (bd->pins[0] == 0x2E && bd->pins[1] == 0x41) {
956 		pins_version = bd->pins[5];
957 		if (pins_version < 2 || pins_version > 5) {
958 			printk(KERN_INFO "matroxfb: Unknown version (%u) of powerup info\n", pins_version);
959 			return -1;
960 		}
961 	} else {
962 		pins_version = 1;
963 	}
964 	if (bd->pins_len != pinslen[pins_version - 1]) {
965 		printk(KERN_INFO "matroxfb: Invalid powerup info\n");
966 		return -1;
967 	}
968 	switch (pins_version) {
969 		case 1:
970 			return parse_pins1(PMINFO bd);
971 		case 2:
972 			return parse_pins2(PMINFO bd);
973 		case 3:
974 			return parse_pins3(PMINFO bd);
975 		case 4:
976 			return parse_pins4(PMINFO bd);
977 		case 5:
978 			return parse_pins5(PMINFO bd);
979 		default:
980 			printk(KERN_DEBUG "matroxfb: Powerup info version %u is not yet supported\n", pins_version);
981 			return -1;
982 	}
983 }
984 
matroxfb_read_pins(WPMINFO2)985 void matroxfb_read_pins(WPMINFO2) {
986 	u32 opt;
987 	u32 biosbase;
988 	u32 fbbase;
989 	struct pci_dev* pdev = ACCESS_FBINFO(pcidev);
990 
991 	memset(&ACCESS_FBINFO(bios), 0, sizeof(ACCESS_FBINFO(bios)));
992 	pci_read_config_dword(pdev, PCI_OPTION_REG, &opt);
993 	pci_write_config_dword(pdev, PCI_OPTION_REG, opt | PCI_OPTION_ENABLE_ROM);
994 	pci_read_config_dword(pdev, PCI_ROM_ADDRESS, &biosbase);
995 	pci_read_config_dword(pdev, ACCESS_FBINFO(devflags.fbResource), &fbbase);
996 	pci_write_config_dword(pdev, PCI_ROM_ADDRESS, (fbbase & PCI_ROM_ADDRESS_MASK) | PCI_ROM_ADDRESS_ENABLE);
997 	parse_bios(vaddr_va(ACCESS_FBINFO(video).vbase), &ACCESS_FBINFO(bios));
998 	pci_write_config_dword(pdev, PCI_ROM_ADDRESS, biosbase);
999 	pci_write_config_dword(pdev, PCI_OPTION_REG, opt);
1000 #ifdef CONFIG_X86
1001 	if (!ACCESS_FBINFO(bios).bios_valid) {
1002 		unsigned char* b;
1003 
1004 		b = ioremap(0x000C0000, 65536);
1005 		if (!b) {
1006 			printk(KERN_INFO "matroxfb: Unable to map legacy BIOS\n");
1007 		} else {
1008 			unsigned int ven = readb(b+0x64+0) | (readb(b+0x64+1) << 8);
1009 			unsigned int dev = readb(b+0x64+2) | (readb(b+0x64+3) << 8);
1010 
1011 			if (ven != pdev->vendor || dev != pdev->device) {
1012 				printk(KERN_INFO "matroxfb: Legacy BIOS is for %04X:%04X, while this device is %04X:%04X\n",
1013 					ven, dev, pdev->vendor, pdev->device);
1014 			} else {
1015 				parse_bios(b, &ACCESS_FBINFO(bios));
1016 			}
1017 			iounmap(b);
1018 		}
1019 	}
1020 #endif
1021 	matroxfb_set_limits(PMINFO &ACCESS_FBINFO(bios));
1022 }
1023 
1024 EXPORT_SYMBOL(matroxfb_DAC_in);
1025 EXPORT_SYMBOL(matroxfb_DAC_out);
1026 EXPORT_SYMBOL(matroxfb_var2my);
1027 EXPORT_SYMBOL(matroxfb_PLL_calcclock);
1028 #ifndef CONFIG_FB_MATROX_MULTIHEAD
1029 struct matrox_fb_info matroxfb_global_mxinfo;
1030 EXPORT_SYMBOL(matroxfb_global_mxinfo);
1031 #endif
1032 EXPORT_SYMBOL(matrox_text_loadfont);	/* for matroxfb_accel */
1033 EXPORT_SYMBOL(matroxfb_createcursorshape);	/* accel, DAC1064, Ti3026 */
1034 EXPORT_SYMBOL(matroxfb_fastfont_tryset);	/* accel */
1035 EXPORT_SYMBOL(matroxfb_fastfont_init);		/* DAC1064, Ti3026 */
1036 EXPORT_SYMBOL(matroxfb_vgaHWinit);		/* DAC1064, Ti3026 */
1037 EXPORT_SYMBOL(matroxfb_vgaHWrestore);		/* DAC1064, Ti3026 */
1038 EXPORT_SYMBOL(matroxfb_read_pins);
1039 
1040 MODULE_AUTHOR("(c) 1999-2002 Petr Vandrovec <vandrove@vc.cvut.cz>");
1041 MODULE_DESCRIPTION("Miscellaneous support for Matrox video cards");
1042 MODULE_LICENSE("GPL");
1043