1 /* $Id: aty128fb.c,v 1.1.1.1.36.1 1999/12/11 09:03:05 Exp $
2 * linux/drivers/video/aty128fb.c -- Frame buffer device for ATI Rage128
3 *
4 * Copyright (C) 1999-2000, Brad Douglas <brad@neruo.com>
5 * Copyright (C) 1999, Anthony Tong <atong@uiuc.edu>
6 *
7 * Ani Joshi / Jeff Garzik
8 * - Code cleanup
9 *
10 * Michel D�nzer <michdaen@iiic.ethz.ch>
11 * - 15/16 bit cleanup
12 * - fix panning
13 *
14 * Benjamin Herrenschmidt
15 * - pmac-specific PM stuff
16 *
17 * Andreas Hundt <andi@convergence.de>
18 * - FB_ACTIVATE fixes
19 *
20 * Based off of Geert's atyfb.c and vfb.c.
21 *
22 * TODO:
23 * - monitor sensing (DDC)
24 * - virtual display
25 * - other platform support (only ppc/x86 supported)
26 * - hardware cursor support
27 * - ioctl()'s
28 *
29 * Please cc: your patches to brad@neruo.com.
30 */
31
32 /*
33 * A special note of gratitude to ATI's devrel for providing documentation,
34 * example code and hardware. Thanks Nitya. -atong and brad
35 */
36
37
38 #include <linux/config.h>
39 #include <linux/module.h>
40 #include <linux/kernel.h>
41 #include <linux/errno.h>
42 #include <linux/string.h>
43 #include <linux/mm.h>
44 #include <linux/tty.h>
45 #include <linux/slab.h>
46 #include <linux/vmalloc.h>
47 #include <linux/delay.h>
48 #include <linux/interrupt.h>
49 #include <asm/uaccess.h>
50 #include <linux/fb.h>
51 #include <linux/init.h>
52 #include <linux/selection.h>
53 #include <linux/console.h>
54 #include <linux/pci.h>
55 #include <linux/ioport.h>
56 #include <asm/io.h>
57
58 #ifdef CONFIG_PPC
59 #include <asm/prom.h>
60 #include <asm/pci-bridge.h>
61 #include <video/macmodes.h>
62 #ifdef CONFIG_NVRAM
63 #include <linux/nvram.h>
64 #endif
65 #endif
66
67 #ifdef CONFIG_ADB_PMU
68 #include <linux/adb.h>
69 #include <linux/pmu.h>
70 #endif
71
72 #ifdef CONFIG_PMAC_BACKLIGHT
73 #include <asm/backlight.h>
74 #endif
75
76 #ifdef CONFIG_FB_COMPAT_XPMAC
77 #include <asm/vc_ioctl.h>
78 #endif
79 #ifdef CONFIG_BOOTX_TEXT
80 #include <asm/btext.h>
81 #endif /* CONFIG_BOOTX_TEXT */
82
83 #include <video/fbcon.h>
84 #include <video/fbcon-cfb8.h>
85 #include <video/fbcon-cfb16.h>
86 #include <video/fbcon-cfb24.h>
87 #include <video/fbcon-cfb32.h>
88
89 #ifdef CONFIG_MTRR
90 #include <asm/mtrr.h>
91 #endif
92
93 #include "aty128.h"
94
95 /* Debug flag */
96 #undef DEBUG
97
98 #ifdef DEBUG
99 #define DBG(fmt, args...) printk(KERN_DEBUG "aty128fb: %s " fmt, __FUNCTION__, ##args);
100 #else
101 #define DBG(fmt, args...)
102 #endif
103
104 #ifndef CONFIG_PPC
105 /* default mode */
106 static struct fb_var_screeninfo default_var __initdata = {
107 /* 640x480, 60 Hz, Non-Interlaced (25.175 MHz dotclock) */
108 640, 480, 640, 480, 0, 0, 8, 0,
109 {0, 8, 0}, {0, 8, 0}, {0, 8, 0}, {0, 0, 0},
110 0, 0, -1, -1, 0, 39722, 48, 16, 33, 10, 96, 2,
111 0, FB_VMODE_NONINTERLACED
112 };
113
114 #else /* CONFIG_PPC */
115 /* default to 1024x768 at 75Hz on PPC - this will work
116 * on the iMac, the usual 640x480 @ 60Hz doesn't. */
117 static struct fb_var_screeninfo default_var = {
118 /* 1024x768, 75 Hz, Non-Interlaced (78.75 MHz dotclock) */
119 1024, 768, 1024, 768, 0, 0, 8, 0,
120 {0, 8, 0}, {0, 8, 0}, {0, 8, 0}, {0, 0, 0},
121 0, 0, -1, -1, 0, 12699, 160, 32, 28, 1, 96, 3,
122 FB_SYNC_HOR_HIGH_ACT|FB_SYNC_VERT_HIGH_ACT, FB_VMODE_NONINTERLACED
123 };
124 #endif /* CONFIG_PPC */
125
126 /* default modedb mode */
127 /* 640x480, 60 Hz, Non-Interlaced (25.172 MHz dotclock) */
128 static struct fb_videomode defaultmode __initdata = {
129 refresh: 60,
130 xres: 640,
131 yres: 480,
132 pixclock: 39722,
133 left_margin: 48,
134 right_margin: 16,
135 upper_margin: 33,
136 lower_margin: 10,
137 hsync_len: 96,
138 vsync_len: 2,
139 sync: 0,
140 vmode: FB_VMODE_NONINTERLACED
141 };
142
143 /* struct to hold chip description information */
144 struct aty128_chip_info {
145 const char *name;
146 unsigned short device;
147 int chip_gen;
148 };
149
150 /* Chip generations */
151 enum {
152 rage_128,
153 rage_128_pro,
154 rage_M3
155 };
156
157 /* supported Rage128 chipsets */
158 static struct aty128_chip_info aty128_pci_probe_list[] __initdata =
159 {
160 {"Rage128 RE (PCI)", PCI_DEVICE_ID_ATI_RAGE128_RE, rage_128},
161 {"Rage128 RF (AGP)", PCI_DEVICE_ID_ATI_RAGE128_RF, rage_128},
162 {"Rage128 RK (PCI)", PCI_DEVICE_ID_ATI_RAGE128_RK, rage_128},
163 {"Rage128 RL (AGP)", PCI_DEVICE_ID_ATI_RAGE128_RL, rage_128},
164 {"Rage128 Pro PF (AGP)", PCI_DEVICE_ID_ATI_RAGE128_PF, rage_128_pro},
165 {"Rage128 Pro PR (PCI)", PCI_DEVICE_ID_ATI_RAGE128_PR, rage_128_pro},
166 {"Rage128 Pro TR (AGP)", PCI_DEVICE_ID_ATI_RAGE128_U3, rage_128_pro},
167 {"Rage128 Pro TF (AGP)", PCI_DEVICE_ID_ATI_RAGE128_U1, rage_128_pro},
168 {"Rage Mobility M3 (PCI)", PCI_DEVICE_ID_ATI_RAGE128_LE, rage_M3},
169 {"Rage Mobility M3 (AGP)", PCI_DEVICE_ID_ATI_RAGE128_LF, rage_M3},
170 {NULL, 0, rage_128}
171 };
172
173 /* packed BIOS settings */
174 #ifndef CONFIG_PPC
175 typedef struct {
176 u8 clock_chip_type;
177 u8 struct_size;
178 u8 accelerator_entry;
179 u8 VGA_entry;
180 u16 VGA_table_offset;
181 u16 POST_table_offset;
182 u16 XCLK;
183 u16 MCLK;
184 u8 num_PLL_blocks;
185 u8 size_PLL_blocks;
186 u16 PCLK_ref_freq;
187 u16 PCLK_ref_divider;
188 u32 PCLK_min_freq;
189 u32 PCLK_max_freq;
190 u16 MCLK_ref_freq;
191 u16 MCLK_ref_divider;
192 u32 MCLK_min_freq;
193 u32 MCLK_max_freq;
194 u16 XCLK_ref_freq;
195 u16 XCLK_ref_divider;
196 u32 XCLK_min_freq;
197 u32 XCLK_max_freq;
198 } __attribute__ ((packed)) PLL_BLOCK;
199 #endif /* !CONFIG_PPC */
200
201 /* onboard memory information */
202 struct aty128_meminfo {
203 u8 ML;
204 u8 MB;
205 u8 Trcd;
206 u8 Trp;
207 u8 Twr;
208 u8 CL;
209 u8 Tr2w;
210 u8 LoopLatency;
211 u8 DspOn;
212 u8 Rloop;
213 const char *name;
214 };
215
216 /* various memory configurations */
217 static const struct aty128_meminfo sdr_128 =
218 { 4, 4, 3, 3, 1, 3, 1, 16, 30, 16, "128-bit SDR SGRAM (1:1)" };
219 static const struct aty128_meminfo sdr_64 =
220 { 4, 8, 3, 3, 1, 3, 1, 17, 46, 17, "64-bit SDR SGRAM (1:1)" };
221 static const struct aty128_meminfo sdr_sgram =
222 { 4, 4, 1, 2, 1, 2, 1, 16, 24, 16, "64-bit SDR SGRAM (2:1)" };
223 static const struct aty128_meminfo ddr_sgram =
224 { 4, 4, 3, 3, 2, 3, 1, 16, 31, 16, "64-bit DDR SGRAM" };
225
226 static const char *aty128fb_name = "ATY Rage128";
227 static char fontname[40] __initdata = { 0 };
228
229 static int noaccel __initdata = 0;
230 static char *font __initdata = NULL;
231 static char *mode __initdata = NULL;
232 static int nomtrr __initdata = 0;
233
234 static char *mode_option __initdata = NULL;
235
236 #ifdef CONFIG_PPC
237 static int default_vmode __initdata = VMODE_1024_768_60;
238 static int default_cmode __initdata = CMODE_8;
239 #endif
240
241 #ifdef CONFIG_PMAC_PBOOK
242 static int default_crt_on __initdata = 0;
243 static int default_lcd_on __initdata = 1;
244 #endif
245
246 #ifdef CONFIG_MTRR
247 static int mtrr = 1;
248 #endif
249
250 /* PLL constants */
251 struct aty128_constants {
252 u32 dotclock;
253 u32 ppll_min;
254 u32 ppll_max;
255 u32 ref_divider;
256 u32 xclk;
257 u32 fifo_width;
258 u32 fifo_depth;
259 };
260
261 struct aty128_crtc {
262 u32 gen_cntl;
263 u32 ext_cntl;
264 u32 h_total, h_sync_strt_wid;
265 u32 v_total, v_sync_strt_wid;
266 u32 pitch;
267 u32 offset, offset_cntl;
268 u32 xoffset, yoffset;
269 u32 vxres, vyres;
270 u32 depth, bpp;
271 };
272
273 struct aty128_pll {
274 u32 post_divider;
275 u32 feedback_divider;
276 u32 vclk;
277 };
278
279 struct aty128_ddafifo {
280 u32 dda_config;
281 u32 dda_on_off;
282 };
283
284 /* register values for a specific mode */
285 struct aty128fb_par {
286 struct aty128_crtc crtc;
287 struct aty128_pll pll;
288 struct aty128_ddafifo fifo_reg;
289 u32 accel_flags;
290 };
291
292 struct fb_info_aty128 {
293 struct fb_info fb_info;
294 struct fb_info_aty128 *next;
295 struct aty128_constants constants; /* PLL and others */
296 unsigned long regbase_phys; /* physical mmio */
297 void *regbase; /* remapped mmio */
298 unsigned long frame_buffer_phys; /* physical fb memory */
299 void *frame_buffer; /* remaped framebuffer */
300 u32 vram_size; /* onboard video ram */
301 int chip_gen;
302 const struct aty128_meminfo *mem; /* onboard mem info */
303 struct aty128fb_par default_par, current_par;
304 struct display disp;
305 struct { u8 red, green, blue, pad; } palette[256];
306 union {
307 #ifdef FBCON_HAS_CFB16
308 u16 cfb16[16];
309 #endif
310 #ifdef FBCON_HAS_CFB24
311 u32 cfb24[16];
312 #endif
313 #ifdef FBCON_HAS_CFB32
314 u32 cfb32[16];
315 #endif
316 } fbcon_cmap;
317 #ifdef CONFIG_PCI
318 struct pci_dev *pdev;
319 #endif
320 #ifdef CONFIG_MTRR
321 struct { int vram; int vram_valid; } mtrr;
322 #endif
323 int currcon;
324 int blitter_may_be_busy;
325 int fifo_slots; /* free slots in FIFO (64 max) */
326 #ifdef CONFIG_PMAC_PBOOK
327 unsigned char *save_framebuffer;
328 int pm_reg;
329 int crt_on, lcd_on;
330 u32 save_lcd_gen_cntl;
331 #endif
332 };
333
334 static struct fb_info_aty128 *board_list = NULL;
335
336 #ifdef CONFIG_PMAC_PBOOK
337 int aty128_sleep_notify(struct pmu_sleep_notifier *self, int when);
338 static struct pmu_sleep_notifier aty128_sleep_notifier = {
339 aty128_sleep_notify, SLEEP_LEVEL_VIDEO,
340 };
341 #endif
342
343 #define round_div(n, d) ((n+(d/2))/d)
344
345 /*
346 * Interface used by the world
347 */
348
349 int aty128fb_setup(char *options);
350
351 static int aty128fb_get_fix(struct fb_fix_screeninfo *fix, int con,
352 struct fb_info *info);
353 static int aty128fb_get_var(struct fb_var_screeninfo *var, int con,
354 struct fb_info *info);
355 static int aty128fb_set_var(struct fb_var_screeninfo *var, int con,
356 struct fb_info *info);
357 static int aty128fb_get_cmap(struct fb_cmap *cmap, int kspc, int con,
358 struct fb_info *info);
359 static int aty128fb_set_cmap(struct fb_cmap *cmap, int kspc, int con,
360 struct fb_info *info);
361 static int aty128fb_pan_display(struct fb_var_screeninfo *var, int con,
362 struct fb_info *fb);
363 static int aty128fb_ioctl(struct inode *inode, struct file *file, u_int cmd,
364 u_long arg, int con, struct fb_info *info);
365 static int aty128fb_rasterimg(struct fb_info *info, int start);
366
367
368 /*
369 * Interface to the low level console driver
370 */
371
372 int aty128fb_init(void);
373 static int aty128fbcon_switch(int con, struct fb_info *fb);
374 static void aty128fbcon_blank(int blank, struct fb_info *fb);
375
376 /*
377 * Internal routines
378 */
379
380 static void aty128_encode_fix(struct fb_fix_screeninfo *fix,
381 struct aty128fb_par *par,
382 const struct fb_info_aty128 *info);
383 static void aty128_set_dispsw(struct display *disp,
384 struct fb_info_aty128 *info, int bpp, int accel);
385 static int aty128_getcolreg(u_int regno, u_int *red, u_int *green, u_int *blue,
386 u_int *transp, struct fb_info *info);
387 static int aty128_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
388 u_int transp, struct fb_info *info);
389 static void do_install_cmap(int con, struct fb_info *info);
390 static int aty128_encode_var(struct fb_var_screeninfo *var,
391 const struct aty128fb_par *par,
392 const struct fb_info_aty128 *info);
393 static int aty128_decode_var(struct fb_var_screeninfo *var,
394 struct aty128fb_par *par,
395 const struct fb_info_aty128 *info);
396 static int aty128_pci_register(struct pci_dev *pdev,
397 const struct aty128_chip_info *aci);
398 static struct fb_info_aty128 *aty128_board_list_add(struct fb_info_aty128
399 *board_list, struct fb_info_aty128 *new_node);
400 #if !defined(CONFIG_PPC) && !defined(__sparc__)
401 static void __init aty128_get_pllinfo(struct fb_info_aty128 *info,
402 char *bios_seg);
403 static char __init *aty128find_ROM(struct fb_info_aty128 *info);
404 #endif
405 static void aty128_timings(struct fb_info_aty128 *info);
406 static void aty128_init_engine(const struct aty128fb_par *par,
407 struct fb_info_aty128 *info);
408 static void aty128_reset_engine(const struct fb_info_aty128 *info);
409 static void aty128_flush_pixel_cache(const struct fb_info_aty128 *info);
410 static void do_wait_for_fifo(u16 entries, struct fb_info_aty128 *info);
411 static void wait_for_fifo(u16 entries, struct fb_info_aty128 *info);
412 static void wait_for_idle(struct fb_info_aty128 *info);
413 static u32 depth_to_dst(u32 depth);
414
415 #ifdef FBCON_HAS_CFB8
416 static struct display_switch fbcon_aty128_8;
417 static void fbcon_aty8_putc(struct vc_data *conp, struct display *p,
418 int c, int yy, int xx);
419 static void fbcon_aty8_putcs(struct vc_data *conp, struct display *p,
420 const unsigned short *s, int count,
421 int yy, int xx);
422 #endif
423 #ifdef FBCON_HAS_CFB16
424 static struct display_switch fbcon_aty128_16;
425 static void fbcon_aty16_putc(struct vc_data *conp, struct display *p,
426 int c, int yy, int xx);
427 static void fbcon_aty16_putcs(struct vc_data *conp, struct display *p,
428 const unsigned short *s, int count,
429 int yy, int xx);
430 #endif
431 #ifdef FBCON_HAS_CFB24
432 static struct display_switch fbcon_aty128_24;
433 static void fbcon_aty24_putc(struct vc_data *conp, struct display *p,
434 int c, int yy, int xx);
435 static void fbcon_aty24_putcs(struct vc_data *conp, struct display *p,
436 const unsigned short *s, int count,
437 int yy, int xx);
438 #endif
439 #ifdef FBCON_HAS_CFB32
440 static struct display_switch fbcon_aty128_32;
441 static void fbcon_aty32_putc(struct vc_data *conp, struct display *p,
442 int c, int yy, int xx);
443 static void fbcon_aty32_putcs(struct vc_data *conp, struct display *p,
444 const unsigned short *s, int count,
445 int yy, int xx);
446 #endif
447
448 static struct fb_ops aty128fb_ops = {
449 owner: THIS_MODULE,
450 fb_get_fix: aty128fb_get_fix,
451 fb_get_var: aty128fb_get_var,
452 fb_set_var: aty128fb_set_var,
453 fb_get_cmap: aty128fb_get_cmap,
454 fb_set_cmap: aty128fb_set_cmap,
455 fb_pan_display: aty128fb_pan_display,
456 fb_ioctl: aty128fb_ioctl,
457 fb_rasterimg: aty128fb_rasterimg,
458 };
459
460 #ifdef CONFIG_PMAC_BACKLIGHT
461 static int aty128_set_backlight_enable(int on, int level, void* data);
462 static int aty128_set_backlight_level(int level, void* data);
463
464 static struct backlight_controller aty128_backlight_controller = {
465 aty128_set_backlight_enable,
466 aty128_set_backlight_level
467 };
468 #endif /* CONFIG_PMAC_BACKLIGHT */
469
470 /*
471 * Functions to read from/write to the mmio registers
472 * - endian conversions may possibly be avoided by
473 * using the other register aperture. TODO.
474 */
475 static inline u32
_aty_ld_le32(volatile unsigned int regindex,const struct fb_info_aty128 * info)476 _aty_ld_le32(volatile unsigned int regindex,
477 const struct fb_info_aty128 *info)
478 {
479 u32 val;
480
481 #if defined(__powerpc__)
482 asm("lwbrx %0,%1,%2;eieio" : "=r"(val) : "b"(regindex), "r"(info->regbase));
483 #else
484 val = readl (info->regbase + regindex);
485 #endif
486
487 return val;
488 }
489
490 static inline void
_aty_st_le32(volatile unsigned int regindex,u32 val,const struct fb_info_aty128 * info)491 _aty_st_le32(volatile unsigned int regindex, u32 val,
492 const struct fb_info_aty128 *info)
493 {
494 #if defined(__powerpc__)
495 asm("stwbrx %0,%1,%2;eieio" : : "r"(val), "b"(regindex),
496 "r"(info->regbase) : "memory");
497 #else
498 writel (val, info->regbase + regindex);
499 #endif
500 }
501
502 static inline u8
_aty_ld_8(unsigned int regindex,const struct fb_info_aty128 * info)503 _aty_ld_8(unsigned int regindex, const struct fb_info_aty128 *info)
504 {
505 return readb (info->regbase + regindex);
506 }
507
508 static inline void
_aty_st_8(unsigned int regindex,u8 val,const struct fb_info_aty128 * info)509 _aty_st_8(unsigned int regindex, u8 val, const struct fb_info_aty128 *info)
510 {
511 writeb (val, info->regbase + regindex);
512 }
513
514 #define aty_ld_le32(regindex) _aty_ld_le32(regindex, info)
515 #define aty_st_le32(regindex, val) _aty_st_le32(regindex, val, info)
516 #define aty_ld_8(regindex) _aty_ld_8(regindex, info)
517 #define aty_st_8(regindex, val) _aty_st_8(regindex, val, info)
518
519 /*
520 * Functions to read from/write to the pll registers
521 */
522
523 #define aty_ld_pll(pll_index) _aty_ld_pll(pll_index, info)
524 #define aty_st_pll(pll_index, val) _aty_st_pll(pll_index, val, info)
525
526
527 static u32
_aty_ld_pll(unsigned int pll_index,const struct fb_info_aty128 * info)528 _aty_ld_pll(unsigned int pll_index,
529 const struct fb_info_aty128 *info)
530 {
531 aty_st_8(CLOCK_CNTL_INDEX, pll_index & 0x3F);
532 return aty_ld_le32(CLOCK_CNTL_DATA);
533 }
534
535
536 static void
_aty_st_pll(unsigned int pll_index,u32 val,const struct fb_info_aty128 * info)537 _aty_st_pll(unsigned int pll_index, u32 val,
538 const struct fb_info_aty128 *info)
539 {
540 aty_st_8(CLOCK_CNTL_INDEX, (pll_index & 0x3F) | PLL_WR_EN);
541 aty_st_le32(CLOCK_CNTL_DATA, val);
542 }
543
544
545 /* return true when the PLL has completed an atomic update */
546 static int
aty_pll_readupdate(const struct fb_info_aty128 * info)547 aty_pll_readupdate(const struct fb_info_aty128 *info)
548 {
549 return !(aty_ld_pll(PPLL_REF_DIV) & PPLL_ATOMIC_UPDATE_R);
550 }
551
552
553 static void
aty_pll_wait_readupdate(const struct fb_info_aty128 * info)554 aty_pll_wait_readupdate(const struct fb_info_aty128 *info)
555 {
556 unsigned long timeout = jiffies + HZ/100; // should be more than enough
557 int reset = 1;
558
559 while (time_before(jiffies, timeout))
560 if (aty_pll_readupdate(info)) {
561 reset = 0;
562 break;
563 }
564
565 if (reset) /* reset engine?? */
566 printk(KERN_DEBUG "aty128fb: PLL write timeout!\n");
567 }
568
569
570 /* tell PLL to update */
571 static void
aty_pll_writeupdate(const struct fb_info_aty128 * info)572 aty_pll_writeupdate(const struct fb_info_aty128 *info)
573 {
574 aty_pll_wait_readupdate(info);
575
576 aty_st_pll(PPLL_REF_DIV,
577 aty_ld_pll(PPLL_REF_DIV) | PPLL_ATOMIC_UPDATE_W);
578 }
579
580
581 /* write to the scratch register to test r/w functionality */
582 static int __init
register_test(const struct fb_info_aty128 * info)583 register_test(const struct fb_info_aty128 *info)
584 {
585 u32 val;
586 int flag = 0;
587
588 val = aty_ld_le32(BIOS_0_SCRATCH);
589
590 aty_st_le32(BIOS_0_SCRATCH, 0x55555555);
591 if (aty_ld_le32(BIOS_0_SCRATCH) == 0x55555555) {
592 aty_st_le32(BIOS_0_SCRATCH, 0xAAAAAAAA);
593
594 if (aty_ld_le32(BIOS_0_SCRATCH) == 0xAAAAAAAA)
595 flag = 1;
596 }
597
598 aty_st_le32(BIOS_0_SCRATCH, val); // restore value
599 return flag;
600 }
601
602
603 /*
604 * Accelerator engine functions
605 */
606 static void
do_wait_for_fifo(u16 entries,struct fb_info_aty128 * info)607 do_wait_for_fifo(u16 entries, struct fb_info_aty128 *info)
608 {
609 int i;
610
611 for (;;) {
612 for (i = 0; i < 2000000; i++) {
613 info->fifo_slots = aty_ld_le32(GUI_STAT) & 0x0fff;
614 if (info->fifo_slots >= entries)
615 return;
616 }
617 aty128_reset_engine(info);
618 }
619 }
620
621
622 static void
wait_for_idle(struct fb_info_aty128 * info)623 wait_for_idle(struct fb_info_aty128 *info)
624 {
625 int i;
626
627 do_wait_for_fifo(64, info);
628
629 for (;;) {
630 for (i = 0; i < 2000000; i++) {
631 if (!(aty_ld_le32(GUI_STAT) & (1 << 31))) {
632 aty128_flush_pixel_cache(info);
633 info->blitter_may_be_busy = 0;
634 return;
635 }
636 }
637 aty128_reset_engine(info);
638 }
639 }
640
641
642 static void
wait_for_fifo(u16 entries,struct fb_info_aty128 * info)643 wait_for_fifo(u16 entries, struct fb_info_aty128 *info)
644 {
645 if (info->fifo_slots < entries)
646 do_wait_for_fifo(64, info);
647 info->fifo_slots -= entries;
648 }
649
650
651 static void
aty128_flush_pixel_cache(const struct fb_info_aty128 * info)652 aty128_flush_pixel_cache(const struct fb_info_aty128 *info)
653 {
654 int i;
655 u32 tmp;
656
657 tmp = aty_ld_le32(PC_NGUI_CTLSTAT);
658 tmp &= ~(0x00ff);
659 tmp |= 0x00ff;
660 aty_st_le32(PC_NGUI_CTLSTAT, tmp);
661
662 for (i = 0; i < 2000000; i++)
663 if (!(aty_ld_le32(PC_NGUI_CTLSTAT) & PC_BUSY))
664 break;
665 }
666
667
668 static void
aty128_reset_engine(const struct fb_info_aty128 * info)669 aty128_reset_engine(const struct fb_info_aty128 *info)
670 {
671 u32 gen_reset_cntl, clock_cntl_index, mclk_cntl;
672
673 aty128_flush_pixel_cache(info);
674
675 clock_cntl_index = aty_ld_le32(CLOCK_CNTL_INDEX);
676 mclk_cntl = aty_ld_pll(MCLK_CNTL);
677
678 aty_st_pll(MCLK_CNTL, mclk_cntl | 0x00030000);
679
680 gen_reset_cntl = aty_ld_le32(GEN_RESET_CNTL);
681 aty_st_le32(GEN_RESET_CNTL, gen_reset_cntl | SOFT_RESET_GUI);
682 aty_ld_le32(GEN_RESET_CNTL);
683 aty_st_le32(GEN_RESET_CNTL, gen_reset_cntl & ~(SOFT_RESET_GUI));
684 aty_ld_le32(GEN_RESET_CNTL);
685
686 aty_st_pll(MCLK_CNTL, mclk_cntl);
687 aty_st_le32(CLOCK_CNTL_INDEX, clock_cntl_index);
688 aty_st_le32(GEN_RESET_CNTL, gen_reset_cntl);
689
690 /* use old pio mode */
691 aty_st_le32(PM4_BUFFER_CNTL, PM4_BUFFER_CNTL_NONPM4);
692
693 DBG("engine reset");
694 }
695
696
697 static void
aty128_init_engine(const struct aty128fb_par * par,struct fb_info_aty128 * info)698 aty128_init_engine(const struct aty128fb_par *par,
699 struct fb_info_aty128 *info)
700 {
701 u32 pitch_value;
702
703 wait_for_idle(info);
704
705 /* 3D scaler not spoken here */
706 wait_for_fifo(1, info);
707 aty_st_le32(SCALE_3D_CNTL, 0x00000000);
708
709 aty128_reset_engine(info);
710
711 pitch_value = par->crtc.pitch;
712 if (par->crtc.bpp == 24) {
713 pitch_value = pitch_value * 3;
714 }
715
716 wait_for_fifo(4, info);
717 /* setup engine offset registers */
718 aty_st_le32(DEFAULT_OFFSET, 0x00000000);
719
720 /* setup engine pitch registers */
721 aty_st_le32(DEFAULT_PITCH, pitch_value);
722
723 /* set the default scissor register to max dimensions */
724 aty_st_le32(DEFAULT_SC_BOTTOM_RIGHT, (0x1FFF << 16) | 0x1FFF);
725
726 /* set the drawing controls registers */
727 aty_st_le32(DP_GUI_MASTER_CNTL,
728 GMC_SRC_PITCH_OFFSET_DEFAULT |
729 GMC_DST_PITCH_OFFSET_DEFAULT |
730 GMC_SRC_CLIP_DEFAULT |
731 GMC_DST_CLIP_DEFAULT |
732 GMC_BRUSH_SOLIDCOLOR |
733 (depth_to_dst(par->crtc.depth) << 8) |
734 GMC_SRC_DSTCOLOR |
735 GMC_BYTE_ORDER_MSB_TO_LSB |
736 GMC_DP_CONVERSION_TEMP_6500 |
737 ROP3_PATCOPY |
738 GMC_DP_SRC_RECT |
739 GMC_3D_FCN_EN_CLR |
740 GMC_DST_CLR_CMP_FCN_CLEAR |
741 GMC_AUX_CLIP_CLEAR |
742 GMC_WRITE_MASK_SET);
743
744 wait_for_fifo(8, info);
745 /* clear the line drawing registers */
746 aty_st_le32(DST_BRES_ERR, 0);
747 aty_st_le32(DST_BRES_INC, 0);
748 aty_st_le32(DST_BRES_DEC, 0);
749
750 /* set brush color registers */
751 aty_st_le32(DP_BRUSH_FRGD_CLR, 0xFFFFFFFF); /* white */
752 aty_st_le32(DP_BRUSH_BKGD_CLR, 0x00000000); /* black */
753
754 /* set source color registers */
755 aty_st_le32(DP_SRC_FRGD_CLR, 0xFFFFFFFF); /* white */
756 aty_st_le32(DP_SRC_BKGD_CLR, 0x00000000); /* black */
757
758 /* default write mask */
759 aty_st_le32(DP_WRITE_MASK, 0xFFFFFFFF);
760
761 /* Wait for all the writes to be completed before returning */
762 wait_for_idle(info);
763 }
764
765
766 /* convert depth values to their register representation */
767 static u32
depth_to_dst(u32 depth)768 depth_to_dst(u32 depth)
769 {
770 if (depth <= 8)
771 return DST_8BPP;
772 else if (depth <= 15)
773 return DST_15BPP;
774 else if (depth == 16)
775 return DST_16BPP;
776 else if (depth <= 24)
777 return DST_24BPP;
778 else if (depth <= 32)
779 return DST_32BPP;
780
781 return -EINVAL;
782 }
783
784
785 /*
786 * CRTC programming
787 */
788
789 /* Program the CRTC registers */
790 static void
aty128_set_crtc(const struct aty128_crtc * crtc,const struct fb_info_aty128 * info)791 aty128_set_crtc(const struct aty128_crtc *crtc,
792 const struct fb_info_aty128 *info)
793 {
794 aty_st_le32(CRTC_GEN_CNTL, crtc->gen_cntl);
795 aty_st_le32(CRTC_H_TOTAL_DISP, crtc->h_total);
796 aty_st_le32(CRTC_H_SYNC_STRT_WID, crtc->h_sync_strt_wid);
797 aty_st_le32(CRTC_V_TOTAL_DISP, crtc->v_total);
798 aty_st_le32(CRTC_V_SYNC_STRT_WID, crtc->v_sync_strt_wid);
799 aty_st_le32(CRTC_PITCH, crtc->pitch);
800 aty_st_le32(CRTC_OFFSET, crtc->offset);
801 aty_st_le32(CRTC_OFFSET_CNTL, crtc->offset_cntl);
802 /* Disable ATOMIC updating. Is this the right place? */
803 aty_st_pll(PPLL_CNTL, aty_ld_pll(PPLL_CNTL) & ~(0x00030000));
804 }
805
806
807 static int
aty128_var_to_crtc(const struct fb_var_screeninfo * var,struct aty128_crtc * crtc,const struct fb_info_aty128 * info)808 aty128_var_to_crtc(const struct fb_var_screeninfo *var,
809 struct aty128_crtc *crtc,
810 const struct fb_info_aty128 *info)
811 {
812 u32 xres, yres, vxres, vyres, xoffset, yoffset, bpp, dst;
813 u32 left, right, upper, lower, hslen, vslen, sync, vmode;
814 u32 h_total, h_disp, h_sync_strt, h_sync_wid, h_sync_pol;
815 u32 v_total, v_disp, v_sync_strt, v_sync_wid, v_sync_pol, c_sync;
816 u32 depth, bytpp;
817 u8 hsync_strt_pix[5] = { 0, 0x12, 9, 6, 5 };
818 u8 mode_bytpp[7] = { 0, 0, 1, 2, 2, 3, 4 };
819
820 /* input */
821 xres = var->xres;
822 yres = var->yres;
823 vxres = var->xres_virtual;
824 vyres = var->yres_virtual;
825 xoffset = var->xoffset;
826 yoffset = var->yoffset;
827 bpp = var->bits_per_pixel;
828 left = var->left_margin;
829 right = var->right_margin;
830 upper = var->upper_margin;
831 lower = var->lower_margin;
832 hslen = var->hsync_len;
833 vslen = var->vsync_len;
834 sync = var->sync;
835 vmode = var->vmode;
836
837 if (bpp != 16)
838 depth = bpp;
839 else
840 depth = (var->green.length == 6) ? 16 : 15;
841
842 /* check for mode eligibility
843 * accept only non interlaced modes */
844 if ((vmode & FB_VMODE_MASK) != FB_VMODE_NONINTERLACED)
845 return -EINVAL;
846
847 /* convert (and round up) and validate */
848 xres = (xres + 7) & ~7;
849 xoffset = (xoffset + 7) & ~7;
850
851 if (vxres < xres + xoffset)
852 vxres = xres + xoffset;
853
854 if (vyres < yres + yoffset)
855 vyres = yres + yoffset;
856
857 /* convert depth into ATI register depth */
858 dst = depth_to_dst(depth);
859
860 if (dst == -EINVAL) {
861 printk(KERN_ERR "aty128fb: Invalid depth or RGBA\n");
862 return -EINVAL;
863 }
864
865 /* convert register depth to bytes per pixel */
866 bytpp = mode_bytpp[dst];
867
868 /* make sure there is enough video ram for the mode */
869 if ((u32)(vxres * vyres * bytpp) > info->vram_size) {
870 printk(KERN_ERR "aty128fb: Not enough memory for mode\n");
871 return -EINVAL;
872 }
873
874 h_disp = (xres >> 3) - 1;
875 h_total = (((xres + right + hslen + left) >> 3) - 1) & 0xFFFFL;
876
877 v_disp = yres - 1;
878 v_total = (yres + upper + vslen + lower - 1) & 0xFFFFL;
879
880 /* check to make sure h_total and v_total are in range */
881 if (((h_total >> 3) - 1) > 0x1ff || (v_total - 1) > 0x7FF) {
882 printk(KERN_ERR "aty128fb: invalid width ranges\n");
883 return -EINVAL;
884 }
885
886 h_sync_wid = (hslen + 7) >> 3;
887 if (h_sync_wid == 0)
888 h_sync_wid = 1;
889 else if (h_sync_wid > 0x3f) /* 0x3f = max hwidth */
890 h_sync_wid = 0x3f;
891
892 h_sync_strt = h_disp + (right >> 3);
893
894 v_sync_wid = vslen;
895 if (v_sync_wid == 0)
896 v_sync_wid = 1;
897 else if (v_sync_wid > 0x1f) /* 0x1f = max vwidth */
898 v_sync_wid = 0x1f;
899
900 v_sync_strt = v_disp + lower;
901
902 h_sync_pol = sync & FB_SYNC_HOR_HIGH_ACT ? 0 : 1;
903 v_sync_pol = sync & FB_SYNC_VERT_HIGH_ACT ? 0 : 1;
904
905 c_sync = sync & FB_SYNC_COMP_HIGH_ACT ? (1 << 4) : 0;
906
907 crtc->gen_cntl = 0x3000000L | c_sync | (dst << 8);
908
909 crtc->h_total = h_total | (h_disp << 16);
910 crtc->v_total = v_total | (v_disp << 16);
911
912 crtc->h_sync_strt_wid = hsync_strt_pix[bytpp] | (h_sync_strt << 3) |
913 (h_sync_wid << 16) | (h_sync_pol << 23);
914 crtc->v_sync_strt_wid = v_sync_strt | (v_sync_wid << 16) |
915 (v_sync_pol << 23);
916
917 crtc->pitch = vxres >> 3;
918
919 crtc->offset = 0;
920
921 if ((var->activate & FB_ACTIVATE_MASK) == FB_ACTIVATE_NOW)
922 crtc->offset_cntl = 0x00010000;
923 else
924 crtc->offset_cntl = 0;
925
926 crtc->vxres = vxres;
927 crtc->vyres = vyres;
928 crtc->xoffset = xoffset;
929 crtc->yoffset = yoffset;
930 crtc->depth = depth;
931 crtc->bpp = bpp;
932
933 return 0;
934 }
935
936
937 static int
aty128_pix_width_to_var(int pix_width,struct fb_var_screeninfo * var)938 aty128_pix_width_to_var(int pix_width, struct fb_var_screeninfo *var)
939 {
940
941 /* fill in pixel info */
942 switch (pix_width) {
943 case CRTC_PIX_WIDTH_8BPP:
944 var->bits_per_pixel = 8;
945 var->red.offset = 0;
946 var->red.length = 8;
947 var->green.offset = 0;
948 var->green.length = 8;
949 var->blue.offset = 0;
950 var->blue.length = 8;
951 var->transp.offset = 0;
952 var->transp.length = 0;
953 break;
954 case CRTC_PIX_WIDTH_15BPP:
955 var->bits_per_pixel = 16;
956 var->red.offset = 10;
957 var->red.length = 5;
958 var->green.offset = 5;
959 var->green.length = 5;
960 var->blue.offset = 0;
961 var->blue.length = 5;
962 var->transp.offset = 0;
963 var->transp.length = 0;
964 break;
965 case CRTC_PIX_WIDTH_16BPP:
966 var->bits_per_pixel = 16;
967 var->red.offset = 11;
968 var->red.length = 5;
969 var->green.offset = 5;
970 var->green.length = 6;
971 var->blue.offset = 0;
972 var->blue.length = 5;
973 var->transp.offset = 0;
974 var->transp.length = 0;
975 break;
976 case CRTC_PIX_WIDTH_24BPP:
977 var->bits_per_pixel = 24;
978 var->red.offset = 16;
979 var->red.length = 8;
980 var->green.offset = 8;
981 var->green.length = 8;
982 var->blue.offset = 0;
983 var->blue.length = 8;
984 var->transp.offset = 0;
985 var->transp.length = 0;
986 break;
987 case CRTC_PIX_WIDTH_32BPP:
988 var->bits_per_pixel = 32;
989 var->red.offset = 16;
990 var->red.length = 8;
991 var->green.offset = 8;
992 var->green.length = 8;
993 var->blue.offset = 0;
994 var->blue.length = 8;
995 var->transp.offset = 24;
996 var->transp.length = 8;
997 break;
998 default:
999 printk(KERN_ERR "aty128fb: Invalid pixel width\n");
1000 return -EINVAL;
1001 }
1002
1003 return 0;
1004 }
1005
1006
1007 static int
aty128_crtc_to_var(const struct aty128_crtc * crtc,struct fb_var_screeninfo * var)1008 aty128_crtc_to_var(const struct aty128_crtc *crtc,
1009 struct fb_var_screeninfo *var)
1010 {
1011 u32 xres, yres, left, right, upper, lower, hslen, vslen, sync;
1012 u32 h_total, h_disp, h_sync_strt, h_sync_dly, h_sync_wid, h_sync_pol;
1013 u32 v_total, v_disp, v_sync_strt, v_sync_wid, v_sync_pol, c_sync;
1014 u32 pix_width;
1015
1016 /* fun with masking */
1017 h_total = crtc->h_total & 0x1ff;
1018 h_disp = (crtc->h_total >> 16) & 0xff;
1019 h_sync_strt = (crtc->h_sync_strt_wid >> 3) & 0x1ff;
1020 h_sync_dly = crtc->h_sync_strt_wid & 0x7;
1021 h_sync_wid = (crtc->h_sync_strt_wid >> 16) & 0x3f;
1022 h_sync_pol = (crtc->h_sync_strt_wid >> 23) & 0x1;
1023 v_total = crtc->v_total & 0x7ff;
1024 v_disp = (crtc->v_total >> 16) & 0x7ff;
1025 v_sync_strt = crtc->v_sync_strt_wid & 0x7ff;
1026 v_sync_wid = (crtc->v_sync_strt_wid >> 16) & 0x1f;
1027 v_sync_pol = (crtc->v_sync_strt_wid >> 23) & 0x1;
1028 c_sync = crtc->gen_cntl & CRTC_CSYNC_EN ? 1 : 0;
1029 pix_width = crtc->gen_cntl & CRTC_PIX_WIDTH_MASK;
1030
1031 /* do conversions */
1032 xres = (h_disp + 1) << 3;
1033 yres = v_disp + 1;
1034 left = ((h_total - h_sync_strt - h_sync_wid) << 3) - h_sync_dly;
1035 right = ((h_sync_strt - h_disp) << 3) + h_sync_dly;
1036 hslen = h_sync_wid << 3;
1037 upper = v_total - v_sync_strt - v_sync_wid;
1038 lower = v_sync_strt - v_disp;
1039 vslen = v_sync_wid;
1040 sync = (h_sync_pol ? 0 : FB_SYNC_HOR_HIGH_ACT) |
1041 (v_sync_pol ? 0 : FB_SYNC_VERT_HIGH_ACT) |
1042 (c_sync ? FB_SYNC_COMP_HIGH_ACT : 0);
1043
1044 aty128_pix_width_to_var(pix_width, var);
1045
1046 var->xres = xres;
1047 var->yres = yres;
1048 var->xres_virtual = crtc->vxres;
1049 var->yres_virtual = crtc->vyres;
1050 var->xoffset = crtc->xoffset;
1051 var->yoffset = crtc->yoffset;
1052 var->left_margin = left;
1053 var->right_margin = right;
1054 var->upper_margin = upper;
1055 var->lower_margin = lower;
1056 var->hsync_len = hslen;
1057 var->vsync_len = vslen;
1058 var->sync = sync;
1059 var->vmode = FB_VMODE_NONINTERLACED;
1060
1061 return 0;
1062 }
1063
1064 static void
aty128_set_crt_enable(struct fb_info_aty128 * info,int on)1065 aty128_set_crt_enable(struct fb_info_aty128 *info, int on)
1066 {
1067 if (on) {
1068 aty_st_le32(CRTC_EXT_CNTL, aty_ld_le32(CRTC_EXT_CNTL) | CRT_CRTC_ON);
1069 aty_st_le32(DAC_CNTL, (aty_ld_le32(DAC_CNTL) | DAC_PALETTE2_SNOOP_EN));
1070 } else
1071 aty_st_le32(CRTC_EXT_CNTL, aty_ld_le32(CRTC_EXT_CNTL) & ~CRT_CRTC_ON);
1072 }
1073
1074 static void
aty128_set_lcd_enable(struct fb_info_aty128 * info,int on)1075 aty128_set_lcd_enable(struct fb_info_aty128 *info, int on)
1076 {
1077 u32 reg;
1078
1079 if (on) {
1080 reg = aty_ld_le32(LVDS_GEN_CNTL);
1081 reg |= LVDS_ON | LVDS_EN | LVDS_BLON | LVDS_DIGION;
1082 reg &= ~LVDS_DISPLAY_DIS;
1083 aty_st_le32(LVDS_GEN_CNTL, reg);
1084 #ifdef CONFIG_PMAC_BACKLIGHT
1085 aty128_set_backlight_enable(get_backlight_enable(), get_backlight_level(), info);
1086 #endif
1087 } else {
1088 #ifdef CONFIG_PMAC_BACKLIGHT
1089 aty128_set_backlight_enable(0, 0, info);
1090 #endif
1091 reg = aty_ld_le32(LVDS_GEN_CNTL);
1092 reg |= LVDS_DISPLAY_DIS;
1093 aty_st_le32(LVDS_GEN_CNTL, reg);
1094 mdelay(100);
1095 reg &= ~(LVDS_ON /*| LVDS_EN*/);
1096 aty_st_le32(LVDS_GEN_CNTL, reg);
1097 }
1098 }
1099
1100 static void
aty128_set_pll(struct aty128_pll * pll,const struct fb_info_aty128 * info)1101 aty128_set_pll(struct aty128_pll *pll, const struct fb_info_aty128 *info)
1102 {
1103 u32 div3;
1104
1105 unsigned char post_conv[] = /* register values for post dividers */
1106 { 2, 0, 1, 4, 2, 2, 6, 2, 3, 2, 2, 2, 7 };
1107
1108 /* select PPLL_DIV_3 */
1109 aty_st_le32(CLOCK_CNTL_INDEX, aty_ld_le32(CLOCK_CNTL_INDEX) | (3 << 8));
1110
1111 /* reset PLL */
1112 aty_st_pll(PPLL_CNTL,
1113 aty_ld_pll(PPLL_CNTL) | PPLL_RESET | PPLL_ATOMIC_UPDATE_EN);
1114
1115 /* write the reference divider */
1116 aty_pll_wait_readupdate(info);
1117 aty_st_pll(PPLL_REF_DIV, info->constants.ref_divider & 0x3ff);
1118 aty_pll_writeupdate(info);
1119
1120 div3 = aty_ld_pll(PPLL_DIV_3);
1121 div3 &= ~PPLL_FB3_DIV_MASK;
1122 div3 |= pll->feedback_divider;
1123 div3 &= ~PPLL_POST3_DIV_MASK;
1124 div3 |= post_conv[pll->post_divider] << 16;
1125
1126 /* write feedback and post dividers */
1127 aty_pll_wait_readupdate(info);
1128 aty_st_pll(PPLL_DIV_3, div3);
1129 aty_pll_writeupdate(info);
1130
1131 aty_pll_wait_readupdate(info);
1132 aty_st_pll(HTOTAL_CNTL, 0); /* no horiz crtc adjustment */
1133 aty_pll_writeupdate(info);
1134
1135 /* clear the reset, just in case */
1136 aty_st_pll(PPLL_CNTL, aty_ld_pll(PPLL_CNTL) & ~PPLL_RESET);
1137
1138 #if 0
1139 if (info->chip_gen == rage_M3) {
1140 /* XXX energy saving, disable VCLK during blanking */
1141 aty_pll_wait_readupdate(info);
1142 aty_st_pll(VCLK_ECP_CNTL, aty_ld_pll(VCLK_ECP_CNTL) | 0xc0);
1143 aty_pll_writeupdate(info);
1144
1145 /* Set PM clocks */
1146 aty_pll_wait_readupdate(info);
1147 aty_st_pll(XCLK_CNTL, aty_ld_pll(XCLK_CNTL) | 0x00330000);
1148 aty_pll_writeupdate(info);
1149 aty_pll_wait_readupdate(info);
1150 aty_st_pll(MCLK_CNTL, aty_ld_pll(MCLK_CNTL) | 0x00000700);
1151 aty_pll_writeupdate(info);
1152 }
1153 #endif
1154 }
1155
1156
1157 static int
aty128_var_to_pll(u32 period_in_ps,struct aty128_pll * pll,const struct fb_info_aty128 * info)1158 aty128_var_to_pll(u32 period_in_ps, struct aty128_pll *pll,
1159 const struct fb_info_aty128 *info)
1160 {
1161 const struct aty128_constants c = info->constants;
1162 unsigned char post_dividers[] = {1,2,4,8,3,6,12};
1163 u32 output_freq;
1164 u32 vclk; /* in .01 MHz */
1165 int i;
1166 u32 n, d;
1167
1168 vclk = 100000000 / period_in_ps; /* convert units to 10 kHz */
1169
1170 /* adjust pixel clock if necessary */
1171 if (vclk > c.ppll_max)
1172 vclk = c.ppll_max;
1173 if (vclk * 12 < c.ppll_min)
1174 vclk = c.ppll_min/12;
1175
1176 /* now, find an acceptable divider */
1177 for (i = 0; i < sizeof(post_dividers); i++) {
1178 output_freq = post_dividers[i] * vclk;
1179 if (output_freq >= c.ppll_min && output_freq <= c.ppll_max)
1180 break;
1181 }
1182
1183 /* calculate feedback divider */
1184 n = c.ref_divider * output_freq;
1185 d = c.dotclock;
1186
1187 pll->post_divider = post_dividers[i];
1188 pll->feedback_divider = round_div(n, d);
1189 pll->vclk = vclk;
1190
1191 DBG("post %d feedback %d vlck %d output %d ref_divider %d "
1192 "vclk_per: %d\n", pll->post_divider,
1193 pll->feedback_divider, vclk, output_freq,
1194 c.ref_divider, period_in_ps);
1195
1196 return 0;
1197 }
1198
1199
1200 static int
aty128_pll_to_var(const struct aty128_pll * pll,struct fb_var_screeninfo * var,const struct fb_info_aty128 * info)1201 aty128_pll_to_var(const struct aty128_pll *pll, struct fb_var_screeninfo *var,
1202 const struct fb_info_aty128 *info)
1203 {
1204 var->pixclock = 100000000 / pll->vclk;
1205
1206 return 0;
1207 }
1208
1209
1210 static void
aty128_set_fifo(const struct aty128_ddafifo * dsp,const struct fb_info_aty128 * info)1211 aty128_set_fifo(const struct aty128_ddafifo *dsp,
1212 const struct fb_info_aty128 *info)
1213 {
1214 aty_st_le32(DDA_CONFIG, dsp->dda_config);
1215 aty_st_le32(DDA_ON_OFF, dsp->dda_on_off);
1216 }
1217
1218
1219 static int
aty128_ddafifo(struct aty128_ddafifo * dsp,const struct aty128_pll * pll,u32 depth,const struct fb_info_aty128 * info)1220 aty128_ddafifo(struct aty128_ddafifo *dsp,
1221 const struct aty128_pll *pll,
1222 u32 depth,
1223 const struct fb_info_aty128 *info)
1224 {
1225 const struct aty128_meminfo *m = info->mem;
1226 u32 xclk = info->constants.xclk;
1227 u32 fifo_width = info->constants.fifo_width;
1228 u32 fifo_depth = info->constants.fifo_depth;
1229 s32 x, b, p, ron, roff;
1230 u32 n, d, bpp;
1231
1232 /* round up to multiple of 8 */
1233 bpp = (depth+7) & ~7;
1234
1235 n = xclk * fifo_width;
1236 d = pll->vclk * bpp;
1237 x = round_div(n, d);
1238
1239 ron = 4 * m->MB +
1240 3 * ((m->Trcd - 2 > 0) ? m->Trcd - 2 : 0) +
1241 2 * m->Trp +
1242 m->Twr +
1243 m->CL +
1244 m->Tr2w +
1245 x;
1246
1247 DBG("x %x\n", x);
1248
1249 b = 0;
1250 while (x) {
1251 x >>= 1;
1252 b++;
1253 }
1254 p = b + 1;
1255
1256 ron <<= (11 - p);
1257
1258 n <<= (11 - p);
1259 x = round_div(n, d);
1260 roff = x * (fifo_depth - 4);
1261
1262 if ((ron + m->Rloop) >= roff) {
1263 printk(KERN_ERR "aty128fb: Mode out of range!\n");
1264 return -EINVAL;
1265 }
1266
1267 DBG("p: %x rloop: %x x: %x ron: %x roff: %x\n",
1268 p, m->Rloop, x, ron, roff);
1269
1270 dsp->dda_config = p << 16 | m->Rloop << 20 | x;
1271 dsp->dda_on_off = ron << 16 | roff;
1272
1273 return 0;
1274 }
1275
1276
1277 /*
1278 * This actually sets the video mode.
1279 */
1280 static void
aty128_set_par(struct aty128fb_par * par,struct fb_info_aty128 * info)1281 aty128_set_par(struct aty128fb_par *par,
1282 struct fb_info_aty128 *info)
1283 {
1284 u32 config;
1285
1286 info->current_par = *par;
1287
1288 if (info->blitter_may_be_busy)
1289 wait_for_idle(info);
1290
1291 /* clear all registers that may interfere with mode setting */
1292 aty_st_le32(OVR_CLR, 0);
1293 aty_st_le32(OVR_WID_LEFT_RIGHT, 0);
1294 aty_st_le32(OVR_WID_TOP_BOTTOM, 0);
1295 aty_st_le32(OV0_SCALE_CNTL, 0);
1296 aty_st_le32(MPP_TB_CONFIG, 0);
1297 aty_st_le32(MPP_GP_CONFIG, 0);
1298 aty_st_le32(SUBPIC_CNTL, 0);
1299 aty_st_le32(VIPH_CONTROL, 0);
1300 aty_st_le32(I2C_CNTL_1, 0); /* turn off i2c */
1301 aty_st_le32(GEN_INT_CNTL, 0); /* turn off interrupts */
1302 aty_st_le32(CAP0_TRIG_CNTL, 0);
1303 aty_st_le32(CAP1_TRIG_CNTL, 0);
1304
1305 aty_st_8(CRTC_EXT_CNTL + 1, 4); /* turn video off */
1306
1307 aty128_set_crtc(&par->crtc, info);
1308 aty128_set_pll(&par->pll, info);
1309 aty128_set_fifo(&par->fifo_reg, info);
1310
1311 config = aty_ld_le32(CONFIG_CNTL) & ~3;
1312
1313 #if defined(__BIG_ENDIAN)
1314 if (par->crtc.bpp == 32)
1315 config |= 2; /* make aperture do 32 bit swapping */
1316 else if (par->crtc.bpp == 16)
1317 config |= 1; /* make aperture do 16 bit swapping */
1318 #endif
1319
1320 aty_st_le32(CONFIG_CNTL, config);
1321 aty_st_8(CRTC_EXT_CNTL + 1, 0); /* turn the video back on */
1322
1323 #ifdef CONFIG_PMAC_PBOOK
1324 if (info->chip_gen == rage_M3) {
1325 aty128_set_crt_enable(info, info->crt_on);
1326 aty128_set_lcd_enable(info, info->lcd_on);
1327 }
1328 #endif
1329 if (par->accel_flags & FB_ACCELF_TEXT)
1330 aty128_init_engine(par, info);
1331
1332 #ifdef CONFIG_FB_COMPAT_XPMAC
1333 if (!console_fb_info || console_fb_info == &info->fb_info) {
1334 struct fb_var_screeninfo var;
1335 int cmode, vmode;
1336
1337 display_info.height = ((par->crtc.v_total >> 16) & 0x7ff) + 1;
1338 display_info.width = (((par->crtc.h_total >> 16) & 0xff) + 1) << 3;
1339 display_info.depth = par->crtc.bpp;
1340 display_info.pitch = (par->crtc.vxres * par->crtc.bpp) >> 3;
1341 aty128_encode_var(&var, par, info);
1342 if (mac_var_to_vmode(&var, &vmode, &cmode))
1343 display_info.mode = 0;
1344 else
1345 display_info.mode = vmode;
1346 strcpy(display_info.name, aty128fb_name);
1347 display_info.fb_address = info->frame_buffer_phys;
1348 display_info.cmap_adr_address = 0;
1349 display_info.cmap_data_address = 0;
1350 display_info.disp_reg_address = info->regbase_phys;
1351 }
1352 #endif /* CONFIG_FB_COMPAT_XPMAC */
1353 #if defined(CONFIG_BOOTX_TEXT)
1354 btext_update_display(info->frame_buffer_phys,
1355 (((par->crtc.h_total>>16) & 0xff)+1)*8,
1356 ((par->crtc.v_total>>16) & 0x7ff)+1,
1357 par->crtc.bpp,
1358 par->crtc.vxres*par->crtc.bpp/8);
1359 #endif /* CONFIG_BOOTX_TEXT */
1360 }
1361
1362 /*
1363 * encode/decode the User Defined Part of the Display
1364 */
1365
1366 static int
aty128_decode_var(struct fb_var_screeninfo * var,struct aty128fb_par * par,const struct fb_info_aty128 * info)1367 aty128_decode_var(struct fb_var_screeninfo *var, struct aty128fb_par *par,
1368 const struct fb_info_aty128 *info)
1369 {
1370 int err;
1371
1372 if ((err = aty128_var_to_crtc(var, &par->crtc, info)))
1373 return err;
1374
1375 if ((err = aty128_var_to_pll(var->pixclock, &par->pll, info)))
1376 return err;
1377
1378 if ((err = aty128_ddafifo(&par->fifo_reg, &par->pll, par->crtc.depth, info)))
1379 return err;
1380
1381 if (var->accel_flags & FB_ACCELF_TEXT)
1382 par->accel_flags = FB_ACCELF_TEXT;
1383 else
1384 par->accel_flags = 0;
1385
1386 return 0;
1387 }
1388
1389
1390 static int
aty128_encode_var(struct fb_var_screeninfo * var,const struct aty128fb_par * par,const struct fb_info_aty128 * info)1391 aty128_encode_var(struct fb_var_screeninfo *var,
1392 const struct aty128fb_par *par,
1393 const struct fb_info_aty128 *info)
1394 {
1395 int err;
1396
1397 if ((err = aty128_crtc_to_var(&par->crtc, var)))
1398 return err;
1399
1400 if ((err = aty128_pll_to_var(&par->pll, var, info)))
1401 return err;
1402
1403 var->red.msb_right = 0;
1404 var->green.msb_right = 0;
1405 var->blue.msb_right = 0;
1406 var->transp.msb_right = 0;
1407
1408 var->nonstd = 0;
1409 var->activate = 0;
1410
1411 var->height = -1;
1412 var->width = -1;
1413 var->accel_flags = par->accel_flags;
1414
1415 return 0;
1416 }
1417
1418
1419 /*
1420 * Get the User Defined Part of the Display
1421 */
1422
1423 static int
aty128fb_get_var(struct fb_var_screeninfo * var,int con,struct fb_info * fb)1424 aty128fb_get_var(struct fb_var_screeninfo *var, int con, struct fb_info *fb)
1425 {
1426 const struct fb_info_aty128 *info = (struct fb_info_aty128 *)fb;
1427
1428 if (con == -1)
1429 aty128_encode_var(var, &info->default_par, info);
1430 else
1431 *var = fb_display[con].var;
1432 return 0;
1433 }
1434
1435
1436 /*
1437 * Set the User Defined Part of the Display
1438 */
1439
1440 static int
aty128fb_set_var(struct fb_var_screeninfo * var,int con,struct fb_info * fb)1441 aty128fb_set_var(struct fb_var_screeninfo *var, int con, struct fb_info *fb)
1442 {
1443 struct fb_info_aty128 *info = (struct fb_info_aty128 *)fb;
1444 struct aty128fb_par par;
1445 struct display *display;
1446 int oldxres, oldyres, oldvxres, oldvyres, oldbpp, oldgreen, oldaccel;
1447 int accel, err;
1448
1449 display = (con >= 0) ? &fb_display[con] : fb->disp;
1450
1451 /* basic (in)sanity checks */
1452 if (!var->xres)
1453 var->xres = 1;
1454 if (!var->yres)
1455 var->yres = 1;
1456 if (var->xres > var->xres_virtual)
1457 var->xres_virtual = var->xres;
1458 if (var->yres > var->yres_virtual)
1459 var->yres_virtual = var->yres;
1460
1461 switch (var->bits_per_pixel) {
1462 case 0 ... 8:
1463 var->bits_per_pixel = 8;
1464 break;
1465 case 9 ... 16:
1466 var->bits_per_pixel = 16;
1467 break;
1468 case 17 ... 24:
1469 var->bits_per_pixel = 24;
1470 break;
1471 case 25 ... 32:
1472 var->bits_per_pixel = 32;
1473 break;
1474 default:
1475 return -EINVAL;
1476 }
1477
1478 if ((err = aty128_decode_var(var, &par, info)))
1479 return err;
1480
1481 aty128_encode_var(var, &par, info);
1482
1483 if ((var->activate & FB_ACTIVATE_MASK) == FB_ACTIVATE_TEST)
1484 return 0;
1485
1486 oldxres = display->var.xres;
1487 oldyres = display->var.yres;
1488 oldvxres = display->var.xres_virtual;
1489 oldvyres = display->var.yres_virtual;
1490 oldbpp = display->var.bits_per_pixel;
1491 oldgreen = display->var.green.length;
1492 oldaccel = display->var.accel_flags;
1493 display->var = *var;
1494 if (oldxres != var->xres || oldyres != var->yres ||
1495 oldvxres != var->xres_virtual || oldvyres != var->yres_virtual ||
1496 oldgreen != var->green.length || oldbpp != var->bits_per_pixel ||
1497 oldaccel != var->accel_flags) {
1498
1499 struct fb_fix_screeninfo fix;
1500
1501 aty128_encode_fix(&fix, &par, info);
1502 display->screen_base = info->frame_buffer;
1503 display->visual = fix.visual;
1504 display->type = fix.type;
1505 display->type_aux = fix.type_aux;
1506 display->ypanstep = fix.ypanstep;
1507 display->ywrapstep = fix.ywrapstep;
1508 display->line_length = fix.line_length;
1509 display->can_soft_blank = 1;
1510 display->inverse = 0;
1511
1512 accel = var->accel_flags & FB_ACCELF_TEXT;
1513 aty128_set_dispsw(display, info, par.crtc.bpp, accel);
1514
1515 if (accel)
1516 display->scrollmode = SCROLL_YNOMOVE;
1517 else
1518 display->scrollmode = SCROLL_YREDRAW;
1519
1520 if (info->fb_info.changevar)
1521 (*info->fb_info.changevar)(con);
1522 }
1523
1524 if (!info->fb_info.display_fg || info->fb_info.display_fg->vc_num == con)
1525 aty128_set_par(&par, info);
1526
1527 if (oldbpp != var->bits_per_pixel || oldgreen != var->green.length) {
1528 if ((err = fb_alloc_cmap(&display->cmap, 0, 0)))
1529 return err;
1530 do_install_cmap(con, &info->fb_info);
1531 }
1532
1533 return 0;
1534 }
1535
1536
1537 static void
aty128_set_dispsw(struct display * disp,struct fb_info_aty128 * info,int bpp,int accel)1538 aty128_set_dispsw(struct display *disp,
1539 struct fb_info_aty128 *info, int bpp, int accel)
1540 {
1541 switch (bpp) {
1542 #ifdef FBCON_HAS_CFB8
1543 case 8:
1544 disp->dispsw = accel ? &fbcon_aty128_8 : &fbcon_cfb8;
1545 break;
1546 #endif
1547 #ifdef FBCON_HAS_CFB16
1548 case 16:
1549 disp->dispsw = accel ? &fbcon_aty128_16 : &fbcon_cfb16;
1550 disp->dispsw_data = info->fbcon_cmap.cfb16;
1551 break;
1552 #endif
1553 #ifdef FBCON_HAS_CFB24
1554 case 24:
1555 disp->dispsw = accel ? &fbcon_aty128_24 : &fbcon_cfb24;
1556 disp->dispsw_data = info->fbcon_cmap.cfb24;
1557 break;
1558 #endif
1559 #ifdef FBCON_HAS_CFB32
1560 case 32:
1561 disp->dispsw = accel ? &fbcon_aty128_32 : &fbcon_cfb32;
1562 disp->dispsw_data = info->fbcon_cmap.cfb32;
1563 break;
1564 #endif
1565 default:
1566 disp->dispsw = &fbcon_dummy;
1567 }
1568 }
1569
1570
1571 static void
aty128_encode_fix(struct fb_fix_screeninfo * fix,struct aty128fb_par * par,const struct fb_info_aty128 * info)1572 aty128_encode_fix(struct fb_fix_screeninfo *fix,
1573 struct aty128fb_par *par,
1574 const struct fb_info_aty128 *info)
1575 {
1576 memset(fix, 0, sizeof(struct fb_fix_screeninfo));
1577
1578 strcpy(fix->id, aty128fb_name);
1579
1580 fix->smem_start = (unsigned long)info->frame_buffer_phys;
1581 fix->mmio_start = (unsigned long)info->regbase_phys;
1582
1583 fix->smem_len = info->vram_size;
1584 fix->mmio_len = 0x1fff;
1585
1586 fix->type = FB_TYPE_PACKED_PIXELS;
1587 fix->type_aux = 0;
1588 fix->line_length = (par->crtc.vxres * par->crtc.bpp) >> 3;
1589 fix->visual = par->crtc.bpp == 8 ? FB_VISUAL_PSEUDOCOLOR
1590 : FB_VISUAL_DIRECTCOLOR;
1591 fix->ywrapstep = 0;
1592 fix->xpanstep = 8;
1593 fix->ypanstep = 1;
1594
1595 fix->accel = FB_ACCEL_ATI_RAGE128;
1596
1597 return;
1598 }
1599
1600
1601 /*
1602 * Get the Fixed Part of the Display
1603 */
1604 static int
aty128fb_get_fix(struct fb_fix_screeninfo * fix,int con,struct fb_info * fb)1605 aty128fb_get_fix(struct fb_fix_screeninfo *fix, int con, struct fb_info *fb)
1606 {
1607 const struct fb_info_aty128 *info = (struct fb_info_aty128 *)fb;
1608 struct aty128fb_par par;
1609
1610 if (con == -1)
1611 par = info->default_par;
1612 else
1613 aty128_decode_var(&fb_display[con].var, &par, info);
1614
1615 aty128_encode_fix(fix, &par, info);
1616
1617 return 0;
1618 }
1619
1620
1621 /*
1622 * Pan or Wrap the Display
1623 */
1624 static int
aty128fb_pan_display(struct fb_var_screeninfo * var,int con,struct fb_info * fb)1625 aty128fb_pan_display(struct fb_var_screeninfo *var, int con,
1626 struct fb_info *fb)
1627 {
1628 struct fb_info_aty128 *info = (struct fb_info_aty128 *)fb;
1629 struct aty128fb_par *par = &info->current_par;
1630 u32 xoffset, yoffset;
1631 u32 offset;
1632 u32 xres, yres;
1633
1634 xres = (((par->crtc.h_total >> 16) & 0xff) + 1) << 3;
1635 yres = ((par->crtc.v_total >> 16) & 0x7ff) + 1;
1636
1637 xoffset = (var->xoffset +7) & ~7;
1638 yoffset = var->yoffset;
1639
1640 if (xoffset+xres > par->crtc.vxres || yoffset+yres > par->crtc.vyres)
1641 return -EINVAL;
1642
1643 par->crtc.xoffset = xoffset;
1644 par->crtc.yoffset = yoffset;
1645
1646 offset = ((yoffset * par->crtc.vxres + xoffset)*(par->crtc.bpp >> 3)) & ~7;
1647
1648 if (par->crtc.bpp == 24)
1649 offset += 8 * (offset % 3); /* Must be multiple of 8 and 3 */
1650
1651 aty_st_le32(CRTC_OFFSET, offset);
1652
1653 return 0;
1654 }
1655
1656
1657 /*
1658 * Get the Colormap
1659 */
1660
1661 static int
aty128fb_get_cmap(struct fb_cmap * cmap,int kspc,int con,struct fb_info * info)1662 aty128fb_get_cmap(struct fb_cmap *cmap, int kspc, int con,
1663 struct fb_info *info)
1664 {
1665 struct fb_info_aty128 *fb = (struct fb_info_aty128 *)info;
1666 struct display *disp = (con < 0) ? info->disp : (fb_display + con);
1667
1668 if (con == fb->currcon) /* current console? */
1669 return fb_get_cmap(cmap, kspc, aty128_getcolreg, info);
1670 else if (disp->cmap.len) /* non default colormap? */
1671 fb_copy_cmap(&disp->cmap, cmap, kspc ? 0 : 2);
1672 else
1673 fb_copy_cmap(fb_default_cmap((disp->var.bits_per_pixel==8) ? 256 : 32),
1674 cmap, kspc ? 0 : 2);
1675
1676 return 0;
1677 }
1678
1679 /*
1680 * Set the Colormap
1681 */
1682
1683 static int
aty128fb_set_cmap(struct fb_cmap * cmap,int kspc,int con,struct fb_info * info)1684 aty128fb_set_cmap(struct fb_cmap *cmap, int kspc, int con,
1685 struct fb_info *info)
1686 {
1687 struct fb_info_aty128 *fb = (struct fb_info_aty128 *)info;
1688 struct display *disp = (con < 0) ? info->disp : (fb_display + con);
1689 unsigned int cmap_len = (disp->var.bits_per_pixel==8) ? 256 : 32;
1690
1691 if (disp->cmap.len != cmap_len) {
1692 int err = fb_alloc_cmap(&disp->cmap, cmap_len, 0);
1693
1694 if (!disp->cmap.len) { /* no colormap allocated? */
1695 int size = (disp->var.bits_per_pixel <= 8) ? 256 : 32;
1696 if ((err = fb_alloc_cmap(&disp->cmap, size, 0)))
1697 return err;
1698 }
1699 if (err) return err;
1700 }
1701
1702 if (con == fb->currcon) /* current console? */
1703 return fb_set_cmap(cmap, kspc, aty128_setcolreg, info);
1704 else
1705 fb_copy_cmap(cmap, &disp->cmap, kspc ? 0 : 1);
1706
1707 return 0;
1708 }
1709
1710 /*
1711 * Helper function to store a single palette register
1712 */
1713 static __inline__ void
aty128_st_pal(u_int regno,u_int red,u_int green,u_int blue,struct fb_info_aty128 * info)1714 aty128_st_pal(u_int regno, u_int red, u_int green, u_int blue,
1715 struct fb_info_aty128 *info)
1716 {
1717 /* Note: For now, on M3, we set palette on both heads, which may
1718 * be useless. Can someone with a M3 check this ?
1719 *
1720 * This code would still be useful if using the second CRTC to
1721 * do mirroring
1722 */
1723
1724 if (info->chip_gen == rage_M3) {
1725 #if 0
1726 aty_st_le32(DAC_CNTL, aty_ld_le32(DAC_CNTL) | DAC_PALETTE_ACCESS_CNTL);
1727 aty_st_8(PALETTE_INDEX, regno);
1728 aty_st_le32(PALETTE_DATA, (red<<16)|(green<<8)|blue);
1729 #endif
1730 aty_st_le32(DAC_CNTL, aty_ld_le32(DAC_CNTL) & ~DAC_PALETTE_ACCESS_CNTL);
1731 }
1732 aty_st_8(PALETTE_INDEX, regno);
1733 aty_st_le32(PALETTE_DATA, (red<<16)|(green<<8)|blue);
1734 }
1735
1736 static int
aty128fb_rasterimg(struct fb_info * info,int start)1737 aty128fb_rasterimg(struct fb_info *info, int start)
1738 {
1739 struct fb_info_aty128 *fb = (struct fb_info_aty128 *)info;
1740
1741 if (fb->blitter_may_be_busy)
1742 wait_for_idle(fb);
1743
1744 return 0;
1745 }
1746
1747
1748 int __init
aty128fb_setup(char * options)1749 aty128fb_setup(char *options)
1750 {
1751 char *this_opt;
1752
1753 if (!options || !*options)
1754 return 0;
1755
1756 while ((this_opt = strsep(&options, ",")) != 0) {
1757 if (!strncmp(this_opt, "font:", 5)) {
1758 char *p;
1759 int i;
1760
1761 p = this_opt +5;
1762 for (i = 0; i < sizeof(fontname) - 1; i++)
1763 if (!*p || *p == ' ' || *p == ',')
1764 break;
1765 memcpy(fontname, this_opt + 5, i);
1766 fontname[i] = 0;
1767 } else if (!strncmp(this_opt, "noaccel", 7)) {
1768 noaccel = 1;
1769 #ifdef CONFIG_PMAC_PBOOK
1770 } else if (!strncmp(this_opt, "lcd:", 4)) {
1771 default_lcd_on = simple_strtoul(this_opt+4, NULL, 0);
1772 } else if (!strncmp(this_opt, "crt:", 4)) {
1773 default_crt_on = simple_strtoul(this_opt+4, NULL, 0);
1774 #endif
1775 }
1776 #ifdef CONFIG_MTRR
1777 else if(!strncmp(this_opt, "nomtrr", 6)) {
1778 mtrr = 0;
1779 }
1780 #endif
1781 #ifdef CONFIG_PPC
1782 /* vmode and cmode depreciated */
1783 else if (!strncmp(this_opt, "vmode:", 6)) {
1784 unsigned int vmode = simple_strtoul(this_opt+6, NULL, 0);
1785 if (vmode > 0 && vmode <= VMODE_MAX)
1786 default_vmode = vmode;
1787 } else if (!strncmp(this_opt, "cmode:", 6)) {
1788 unsigned int cmode = simple_strtoul(this_opt+6, NULL, 0);
1789 switch (cmode) {
1790 case 0:
1791 case 8:
1792 default_cmode = CMODE_8;
1793 break;
1794 case 15:
1795 case 16:
1796 default_cmode = CMODE_16;
1797 break;
1798 case 24:
1799 case 32:
1800 default_cmode = CMODE_32;
1801 break;
1802 }
1803 }
1804 #endif /* CONFIG_PPC */
1805 else
1806 mode_option = this_opt;
1807 }
1808 return 0;
1809 }
1810
1811
1812 /*
1813 * Initialisation
1814 */
1815
1816 static int __init
aty128_init(struct fb_info_aty128 * info,const char * name)1817 aty128_init(struct fb_info_aty128 *info, const char *name)
1818 {
1819 struct fb_var_screeninfo var;
1820 u32 dac;
1821 int j, k;
1822 u8 chip_rev;
1823 const struct aty128_chip_info *aci = &aty128_pci_probe_list[0];
1824 char *video_card = "Rage128";
1825
1826 if (!info->vram_size) /* may have already been probed */
1827 info->vram_size = aty_ld_le32(CONFIG_MEMSIZE) & 0x03FFFFFF;
1828
1829 /* Get the chip revision */
1830 chip_rev = (aty_ld_le32(CONFIG_CNTL) >> 16) & 0x1F;
1831
1832 /* put a name with the face */
1833 while (aci->name && info->pdev->device != aci->device) { aci++; }
1834 video_card = (char *)aci->name;
1835 info->chip_gen = aci->chip_gen;
1836
1837 printk(KERN_INFO "aty128fb: %s [chip rev 0x%x] ", video_card, chip_rev);
1838
1839 if (info->vram_size % (1024 * 1024) == 0)
1840 printk("%dM %s\n", info->vram_size / (1024*1024), info->mem->name);
1841 else
1842 printk("%dk %s\n", info->vram_size / 1024, info->mem->name);
1843
1844 /* fill in info */
1845 strcpy(info->fb_info.modename, aty128fb_name);
1846 info->fb_info.node = -1;
1847 info->fb_info.fbops = &aty128fb_ops;
1848 info->fb_info.disp = &info->disp;
1849 strcpy(info->fb_info.fontname, fontname);
1850 info->fb_info.changevar = NULL;
1851 info->fb_info.switch_con = &aty128fbcon_switch;
1852 info->fb_info.updatevar = NULL;
1853 info->fb_info.blank = &aty128fbcon_blank;
1854 info->fb_info.flags = FBINFO_FLAG_DEFAULT;
1855 #ifdef CONFIG_PMAC_PBOOK
1856 info->lcd_on = default_lcd_on;
1857 info->crt_on = default_crt_on;
1858 #endif
1859
1860 var = default_var;
1861 #ifdef CONFIG_PPC
1862 if (_machine == _MACH_Pmac) {
1863 if (mode_option) {
1864 if (!mac_find_mode(&var, &info->fb_info, mode_option, 8))
1865 var = default_var;
1866 } else {
1867 if (default_vmode <= 0 || default_vmode > VMODE_MAX)
1868 default_vmode = VMODE_1024_768_60;
1869
1870 /* iMacs need that resolution
1871 * PowerMac2,1 first r128 iMacs
1872 * PowerMac2,2 summer 2000 iMacs
1873 * PowerMac4,1 january 2001 iMacs "flower power"
1874 */
1875 if (machine_is_compatible("PowerMac2,1") ||
1876 machine_is_compatible("PowerMac2,2") ||
1877 machine_is_compatible("PowerMac4,1"))
1878 default_vmode = VMODE_1024_768_75;
1879
1880 /* iBook SE */
1881 if (machine_is_compatible("PowerBook2,2"))
1882 default_vmode = VMODE_800_600_60;
1883
1884 /* PowerBook Firewire (Pismo), iBook Dual USB */
1885 if (machine_is_compatible("PowerBook3,1") ||
1886 machine_is_compatible("PowerBook4,1"))
1887 default_vmode = VMODE_1024_768_60;
1888
1889 /* PowerBook Titanium */
1890 if (machine_is_compatible("PowerBook3,2"))
1891 default_vmode = VMODE_1152_768_60;
1892
1893 if (default_cmode < CMODE_8 || default_cmode > CMODE_32)
1894 default_cmode = CMODE_8;
1895
1896 if (mac_vmode_to_var(default_vmode, default_cmode, &var))
1897 var = default_var;
1898 }
1899 } else
1900 #endif /* CONFIG_PPC */
1901 {
1902 if (fb_find_mode(&var, &info->fb_info, mode_option, NULL, 0,
1903 &defaultmode, 8) == 0)
1904 var = default_var;
1905 }
1906
1907 if (noaccel)
1908 var.accel_flags &= ~FB_ACCELF_TEXT;
1909 else
1910 var.accel_flags |= FB_ACCELF_TEXT;
1911
1912 if (aty128_decode_var(&var, &info->default_par, info)) {
1913 printk(KERN_ERR "aty128fb: Cannot set default mode.\n");
1914 return 0;
1915 }
1916
1917 /* load up the palette with default colors */
1918 for (j = 0; j < 16; j++) {
1919 k = color_table[j];
1920 info->palette[j].red = default_red[k];
1921 info->palette[j].green = default_grn[k];
1922 info->palette[j].blue = default_blu[k];
1923 }
1924
1925 /* setup the DAC the way we like it */
1926 dac = aty_ld_le32(DAC_CNTL);
1927 dac |= (DAC_8BIT_EN | DAC_RANGE_CNTL);
1928 dac |= DAC_MASK;
1929 if (info->chip_gen == rage_M3)
1930 dac |= DAC_PALETTE2_SNOOP_EN;
1931 aty_st_le32(DAC_CNTL, dac);
1932
1933 /* turn off bus mastering, just in case */
1934 aty_st_le32(BUS_CNTL, aty_ld_le32(BUS_CNTL) | BUS_MASTER_DIS);
1935
1936 aty128fb_set_var(&var, -1, &info->fb_info);
1937 aty128_init_engine(&info->default_par, info);
1938
1939 board_list = aty128_board_list_add(board_list, info);
1940
1941 if (register_framebuffer(&info->fb_info) < 0)
1942 return 0;
1943
1944 #ifdef CONFIG_PMAC_BACKLIGHT
1945 /* Could be extended to Rage128Pro LVDS output too */
1946 if (info->chip_gen == rage_M3)
1947 register_backlight_controller(&aty128_backlight_controller, info, "ati");
1948 #endif /* CONFIG_PMAC_BACKLIGHT */
1949 #ifdef CONFIG_PMAC_PBOOK
1950 if (!info->pdev)
1951 printk(KERN_WARNING "aty128fb: Not a PCI card, can't enable power management\n");
1952 else {
1953 info->pm_reg = pci_find_capability(info->pdev, PCI_CAP_ID_PM);
1954 pmu_register_sleep_notifier(&aty128_sleep_notifier);
1955 }
1956 #endif
1957
1958 printk(KERN_INFO "fb%d: %s frame buffer device on %s\n",
1959 GET_FB_IDX(info->fb_info.node), aty128fb_name, name);
1960
1961 return 1; /* success! */
1962 }
1963
1964
1965 /* add a new card to the list ++ajoshi */
1966 static struct
aty128_board_list_add(struct fb_info_aty128 * board_list,struct fb_info_aty128 * new_node)1967 fb_info_aty128 *aty128_board_list_add(struct fb_info_aty128 *board_list,
1968 struct fb_info_aty128 *new_node)
1969 {
1970 struct fb_info_aty128 *i_p = board_list;
1971
1972 new_node->next = NULL;
1973 if(board_list == NULL)
1974 return new_node;
1975 while(i_p->next != NULL)
1976 i_p = i_p->next;
1977 i_p->next = new_node;
1978
1979 return board_list;
1980 }
1981
1982
1983 int __init
aty128fb_init(void)1984 aty128fb_init(void)
1985 {
1986 #ifdef CONFIG_PCI
1987 struct pci_dev *pdev = NULL;
1988 const struct aty128_chip_info *aci = &aty128_pci_probe_list[0];
1989
1990 while (aci->name != NULL) {
1991 pdev = pci_find_device(PCI_VENDOR_ID_ATI, aci->device, pdev);
1992 while (pdev != NULL) {
1993 if (aty128_pci_register(pdev, aci) == 0)
1994 return 0;
1995 pdev = pci_find_device(PCI_VENDOR_ID_ATI, aci->device, pdev);
1996 }
1997 aci++;
1998 }
1999 #endif
2000
2001 return 0;
2002 }
2003
2004
2005 #ifdef CONFIG_PCI
2006 /* register a card ++ajoshi */
2007 static int __init
aty128_pci_register(struct pci_dev * pdev,const struct aty128_chip_info * aci)2008 aty128_pci_register(struct pci_dev *pdev,
2009 const struct aty128_chip_info *aci)
2010 {
2011 struct fb_info_aty128 *info = NULL;
2012 unsigned long fb_addr, reg_addr;
2013 int err;
2014 #if !defined(CONFIG_PPC) && !defined(__sparc__)
2015 char *bios_seg = NULL;
2016 #endif
2017
2018 /* Enable device in PCI config */
2019 if ((err = pci_enable_device(pdev))) {
2020 printk(KERN_ERR "aty128fb: Cannot enable PCI device: %d\n",
2021 err);
2022 return -ENODEV;
2023 }
2024
2025 fb_addr = pci_resource_start(pdev, 0);
2026 if (!request_mem_region(fb_addr, pci_resource_len(pdev, 0),
2027 "aty128fb FB")) {
2028 printk(KERN_ERR "aty128fb: cannot reserve frame "
2029 "buffer memory\n");
2030 goto err_free_fb;
2031 }
2032
2033 reg_addr = pci_resource_start(pdev, 2);
2034 if (!request_mem_region(reg_addr, pci_resource_len(pdev, 2),
2035 "aty128fb MMIO")) {
2036 printk(KERN_ERR "aty128fb: cannot reserve MMIO region\n");
2037 goto err_free_mmio;
2038 }
2039
2040 /* We have the resources. Now virtualize them */
2041 if (!(info = kmalloc(sizeof(struct fb_info_aty128), GFP_ATOMIC))) {
2042 printk(KERN_ERR "aty128fb: can't alloc fb_info_aty128\n");
2043 goto err_unmap_out;
2044 }
2045 memset(info, 0, sizeof(struct fb_info_aty128));
2046
2047 /* Copy PCI device info into info->pdev */
2048 info->pdev = pdev;
2049
2050 info->currcon = -1;
2051
2052 /* Virtualize mmio region */
2053 info->regbase_phys = reg_addr;
2054 info->regbase = ioremap(reg_addr, 0x1FFF);
2055
2056 if (!info->regbase)
2057 goto err_free_info;
2058
2059 /* Grab memory size from the card */
2060 info->vram_size = aty_ld_le32(CONFIG_MEMSIZE) & 0x03FFFFFF;
2061
2062 /* Virtualize the framebuffer */
2063 info->frame_buffer_phys = fb_addr;
2064 info->frame_buffer = ioremap(fb_addr, info->vram_size);
2065
2066 if (!info->frame_buffer) {
2067 iounmap((void *)info->regbase);
2068 goto err_free_info;
2069 }
2070
2071 /* If we can't test scratch registers, something is seriously wrong */
2072 if (!register_test(info)) {
2073 printk(KERN_ERR "aty128fb: Can't write to video register!\n");
2074 goto err_out;
2075 }
2076
2077 #if !defined(CONFIG_PPC) && !defined(__sparc__)
2078 if (!(bios_seg = aty128find_ROM(info)))
2079 printk(KERN_INFO "aty128fb: Rage128 BIOS not located. "
2080 "Guessing...\n");
2081 else {
2082 printk(KERN_INFO "aty128fb: Rage128 BIOS located at "
2083 "segment %4.4lX\n", (unsigned long)bios_seg);
2084 aty128_get_pllinfo(info, bios_seg);
2085 }
2086 #endif
2087 aty128_timings(info);
2088
2089 if (!aty128_init(info, "PCI"))
2090 goto err_out;
2091
2092 #ifdef CONFIG_MTRR
2093 if (mtrr) {
2094 info->mtrr.vram = mtrr_add(info->frame_buffer_phys,
2095 info->vram_size, MTRR_TYPE_WRCOMB, 1);
2096 info->mtrr.vram_valid = 1;
2097 /* let there be speed */
2098 printk(KERN_INFO "aty128fb: Rage128 MTRR set to ON\n");
2099 }
2100 #endif /* CONFIG_MTRR */
2101
2102 #ifdef CONFIG_FB_COMPAT_XPMAC
2103 if (!console_fb_info)
2104 console_fb_info = &info->fb_info;
2105 #endif
2106
2107 return 0;
2108
2109 err_out:
2110 iounmap(info->frame_buffer);
2111 iounmap(info->regbase);
2112 err_free_info:
2113 kfree(info);
2114 err_unmap_out:
2115 release_mem_region(pci_resource_start(pdev, 2),
2116 pci_resource_len(pdev, 2));
2117 err_free_mmio:
2118 release_mem_region(pci_resource_start(pdev, 0),
2119 pci_resource_len(pdev, 0));
2120 err_free_fb:
2121 release_mem_region(pci_resource_start(pdev, 1),
2122 pci_resource_len(pdev, 1));
2123 return -ENODEV;
2124 }
2125 #endif /* CONFIG_PCI */
2126
2127
2128 /* PPC and Sparc cannot read video ROM */
2129 #if !defined(CONFIG_PPC) && !defined(__sparc__)
2130 static char __init
aty128find_ROM(struct fb_info_aty128 * info)2131 *aty128find_ROM(struct fb_info_aty128 *info)
2132 {
2133 u32 segstart;
2134 char *rom_base;
2135 char *rom;
2136 int stage;
2137 int i,j;
2138 char aty_rom_sig[] = "761295520"; /* ATI ROM Signature */
2139 char *R128_sig[] = {
2140 "R128", /* Rage128 ROM identifier */
2141 "128b"
2142 };
2143
2144 for (segstart=0x000c0000; segstart<0x000f0000; segstart+=0x00001000) {
2145 stage = 1;
2146
2147 rom_base = (char *)ioremap(segstart, 0x1000);
2148
2149 if ((*rom_base == 0x55) && (((*(rom_base + 1)) & 0xff) == 0xaa))
2150 stage = 2;
2151
2152 if (stage != 2) {
2153 iounmap(rom_base);
2154 continue;
2155 }
2156 rom = rom_base;
2157
2158 for (i = 0; (i < 128 - strlen(aty_rom_sig)) && (stage != 3); i++) {
2159 if (aty_rom_sig[0] == *rom)
2160 if (strncmp(aty_rom_sig, rom,
2161 strlen(aty_rom_sig)) == 0)
2162 stage = 3;
2163 rom++;
2164 }
2165 if (stage != 3) {
2166 iounmap(rom_base);
2167 continue;
2168 }
2169 rom = rom_base;
2170
2171 /* ATI signature found. Let's see if it's a Rage128 */
2172 for (i = 0; (i < 512) && (stage != 4); i++) {
2173 for(j = 0;j < sizeof(R128_sig)/sizeof(char *);j++) {
2174 if (R128_sig[j][0] == *rom)
2175 if (strncmp(R128_sig[j], rom,
2176 strlen(R128_sig[j])) == 0) {
2177 stage = 4;
2178 break;
2179 }
2180 }
2181 rom++;
2182 }
2183 if (stage != 4) {
2184 iounmap(rom_base);
2185 continue;
2186 }
2187
2188 return rom_base;
2189 }
2190
2191 return NULL;
2192 }
2193
2194
2195 static void __init
aty128_get_pllinfo(struct fb_info_aty128 * info,char * bios_seg)2196 aty128_get_pllinfo(struct fb_info_aty128 *info, char *bios_seg)
2197 {
2198 void *bios_header;
2199 void *header_ptr;
2200 u16 bios_header_offset, pll_info_offset;
2201 PLL_BLOCK pll;
2202
2203 bios_header = bios_seg + 0x48L;
2204 header_ptr = bios_header;
2205
2206 bios_header_offset = readw(header_ptr);
2207 bios_header = bios_seg + bios_header_offset;
2208 bios_header += 0x30;
2209
2210 header_ptr = bios_header;
2211 pll_info_offset = readw(header_ptr);
2212 header_ptr = bios_seg + pll_info_offset;
2213
2214 memcpy_fromio(&pll, header_ptr, 50);
2215
2216 info->constants.ppll_max = pll.PCLK_max_freq;
2217 info->constants.ppll_min = pll.PCLK_min_freq;
2218 info->constants.xclk = (u32)pll.XCLK;
2219 info->constants.ref_divider = (u32)pll.PCLK_ref_divider;
2220 info->constants.dotclock = (u32)pll.PCLK_ref_freq;
2221
2222 DBG("ppll_max %d ppll_min %d xclk %d ref_divider %d dotclock %d\n",
2223 info->constants.ppll_max, info->constants.ppll_min,
2224 info->constants.xclk, info->constants.ref_divider,
2225 info->constants.dotclock);
2226
2227 }
2228 #endif /* !CONFIG_PPC */
2229
2230
2231 /* fill in known card constants if pll_block is not available */
2232 static void __init
aty128_timings(struct fb_info_aty128 * info)2233 aty128_timings(struct fb_info_aty128 *info)
2234 {
2235 #ifdef CONFIG_PPC
2236 /* instead of a table lookup, assume OF has properly
2237 * setup the PLL registers and use their values
2238 * to set the XCLK values and reference divider values */
2239
2240 u32 x_mpll_ref_fb_div;
2241 u32 xclk_cntl;
2242 u32 Nx, M;
2243 unsigned PostDivSet[] =
2244 { 0, 1, 2, 4, 8, 3, 6, 12 };
2245 #endif
2246
2247 if (!info->constants.dotclock)
2248 info->constants.dotclock = 2950;
2249
2250 #ifdef CONFIG_PPC
2251 x_mpll_ref_fb_div = aty_ld_pll(X_MPLL_REF_FB_DIV);
2252 xclk_cntl = aty_ld_pll(XCLK_CNTL) & 0x7;
2253 Nx = (x_mpll_ref_fb_div & 0x00ff00) >> 8;
2254 M = x_mpll_ref_fb_div & 0x0000ff;
2255
2256 info->constants.xclk = round_div((2 * Nx *
2257 info->constants.dotclock), (M * PostDivSet[xclk_cntl]));
2258
2259 info->constants.ref_divider =
2260 aty_ld_pll(PPLL_REF_DIV) & PPLL_REF_DIV_MASK;
2261 #endif
2262
2263 if (!info->constants.ref_divider) {
2264 info->constants.ref_divider = 0x3b;
2265
2266 aty_st_pll(X_MPLL_REF_FB_DIV, 0x004c4c1e);
2267 aty_pll_writeupdate(info);
2268 }
2269 aty_st_pll(PPLL_REF_DIV, info->constants.ref_divider);
2270 aty_pll_writeupdate(info);
2271
2272 /* from documentation */
2273 if (!info->constants.ppll_min)
2274 info->constants.ppll_min = 12500;
2275 if (!info->constants.ppll_max)
2276 info->constants.ppll_max = 25000; /* 23000 on some cards? */
2277 if (!info->constants.xclk)
2278 info->constants.xclk = 0x1d4d; /* same as mclk */
2279
2280 info->constants.fifo_width = 128;
2281 info->constants.fifo_depth = 32;
2282
2283 switch (aty_ld_le32(MEM_CNTL) & 0x3) {
2284 case 0:
2285 info->mem = &sdr_128;
2286 break;
2287 case 1:
2288 info->mem = &sdr_sgram;
2289 break;
2290 case 2:
2291 info->mem = &ddr_sgram;
2292 break;
2293 default:
2294 info->mem = &sdr_sgram;
2295 }
2296 }
2297
2298
2299 static int
aty128fbcon_switch(int con,struct fb_info * fb)2300 aty128fbcon_switch(int con, struct fb_info *fb)
2301 {
2302 struct fb_info_aty128 *info = (struct fb_info_aty128 *)fb;
2303 struct aty128fb_par par;
2304
2305 /* Do we have to save the colormap? */
2306 if (fb_display[info->currcon].cmap.len)
2307 fb_get_cmap(&fb_display[info->currcon].cmap, 1,
2308 aty128_getcolreg, fb);
2309
2310 /* set the current console */
2311 info->currcon = con;
2312
2313 aty128_decode_var(&fb_display[con].var, &par, info);
2314 aty128_set_par(&par, info);
2315
2316 aty128_set_dispsw(&fb_display[con], info, par.crtc.bpp,
2317 par.accel_flags & FB_ACCELF_TEXT);
2318
2319 do_install_cmap(con, fb);
2320
2321 return 1;
2322 }
2323
2324
2325 /*
2326 * Blank the display.
2327 */
2328 static void
aty128fbcon_blank(int blank,struct fb_info * fb)2329 aty128fbcon_blank(int blank, struct fb_info *fb)
2330 {
2331 struct fb_info_aty128 *info = (struct fb_info_aty128 *)fb;
2332 u8 state = 0;
2333
2334 #ifdef CONFIG_PMAC_BACKLIGHT
2335 if ((_machine == _MACH_Pmac) && blank)
2336 set_backlight_enable(0);
2337 #endif /* CONFIG_PMAC_BACKLIGHT */
2338
2339 if (blank & VESA_VSYNC_SUSPEND)
2340 state |= 2;
2341 if (blank & VESA_HSYNC_SUSPEND)
2342 state |= 1;
2343 if (blank & VESA_POWERDOWN)
2344 state |= 4;
2345
2346 aty_st_8(CRTC_EXT_CNTL+1, state);
2347
2348 #ifdef CONFIG_PMAC_PBOOK
2349 if (info->chip_gen == rage_M3) {
2350 aty128_set_crt_enable(info, info->crt_on && !blank);
2351 aty128_set_lcd_enable(info, info->lcd_on && !blank);
2352 }
2353 #endif
2354 #ifdef CONFIG_PMAC_BACKLIGHT
2355 if ((_machine == _MACH_Pmac) && !blank)
2356 set_backlight_enable(1);
2357 #endif /* CONFIG_PMAC_BACKLIGHT */
2358 }
2359
2360
2361 /*
2362 * Read a single color register and split it into
2363 * colors/transparent. Return != 0 for invalid regno.
2364 */
2365 static int
aty128_getcolreg(u_int regno,u_int * red,u_int * green,u_int * blue,u_int * transp,struct fb_info * fb)2366 aty128_getcolreg(u_int regno, u_int *red, u_int *green, u_int *blue,
2367 u_int *transp, struct fb_info *fb)
2368 {
2369 struct fb_info_aty128 *info = (struct fb_info_aty128 *) fb;
2370
2371 if (regno > 255)
2372 return 1;
2373
2374 *red = (info->palette[regno].red<<8) | info->palette[regno].red;
2375 *green = (info->palette[regno].green<<8) | info->palette[regno].green;
2376 *blue = (info->palette[regno].blue<<8) | info->palette[regno].blue;
2377 *transp = 0;
2378
2379 return 0;
2380 }
2381
2382 /*
2383 * Set a single color register. The values supplied are already
2384 * rounded down to the hardware's capabilities (according to the
2385 * entries in the var structure). Return != 0 for invalid regno.
2386 */
2387 static int
aty128_setcolreg(u_int regno,u_int red,u_int green,u_int blue,u_int transp,struct fb_info * fb)2388 aty128_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
2389 u_int transp, struct fb_info *fb)
2390 {
2391 struct fb_info_aty128 *info = (struct fb_info_aty128 *)fb;
2392 u32 palreg;
2393
2394 if (regno > 255)
2395 return 1;
2396
2397 red >>= 8;
2398 green >>= 8;
2399 blue >>= 8;
2400 info->palette[regno].red = red;
2401 info->palette[regno].green = green;
2402 info->palette[regno].blue = blue;
2403
2404 /* Note: For now, on M3, we set palette on both heads, which may
2405 * be useless. Can someone with a M3 check this ? */
2406
2407 /* initialize gamma ramp for hi-color+ */
2408
2409 if ((info->current_par.crtc.bpp > 8) && (regno == 0)) {
2410 int i;
2411
2412 for (i=0; i<256; i++)
2413 aty128_st_pal(i, i, i, i, info);
2414 }
2415
2416 /* initialize palette */
2417
2418 palreg = regno;
2419
2420 if (info->current_par.crtc.bpp == 16)
2421 palreg = regno * 8;
2422
2423 if (info->current_par.crtc.depth == 16) {
2424 aty128_st_pal(palreg/2, info->palette[regno/2].red, green,
2425 info->palette[regno/2].blue, info);
2426 green = info->palette[regno*2].green;
2427 }
2428
2429 if (info->current_par.crtc.bpp == 8 || regno < 32)
2430 aty128_st_pal(palreg, red, green, blue, info);
2431
2432 if (regno < 16)
2433 switch (info->current_par.crtc.depth) {
2434 #ifdef FBCON_HAS_CFB16
2435 case 15:
2436 info->fbcon_cmap.cfb16[regno] = (regno << 10) | (regno << 5) |
2437 regno;
2438 break;
2439 case 16:
2440 info->fbcon_cmap.cfb16[regno] = (regno << 11) | (regno << 5) |
2441 regno;
2442 break;
2443 #endif
2444 #ifdef FBCON_HAS_CFB24
2445 case 24:
2446 info->fbcon_cmap.cfb24[regno] = (regno << 16) | (regno << 8) |
2447 regno;
2448 break;
2449 #endif
2450 #ifdef FBCON_HAS_CFB32
2451 case 32: {
2452 u32 i = (regno << 8) | regno;
2453 info->fbcon_cmap.cfb32[regno] = (i << 16) | i;
2454 break;
2455 }
2456 #endif
2457 }
2458 return 0;
2459 }
2460
2461
2462 static void
do_install_cmap(int con,struct fb_info * info)2463 do_install_cmap(int con, struct fb_info *info)
2464 {
2465 struct display *disp = (con < 0) ? info->disp : (fb_display + con);
2466
2467 if (disp->cmap.len)
2468 fb_set_cmap(&disp->cmap, 1, aty128_setcolreg, info);
2469 else
2470 fb_set_cmap(fb_default_cmap((disp->var.bits_per_pixel==8) ? 256 :32),
2471 1, aty128_setcolreg, info);
2472 }
2473
2474 #define ATY_MIRROR_LCD_ON 0x00000001
2475 #define ATY_MIRROR_CRT_ON 0x00000002
2476
2477 /* out param: u32* backlight value: 0 to 15 */
2478 #define FBIO_ATY128_GET_MIRROR _IOR('@', 1, sizeof(__u32*))
2479 /* in param: u32* backlight value: 0 to 15 */
2480 #define FBIO_ATY128_SET_MIRROR _IOW('@', 2, sizeof(__u32*))
2481
aty128fb_ioctl(struct inode * inode,struct file * file,u_int cmd,u_long arg,int con,struct fb_info * info)2482 static int aty128fb_ioctl(struct inode *inode, struct file *file, u_int cmd,
2483 u_long arg, int con, struct fb_info *info)
2484 {
2485 struct fb_info_aty128 *fb = (struct fb_info_aty128 *)info;
2486 u32 value;
2487 int rc;
2488
2489 switch (cmd) {
2490 #ifdef CONFIG_PMAC_PBOOK
2491 case FBIO_ATY128_SET_MIRROR:
2492 if (fb->chip_gen != rage_M3)
2493 return -EINVAL;
2494 rc = get_user(value, (__u32*)arg);
2495 if (rc)
2496 return rc;
2497 fb->lcd_on = (value & 0x01) != 0;
2498 fb->crt_on = (value & 0x02) != 0;
2499 if (!fb->crt_on && !fb->lcd_on)
2500 fb->lcd_on = 1;
2501 aty128_set_crt_enable(fb, fb->crt_on);
2502 aty128_set_lcd_enable(fb, fb->lcd_on);
2503 break;
2504 case FBIO_ATY128_GET_MIRROR:
2505 if (fb->chip_gen != rage_M3)
2506 return -EINVAL;
2507 value = (fb->crt_on << 1) | fb->lcd_on;
2508 return put_user(value, (__u32*)arg);
2509 #endif
2510 default:
2511 return -EINVAL;
2512 }
2513 return 0;
2514 }
2515
2516 #ifdef CONFIG_PMAC_BACKLIGHT
2517 static int backlight_conv[] = {
2518 0xff, 0xc0, 0xb5, 0xaa, 0x9f, 0x94, 0x89, 0x7e,
2519 0x73, 0x68, 0x5d, 0x52, 0x47, 0x3c, 0x31, 0x24
2520 };
2521
2522 /* We turn off the LCD completely instead of just dimming the backlight.
2523 * This provides greater power saving and the display is useless without
2524 * backlight anyway
2525 */
2526 #define BACKLIGHT_LVDS_OFF
2527 /* That one prevents proper CRT output with LCD off */
2528 #undef BACKLIGHT_DAC_OFF
2529
2530 static int
aty128_set_backlight_enable(int on,int level,void * data)2531 aty128_set_backlight_enable(int on, int level, void* data)
2532 {
2533 struct fb_info_aty128 *info = (struct fb_info_aty128 *)data;
2534 unsigned int reg = aty_ld_le32(LVDS_GEN_CNTL);
2535
2536 if (!info->lcd_on)
2537 on = 0;
2538 reg |= LVDS_BL_MOD_EN | LVDS_BLON;
2539 if (on && level > BACKLIGHT_OFF) {
2540 reg |= LVDS_DIGION;
2541 if ((reg & LVDS_ON) == 0) {
2542 reg &= ~LVDS_BLON;
2543 aty_st_le32(LVDS_GEN_CNTL, reg);
2544 (void)aty_ld_le32(LVDS_GEN_CNTL);
2545 mdelay(10);
2546 reg |= LVDS_BLON;
2547 aty_st_le32(LVDS_GEN_CNTL, reg);
2548 }
2549 reg &= ~LVDS_BL_MOD_LEVEL_MASK;
2550 reg |= (backlight_conv[level] << LVDS_BL_MOD_LEVEL_SHIFT);
2551 #ifdef BACKLIGHT_LVDS_OFF
2552 reg |= LVDS_ON | LVDS_EN;
2553 reg &= ~LVDS_DISPLAY_DIS;
2554 #endif
2555 aty_st_le32(LVDS_GEN_CNTL, reg);
2556 #ifdef BACKLIGHT_DAC_OFF
2557 aty_st_le32(DAC_CNTL, aty_ld_le32(DAC_CNTL) & (~DAC_PDWN));
2558 #endif
2559 } else {
2560 reg &= ~LVDS_BL_MOD_LEVEL_MASK;
2561 reg |= (backlight_conv[0] << LVDS_BL_MOD_LEVEL_SHIFT);
2562 #ifdef BACKLIGHT_LVDS_OFF
2563 reg |= LVDS_DISPLAY_DIS;
2564 aty_st_le32(LVDS_GEN_CNTL, reg);
2565 (void)aty_ld_le32(LVDS_GEN_CNTL);
2566 udelay(10);
2567 reg &= ~(LVDS_ON | LVDS_EN | LVDS_BLON | LVDS_DIGION);
2568 #endif
2569 aty_st_le32(LVDS_GEN_CNTL, reg);
2570 #ifdef BACKLIGHT_DAC_OFF
2571 aty_st_le32(DAC_CNTL, aty_ld_le32(DAC_CNTL) | DAC_PDWN);
2572 #endif
2573 }
2574
2575 return 0;
2576 }
2577
2578 static int
aty128_set_backlight_level(int level,void * data)2579 aty128_set_backlight_level(int level, void* data)
2580 {
2581 return aty128_set_backlight_enable(1, level, data);
2582 }
2583 #endif /* CONFIG_PMAC_BACKLIGHT */
2584
2585 /*
2586 * Accelerated functions
2587 */
2588
2589 static inline void
aty128_rectcopy(int srcx,int srcy,int dstx,int dsty,u_int width,u_int height,struct fb_info_aty128 * info)2590 aty128_rectcopy(int srcx, int srcy, int dstx, int dsty,
2591 u_int width, u_int height,
2592 struct fb_info_aty128 *info)
2593 {
2594 u32 save_dp_datatype, save_dp_cntl, dstval;
2595
2596 if (!width || !height)
2597 return;
2598
2599 dstval = depth_to_dst(info->current_par.crtc.depth);
2600 if (dstval == DST_24BPP) {
2601 srcx *= 3;
2602 dstx *= 3;
2603 width *= 3;
2604 } else if (dstval == -EINVAL) {
2605 printk("aty128fb: invalid depth or RGBA\n");
2606 return;
2607 }
2608
2609 wait_for_fifo(2, info);
2610 save_dp_datatype = aty_ld_le32(DP_DATATYPE);
2611 save_dp_cntl = aty_ld_le32(DP_CNTL);
2612
2613 wait_for_fifo(6, info);
2614 aty_st_le32(SRC_Y_X, (srcy << 16) | srcx);
2615 aty_st_le32(DP_MIX, ROP3_SRCCOPY | DP_SRC_RECT);
2616 aty_st_le32(DP_CNTL, DST_X_LEFT_TO_RIGHT | DST_Y_TOP_TO_BOTTOM);
2617 aty_st_le32(DP_DATATYPE, save_dp_datatype | dstval | SRC_DSTCOLOR);
2618
2619 aty_st_le32(DST_Y_X, (dsty << 16) | dstx);
2620 aty_st_le32(DST_HEIGHT_WIDTH, (height << 16) | width);
2621
2622 info->blitter_may_be_busy = 1;
2623
2624 wait_for_fifo(2, info);
2625 aty_st_le32(DP_DATATYPE, save_dp_datatype);
2626 aty_st_le32(DP_CNTL, save_dp_cntl);
2627 }
2628
2629
2630 /*
2631 * Text mode accelerated functions
2632 */
2633
2634 static void
fbcon_aty128_bmove(struct display * p,int sy,int sx,int dy,int dx,int height,int width)2635 fbcon_aty128_bmove(struct display *p, int sy, int sx, int dy, int dx,
2636 int height, int width)
2637 {
2638 sx *= fontwidth(p);
2639 sy *= fontheight(p);
2640 dx *= fontwidth(p);
2641 dy *= fontheight(p);
2642 width *= fontwidth(p);
2643 height *= fontheight(p);
2644
2645 aty128_rectcopy(sx, sy, dx, dy, width, height,
2646 (struct fb_info_aty128 *)p->fb_info);
2647 }
2648
2649
2650 #ifdef FBCON_HAS_CFB8
fbcon_aty8_putc(struct vc_data * conp,struct display * p,int c,int yy,int xx)2651 static void fbcon_aty8_putc(struct vc_data *conp, struct display *p,
2652 int c, int yy, int xx)
2653 {
2654 struct fb_info_aty128 *fb = (struct fb_info_aty128 *)(p->fb_info);
2655
2656 if (fb->blitter_may_be_busy)
2657 wait_for_idle(fb);
2658
2659 fbcon_cfb8_putc(conp, p, c, yy, xx);
2660 }
2661
2662
fbcon_aty8_putcs(struct vc_data * conp,struct display * p,const unsigned short * s,int count,int yy,int xx)2663 static void fbcon_aty8_putcs(struct vc_data *conp, struct display *p,
2664 const unsigned short *s, int count,
2665 int yy, int xx)
2666 {
2667 struct fb_info_aty128 *fb = (struct fb_info_aty128 *)(p->fb_info);
2668
2669 if (fb->blitter_may_be_busy)
2670 wait_for_idle(fb);
2671
2672 fbcon_cfb8_putcs(conp, p, s, count, yy, xx);
2673 }
2674
2675
fbcon_aty8_clear_margins(struct vc_data * conp,struct display * p,int bottom_only)2676 static void fbcon_aty8_clear_margins(struct vc_data *conp,
2677 struct display *p, int bottom_only)
2678 {
2679 struct fb_info_aty128 *fb = (struct fb_info_aty128 *)(p->fb_info);
2680
2681 if (fb->blitter_may_be_busy)
2682 wait_for_idle(fb);
2683
2684 fbcon_cfb8_clear_margins(conp, p, bottom_only);
2685 }
2686
2687 static struct display_switch fbcon_aty128_8 = {
2688 setup: fbcon_cfb8_setup,
2689 bmove: fbcon_aty128_bmove,
2690 clear: fbcon_cfb8_clear,
2691 putc: fbcon_aty8_putc,
2692 putcs: fbcon_aty8_putcs,
2693 revc: fbcon_cfb8_revc,
2694 clear_margins: fbcon_aty8_clear_margins,
2695 fontwidthmask: FONTWIDTH(4)|FONTWIDTH(8)|FONTWIDTH(12)|FONTWIDTH(16)
2696 };
2697 #endif
2698 #ifdef FBCON_HAS_CFB16
fbcon_aty16_putc(struct vc_data * conp,struct display * p,int c,int yy,int xx)2699 static void fbcon_aty16_putc(struct vc_data *conp, struct display *p,
2700 int c, int yy, int xx)
2701 {
2702 struct fb_info_aty128 *fb = (struct fb_info_aty128 *)(p->fb_info);
2703
2704 if (fb->blitter_may_be_busy)
2705 wait_for_idle(fb);
2706
2707 fbcon_cfb16_putc(conp, p, c, yy, xx);
2708 }
2709
2710
fbcon_aty16_putcs(struct vc_data * conp,struct display * p,const unsigned short * s,int count,int yy,int xx)2711 static void fbcon_aty16_putcs(struct vc_data *conp, struct display *p,
2712 const unsigned short *s, int count,
2713 int yy, int xx)
2714 {
2715 struct fb_info_aty128 *fb = (struct fb_info_aty128 *)(p->fb_info);
2716
2717 if (fb->blitter_may_be_busy)
2718 wait_for_idle(fb);
2719
2720 fbcon_cfb16_putcs(conp, p, s, count, yy, xx);
2721 }
2722
2723
fbcon_aty16_clear_margins(struct vc_data * conp,struct display * p,int bottom_only)2724 static void fbcon_aty16_clear_margins(struct vc_data *conp,
2725 struct display *p, int bottom_only)
2726 {
2727 struct fb_info_aty128 *fb = (struct fb_info_aty128 *)(p->fb_info);
2728
2729 if (fb->blitter_may_be_busy)
2730 wait_for_idle(fb);
2731
2732 fbcon_cfb16_clear_margins(conp, p, bottom_only);
2733 }
2734
2735 static struct display_switch fbcon_aty128_16 = {
2736 setup: fbcon_cfb16_setup,
2737 bmove: fbcon_aty128_bmove,
2738 clear: fbcon_cfb16_clear,
2739 putc: fbcon_aty16_putc,
2740 putcs: fbcon_aty16_putcs,
2741 revc: fbcon_cfb16_revc,
2742 clear_margins: fbcon_aty16_clear_margins,
2743 fontwidthmask: FONTWIDTH(4)|FONTWIDTH(8)|FONTWIDTH(12)|FONTWIDTH(16)
2744 };
2745 #endif
2746 #ifdef FBCON_HAS_CFB24
fbcon_aty24_putc(struct vc_data * conp,struct display * p,int c,int yy,int xx)2747 static void fbcon_aty24_putc(struct vc_data *conp, struct display *p,
2748 int c, int yy, int xx)
2749 {
2750 struct fb_info_aty128 *fb = (struct fb_info_aty128 *)(p->fb_info);
2751
2752 if (fb->blitter_may_be_busy)
2753 wait_for_idle(fb);
2754
2755 fbcon_cfb24_putc(conp, p, c, yy, xx);
2756 }
2757
2758
fbcon_aty24_putcs(struct vc_data * conp,struct display * p,const unsigned short * s,int count,int yy,int xx)2759 static void fbcon_aty24_putcs(struct vc_data *conp, struct display *p,
2760 const unsigned short *s, int count,
2761 int yy, int xx)
2762 {
2763 struct fb_info_aty128 *fb = (struct fb_info_aty128 *)(p->fb_info);
2764
2765 if (fb->blitter_may_be_busy)
2766 wait_for_idle(fb);
2767
2768 fbcon_cfb24_putcs(conp, p, s, count, yy, xx);
2769 }
2770
2771
fbcon_aty24_clear_margins(struct vc_data * conp,struct display * p,int bottom_only)2772 static void fbcon_aty24_clear_margins(struct vc_data *conp,
2773 struct display *p, int bottom_only)
2774 {
2775 struct fb_info_aty128 *fb = (struct fb_info_aty128 *)(p->fb_info);
2776
2777 if (fb->blitter_may_be_busy)
2778 wait_for_idle(fb);
2779
2780 fbcon_cfb24_clear_margins(conp, p, bottom_only);
2781 }
2782
2783 static struct display_switch fbcon_aty128_24 = {
2784 setup: fbcon_cfb24_setup,
2785 bmove: fbcon_aty128_bmove,
2786 clear: fbcon_cfb24_clear,
2787 putc: fbcon_aty24_putc,
2788 putcs: fbcon_aty24_putcs,
2789 revc: fbcon_cfb24_revc,
2790 clear_margins: fbcon_aty24_clear_margins,
2791 fontwidthmask: FONTWIDTH(4)|FONTWIDTH(8)|FONTWIDTH(12)|FONTWIDTH(16)
2792 };
2793 #endif
2794 #ifdef FBCON_HAS_CFB32
fbcon_aty32_putc(struct vc_data * conp,struct display * p,int c,int yy,int xx)2795 static void fbcon_aty32_putc(struct vc_data *conp, struct display *p,
2796 int c, int yy, int xx)
2797 {
2798 struct fb_info_aty128 *fb = (struct fb_info_aty128 *)(p->fb_info);
2799
2800 if (fb->blitter_may_be_busy)
2801 wait_for_idle(fb);
2802
2803 fbcon_cfb32_putc(conp, p, c, yy, xx);
2804 }
2805
2806
fbcon_aty32_putcs(struct vc_data * conp,struct display * p,const unsigned short * s,int count,int yy,int xx)2807 static void fbcon_aty32_putcs(struct vc_data *conp, struct display *p,
2808 const unsigned short *s, int count,
2809 int yy, int xx)
2810 {
2811 struct fb_info_aty128 *fb = (struct fb_info_aty128 *)(p->fb_info);
2812
2813 if (fb->blitter_may_be_busy)
2814 wait_for_idle(fb);
2815
2816 fbcon_cfb32_putcs(conp, p, s, count, yy, xx);
2817 }
2818
2819
fbcon_aty32_clear_margins(struct vc_data * conp,struct display * p,int bottom_only)2820 static void fbcon_aty32_clear_margins(struct vc_data *conp,
2821 struct display *p, int bottom_only)
2822 {
2823 struct fb_info_aty128 *fb = (struct fb_info_aty128 *)(p->fb_info);
2824
2825 if (fb->blitter_may_be_busy)
2826 wait_for_idle(fb);
2827
2828 fbcon_cfb32_clear_margins(conp, p, bottom_only);
2829 }
2830
2831 static struct display_switch fbcon_aty128_32 = {
2832 setup: fbcon_cfb32_setup,
2833 bmove: fbcon_aty128_bmove,
2834 clear: fbcon_cfb32_clear,
2835 putc: fbcon_aty32_putc,
2836 putcs: fbcon_aty32_putcs,
2837 revc: fbcon_cfb32_revc,
2838 clear_margins: fbcon_aty32_clear_margins,
2839 fontwidthmask: FONTWIDTH(4)|FONTWIDTH(8)|FONTWIDTH(12)|FONTWIDTH(16)
2840 };
2841 #endif
2842
2843 #ifdef CONFIG_PMAC_PBOOK
2844 static void
aty128_set_suspend(struct fb_info_aty128 * info,int suspend)2845 aty128_set_suspend(struct fb_info_aty128 *info, int suspend)
2846 {
2847 u32 pmgt;
2848 u16 pwr_command;
2849
2850 if (!info->pm_reg)
2851 return;
2852
2853 /* Set the chip into the appropriate suspend mode (we use D2,
2854 * D3 would require a complete re-initialisation of the chip,
2855 * including PCI config registers, clocks, AGP configuration, ...)
2856 */
2857 if (suspend) {
2858 /* Make sure CRTC2 is reset. Remove that the day we decide to
2859 * actually use CRTC2 and replace it with real code for disabling
2860 * the CRTC2 output during sleep
2861 */
2862 aty_st_le32(CRTC2_GEN_CNTL, aty_ld_le32(CRTC2_GEN_CNTL) &
2863 ~(CRTC2_EN));
2864
2865 /* Set the power management mode to be PCI based */
2866 pmgt = aty_ld_pll(POWER_MANAGEMENT);
2867 #if 0
2868 pmgt &= ~PWR_MGT_MODE_MASK;
2869 pmgt |= PWR_MGT_MODE_PCI | PWR_MGT_ON | PWR_MGT_TRISTATE_MEM_EN | PWR_MGT_AUTO_PWR_UP_EN;
2870 #else /* Use this magic value for now */
2871 pmgt = 0x0c005407;
2872 #endif
2873 aty_st_pll(POWER_MANAGEMENT, pmgt);
2874 (void)aty_ld_pll(POWER_MANAGEMENT);
2875 aty_st_le32(BUS_CNTL1, 0x00000010);
2876 aty_st_le32(MEM_POWER_MISC, 0x0c830000);
2877 mdelay(100);
2878 pci_read_config_word(info->pdev, info->pm_reg+PCI_PM_CTRL, &pwr_command);
2879 /* Switch PCI power management to D2 */
2880 pci_write_config_word(info->pdev, info->pm_reg+PCI_PM_CTRL,
2881 (pwr_command & ~PCI_PM_CTRL_STATE_MASK) | 2);
2882 pci_read_config_word(info->pdev, info->pm_reg+PCI_PM_CTRL, &pwr_command);
2883 } else {
2884 /* Switch back PCI power management to D0 */
2885 mdelay(100);
2886 pci_write_config_word(info->pdev, info->pm_reg+PCI_PM_CTRL, 0);
2887 mdelay(100);
2888 pci_read_config_word(info->pdev, info->pm_reg+PCI_PM_CTRL, &pwr_command);
2889 mdelay(100);
2890 }
2891 }
2892
2893 extern struct display_switch fbcon_dummy;
2894
2895 /*
2896 * Save the contents of the frame buffer when we go to sleep,
2897 * and restore it when we wake up again.
2898 */
2899 int
aty128_sleep_notify(struct pmu_sleep_notifier * self,int when)2900 aty128_sleep_notify(struct pmu_sleep_notifier *self, int when)
2901 {
2902 struct fb_info_aty128 *info;
2903 int result;
2904
2905 result = PBOOK_SLEEP_OK;
2906
2907 for (info = board_list; info != NULL; info = info->next) {
2908 struct fb_fix_screeninfo fix;
2909 int nb;
2910
2911 aty128fb_get_fix(&fix, fg_console, (struct fb_info *)info);
2912 nb = fb_display[fg_console].var.yres * fix.line_length;
2913
2914 switch (when) {
2915 case PBOOK_SLEEP_REQUEST:
2916 info->save_framebuffer = vmalloc(nb);
2917 if (info->save_framebuffer == NULL)
2918 return PBOOK_SLEEP_REFUSE;
2919 break;
2920 case PBOOK_SLEEP_REJECT:
2921 if (info->save_framebuffer) {
2922 vfree(info->save_framebuffer);
2923 info->save_framebuffer = 0;
2924 }
2925 break;
2926 case PBOOK_SLEEP_NOW:
2927 if (info->currcon >= 0)
2928 fb_display[info->currcon].dispsw = &fbcon_dummy;
2929
2930 wait_for_idle(info);
2931 aty128_reset_engine(info);
2932 wait_for_idle(info);
2933
2934 /* Backup fb content */
2935 if (info->save_framebuffer)
2936 memcpy_fromio(info->save_framebuffer,
2937 (void *)info->frame_buffer, nb);
2938
2939 /* Blank display and LCD */
2940 aty128fbcon_blank(VESA_POWERDOWN+1, (struct fb_info *)info);
2941
2942 /* Sleep the chip */
2943 aty128_set_suspend(info, 1);
2944
2945 break;
2946 case PBOOK_WAKE:
2947 /* Wake the chip */
2948 aty128_set_suspend(info, 0);
2949
2950 aty128_reset_engine(info);
2951 wait_for_idle(info);
2952
2953 /* Restore fb content */
2954 if (info->save_framebuffer) {
2955 memcpy_toio((void *)info->frame_buffer,
2956 info->save_framebuffer, nb);
2957 vfree(info->save_framebuffer);
2958 info->save_framebuffer = 0;
2959 }
2960
2961 if (info->currcon >= 0) {
2962 aty128_set_dispsw(
2963 &fb_display[info->currcon],
2964 info,
2965 info->current_par.crtc.bpp,
2966 info->current_par.accel_flags & FB_ACCELF_TEXT);
2967 }
2968 aty128fbcon_blank(0, (struct fb_info *)info);
2969 break;
2970 }
2971 }
2972 return result;
2973 }
2974 #endif /* CONFIG_PMAC_PBOOK */
2975
2976 #ifdef MODULE
2977 MODULE_AUTHOR("(c)1999-2000 Brad Douglas <brad@neruo.com>");
2978 MODULE_DESCRIPTION("FBDev driver for ATI Rage128 / Pro cards");
2979 MODULE_LICENSE("GPL");
2980 MODULE_PARM(noaccel, "i");
2981 MODULE_PARM_DESC(noaccel, "Disable hardware acceleration (0 or 1=disabled) (default=0)");
2982 MODULE_PARM(font, "s");
2983 MODULE_PARM_DESC(font, "Specify one of the compiled-in fonts (default=none)");
2984 MODULE_PARM(mode, "s");
2985 MODULE_PARM_DESC(mode, "Specify resolution as \"<xres>x<yres>[-<bpp>][@<refresh>]\" ");
2986 #ifdef CONFIG_MTRR
2987 MODULE_PARM(nomtrr, "i");
2988 MODULE_PARM_DESC(nomtrr, "Disable MTRR support (0 or 1=disabled) (default=0)");
2989 #endif
2990
2991 int __init
init_module(void)2992 init_module(void)
2993 {
2994 if (noaccel) {
2995 noaccel = 1;
2996 printk(KERN_INFO "aty128fb: Parameter NOACCEL set\n");
2997 }
2998 if (font) {
2999 strncpy(fontname, font, sizeof(fontname)-1);
3000 printk(KERN_INFO "aty128fb: Parameter FONT set to %s\n", font);
3001 }
3002 if (mode) {
3003 mode_option = mode;
3004 printk(KERN_INFO "aty128fb: Parameter MODE set to %s\n", mode);
3005 }
3006 #ifdef CONFIG_MTRR
3007 if (nomtrr) {
3008 mtrr = 0;
3009 printk(KERN_INFO "aty128fb: Parameter NOMTRR set\n");
3010 }
3011 #endif
3012
3013 aty128fb_init();
3014 return 0;
3015 }
3016
3017 void __exit
cleanup_module(void)3018 cleanup_module(void)
3019 {
3020 struct fb_info_aty128 *info = board_list;
3021
3022 while (board_list) {
3023 info = board_list;
3024 board_list = board_list->next;
3025
3026 unregister_framebuffer(&info->fb_info);
3027 #ifdef CONFIG_MTRR
3028 if (info->mtrr.vram_valid)
3029 mtrr_del(info->mtrr.vram, info->frame_buffer_phys,
3030 info->vram_size);
3031 #endif /* CONFIG_MTRR */
3032 iounmap(info->regbase);
3033 iounmap(info->frame_buffer);
3034
3035 release_mem_region(pci_resource_start(info->pdev, 0),
3036 pci_resource_len(info->pdev, 0));
3037 release_mem_region(pci_resource_start(info->pdev, 1),
3038 pci_resource_len(info->pdev, 1));
3039 release_mem_region(pci_resource_start(info->pdev, 2),
3040 pci_resource_len(info->pdev, 2));
3041
3042 kfree(info);
3043 }
3044 }
3045 #endif /* MODULE */
3046