1
2 /*
3 * ATI Frame Buffer Device Driver Core Definitions
4 */
5
6 #include <linux/config.h>
7 #include <linux/sched.h>
8 #include <linux/compiler.h>
9
10 /*
11 * Elements of the hardware specific atyfb_par structure
12 */
13
14 struct crtc {
15 u32 vxres;
16 u32 vyres;
17 u32 xoffset;
18 u32 yoffset;
19 u32 h_tot_disp;
20 u32 h_sync_strt_wid;
21 u32 v_tot_disp;
22 u32 v_sync_strt_wid;
23 u32 off_pitch;
24 u32 gen_cntl;
25 u32 dp_pix_width; /* acceleration */
26 u32 dp_chain_mask; /* acceleration */
27 #ifdef CONFIG_FB_ATY_GENERIC_LCD
28 u32 monitors_enabled; /* LCD monitor support */
29 u16 h_stretching; /* LCD monitor support */
30 u16 v_stretching; /* LCD monitor support */
31 #endif
32 u8 bpp;
33 u8 h_blank_start;
34 u8 h_blank_end;
35 u16 v_blank_start;
36 u8 v_blank_end;
37 u8 genmo;
38 };
39
40 struct pll_514 {
41 u8 m;
42 u8 n;
43 };
44
45 struct pll_18818
46 {
47 u32 program_bits;
48 u32 locationAddr;
49 u32 period_in_ps;
50 u32 post_divider;
51 };
52
53 struct pll_ct {
54 // u8 pll_ref_div;
55 // u8 pll_gen_cntl;
56 // u8 mclk_fb_div;
57 u8 pll_vclk_cntl;
58 u8 vclk_post_div;
59 u8 vclk_fb_div;
60 // u8 alt_post_div;
61 // u8 pll_ext_cntl;
62 u32 dsp_config; /* Mach64 GTB DSP */
63 u32 dsp_on_off; /* Mach64 GTB DSP */
64 // u8 mclk_post_div_real;
65 u8 vclk_post_div_real;
66 };
67
68 union aty_pll {
69 struct pll_ct ct;
70 struct pll_514 ibm514;
71 struct pll_18818 ics2595;
72 };
73
74
75 /*
76 * The hardware parameters for each card
77 */
78
79 struct atyfb_par {
80 struct crtc crtc;
81 union aty_pll pll;
82 u32 accel_flags;
83 };
84
85 struct aty_cursor {
86 int enable;
87 int on;
88 int vbl_cnt;
89 int blink_rate;
90 u32 offset;
91 struct {
92 u16 x, y;
93 } pos, hot, size;
94 u32 color[2];
95 u8 bits[8][64];
96 u8 mask[8][64];
97 u8 *ram;
98 struct timer_list *timer;
99 };
100
101 struct fb_info_aty {
102 struct fb_info fb_info;
103 struct fb_info_aty *next;
104 u32* ati_regaddr[256];
105 unsigned long ati_regbase_phys;
106 unsigned long ati_regbase;
107 unsigned long frame_buffer_phys;
108 unsigned long frame_buffer;
109 unsigned long clk_wr_offset;
110 #ifdef CONFIG_FB_ATY_CT
111 u8 pll_ref_div;
112 u8 xclk_post_div_real;
113 u16 mclk_fb_div;
114 u8 fifo_size;
115 u8 dsp_loop_latency;
116 // u8 page_size;
117 u8 xclkpagefaultdelay,xclkmaxrasdelay;
118 #endif
119 #ifdef CONFIG_FB_ATY_GENERIC_LCD
120 unsigned long bios_base_phys;
121 unsigned long bios_base;
122 unsigned long lcd_table;
123 u16 lcd_width;
124 u16 lcd_height;
125 u32 lcd_pixclock;
126 u16 lcd_htotal;
127 u16 lcd_hdisp;
128 u16 lcd_hsync_start;
129 u16 lcd_hsync_delay;
130 u16 lcd_hsync_width;
131 u16 lcd_vtotal;
132 u16 lcd_vdisp;
133 u16 lcd_vsync_start;
134 u16 lcd_vsync_width;
135 u16 lcd_right;
136 u16 lcd_lower;
137 u16 lcd_hblank_width;
138 u16 lcd_vblank_width;
139 #endif
140 struct pci_mmap_map *mmap_map;
141 struct aty_cursor *cursor;
142 struct aty_cmap_regs *aty_cmap_regs;
143 struct { u8 red, green, blue, pad; } palette[256];
144 struct atyfb_par default_par;
145 struct atyfb_par current_par;
146 u32 features;
147 u32 total_vram;
148 u32 ref_clk_per;
149 u32 pll_per;
150 u32 mclk_per;
151 u32 xclk_per;
152 u8 bus_type;
153 u8 ram_type;
154 u8 mem_refresh_rate;
155 const struct aty_dac_ops *dac_ops;
156 const struct aty_pll_ops *pll_ops;
157 struct display disp;
158 struct display_switch dispsw;
159 union {
160 #ifdef FBCON_HAS_CFB16
161 u16 cfb16[16];
162 #endif
163 #ifdef FBCON_HAS_CFB24
164 u32 cfb24[16];
165 #endif
166 #ifdef FBCON_HAS_CFB32
167 u32 cfb32[16];
168 #endif
169 } fbcon_cmap;
170 u8 blitter_may_be_busy;
171 u8 font_loaded;
172 #ifdef __sparc__
173 u8 mmaped;
174 int open;
175 int vtconsole;
176 int consolecnt;
177 #endif
178 #ifdef CONFIG_PMAC_PBOOK
179 unsigned char *save_framebuffer;
180 unsigned long save_pll[64];
181 #endif
182 };
183
184
185 /*
186 * ATI Mach64 features
187 */
188
189 #define M64_HAS(feature) ((info)->features & (M64F_##feature))
190
191 #define M64F_RESET_3D 0x00000001
192 #define M64F_MAGIC_FIFO 0x00000002
193 #define M64F_GTB_DSP 0x00000004
194 #define M64F_FIFO_24 0x00000008
195 #define M64F_SDRAM_MAGIC_PLL 0x00000010
196 #define M64F_MAGIC_POSTDIV 0x00000020
197 #define M64F_INTEGRATED 0x00000040
198 #define M64F_CT_BUS 0x00000080
199 #define M64F_VT_BUS 0x00000100
200 #define M64F_MOBIL_BUS 0x00000200
201 #define M64F_GX 0x00000400
202 #define M64F_CT 0x00000800
203 #define M64F_VT 0x00001000
204 #define M64F_GT 0x00002000
205 #define M64F_MAGIC_VRAM_SIZE 0x00004000
206 #define M64F_G3_PB_1_1 0x00008000
207 #define M64F_G3_PB_1024x768 0x00010000
208 #define M64F_EXTRA_BRIGHT 0x00020000
209 #define M64F_LT_SLEEP 0x00040000
210 #define M64F_XL_DLL 0x00080000
211
212 #ifdef __i386__
213 # define stdcall __attribute__ ((stdcall))
214 #else
215 # define stdcall
216 #endif
217 #define packed __attribute__ ((packed))
218
219 /*
220 * Register access
221 */
222
aty_ld_le32(int regindex,const struct fb_info_aty * info)223 static inline u32 aty_ld_le32(int regindex,
224 const struct fb_info_aty *info)
225 {
226 if (regindex >= 0x400) {
227 regindex -= 0x800;
228 #if defined(__mc68000__)
229 return le32_to_cpu(*((volatile u32 *)(info->ati_regbase+regindex)));
230 #else
231 return readl (info->ati_regbase + regindex);
232 #endif
233 } else {
234 #if defined(__mc68000__)
235 return le32_to_cpu(*((volatile u32 *)(info->ati_regaddr[regindex/4])));
236 #else
237 return readl (info->ati_regaddr[regindex/4]);
238 #endif
239 };
240 }
241
aty_st_le32_sr(int regindex,u32 val,const struct fb_info_aty * info)242 static inline void aty_st_le32_sr(int regindex, u32 val,
243 const struct fb_info_aty *info)
244 {
245 #if defined(__mc68000__)
246 *((volatile u32 *)(info->ati_regaddr[regindex/4])) = cpu_to_le32(val);
247 #else
248 writel (val,info->ati_regaddr[regindex/4]);
249 #endif
250 }
251
aty_st_le32(int regindex,u32 val,const struct fb_info_aty * info)252 static inline void aty_st_le32(int regindex, u32 val,
253 const struct fb_info_aty *info)
254 {
255 if (regindex >= 0x400) {
256 regindex -= 0x800;
257 #if defined(__mc68000__)
258 *((volatile u32 *)(info->ati_regbase+regindex)) = cpu_to_le32(val);
259 #else
260 writel (val,info->ati_regbase + regindex);
261 #endif
262 } else {
263 #if defined(__mc68000__)
264 *((volatile u32 *)(info->ati_regaddr[regindex/4])) = cpu_to_le32(val);
265 #else
266 writel (val,info->ati_regaddr[regindex/4]);
267 #endif
268 };
269 }
270
aty_ld_8(int regindex,const struct fb_info_aty * info)271 static inline u8 aty_ld_8(int regindex,
272 const struct fb_info_aty *info)
273 {
274 if (regindex >= 0x400)
275 regindex -= 0x800;
276 return readb (info->ati_regbase + regindex);
277 }
278
aty_st_8(int regindex,u8 val,const struct fb_info_aty * info)279 static inline void aty_st_8(int regindex, u8 val,
280 const struct fb_info_aty *info)
281 {
282 if (regindex >= 0x400)
283 regindex -= 0x800;
284 writeb (val,info->ati_regbase + regindex);
285 }
286
287 /*
288 * Mach64 CT PLL operations
289 */
290
291 extern u8 aty_ld_pll(int offset, const struct fb_info_aty *info) stdcall;
292
293 /*
294 * DAC operations
295 */
296
297 struct aty_dac_ops {
298 int (*set_dac)(const struct fb_info_aty *info, const union aty_pll *pll,
299 u32 bpp, u32 accel);
300 };
301
302 extern const struct aty_dac_ops aty_dac_ibm514; /* IBM RGB514 */
303 extern const struct aty_dac_ops aty_dac_ati68860b; /* ATI 68860-B */
304 extern const struct aty_dac_ops aty_dac_att21c498; /* AT&T 21C498 */
305 extern const struct aty_dac_ops aty_dac_unsupported; /* unsupported */
306 extern const struct aty_dac_ops aty_dac_ct; /* Integrated */
307
308
309 /*
310 * Clock operations
311 */
312
313 struct aty_pll_ops {
314 int (*var_to_pll)(const struct fb_info_aty *info, u32 vclk_per, u8 bpp,
315 u32 xres, union aty_pll *pll);
316 u32 (*pll_to_var)(const struct fb_info_aty *info,
317 const union aty_pll *pll);
318 void (*set_pll)(const struct fb_info_aty *info, const union aty_pll *pll);
319 void (*init_pll)(struct fb_info_aty *info);
320 };
321
322 extern const struct aty_pll_ops aty_pll_ati18818_1; /* ATI 18818 */
323 extern const struct aty_pll_ops aty_pll_stg1703; /* STG 1703 */
324 extern const struct aty_pll_ops aty_pll_ch8398; /* Chrontel 8398 */
325 extern const struct aty_pll_ops aty_pll_att20c408; /* AT&T 20C408 */
326 extern const struct aty_pll_ops aty_pll_ibm514; /* IBM RGB514 */
327 extern const struct aty_pll_ops aty_pll_unsupported; /* unsupported */
328 extern const struct aty_pll_ops aty_pll_ct; /* Integrated */
329
330
331 extern void aty_set_pll_ct(const struct fb_info_aty *info,
332 const union aty_pll *pll);
333 //extern void aty_calc_pll_ct(const struct fb_info_aty *info,
334 // struct pll_ct *pll);
335
336
337 /*
338 * Hardware cursor support
339 */
340
341 extern struct aty_cursor *aty_init_cursor(struct fb_info_aty *fb);
342 extern void atyfb_cursor(struct display *p, int mode, int x, int y);
343 extern void aty_set_cursor_color(struct fb_info_aty *fb);
344 extern void aty_set_cursor_shape(struct fb_info_aty *fb);
345 extern int atyfb_set_font(struct display *d, int width, int height);
346
347
348 /*
349 * Hardware acceleration
350 */
351
wait_for_fifo(u16 entries,const struct fb_info_aty * info)352 static inline void wait_for_fifo(u16 entries, const struct fb_info_aty *info)
353 {
354 while (__builtin_expect((aty_ld_le32(FIFO_STAT, info) & 0xffff), 0) >
355 ((u32)(0x8000 >> entries)));
356 }
357
wait_for_idle(struct fb_info_aty * info)358 static inline void wait_for_idle(struct fb_info_aty *info)
359 {
360 wait_for_fifo(16, info);
361 while ((aty_ld_le32(GUI_STAT, info) & 1)!= 0);
362 info->blitter_may_be_busy = 0;
363 }
364
365 extern void aty_reset_engine(const struct fb_info_aty *info);
366 extern void aty_init_engine(const struct atyfb_par *par,
367 struct fb_info_aty *info);
368 extern void aty_rectfill(int dstx, int dsty, u_int width, u_int height,
369 u_int color, struct fb_info_aty *info);
370
371
372 /*
373 * Text console acceleration
374 */
375
376 extern const struct display_switch fbcon_aty0;
377 extern const struct display_switch fbcon_aty8;
378 extern const struct display_switch fbcon_aty16;
379 extern const struct display_switch fbcon_aty24;
380 extern const struct display_switch fbcon_aty32;
381
382