1 /*
2  *  linux/drivers/video/acornfb.h
3  *
4  *  Copyright (C) 1998,1999 Russell King
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License version 2 as
8  * published by the Free Software Foundation.
9  *
10  *  Frame buffer code for Acorn platforms
11  */
12 #if defined(HAS_VIDC20)
13 #include <asm/hardware/iomd.h>
14 #define VIDC_PALETTE_SIZE	256
15 #define VIDC_NAME		"VIDC20"
16 #elif defined(HAS_VIDC)
17 #include <asm/hardware/memc.h>
18 #define VIDC_PALETTE_SIZE	16
19 #define VIDC_NAME		"VIDC"
20 #endif
21 
22 #define EXTEND8(x) ((x)|(x)<<8)
23 #define EXTEND4(x) ((x)|(x)<<4|(x)<<8|(x)<<12)
24 
25 struct vidc20_palette {
26 	u_int red:8;
27 	u_int green:8;
28 	u_int blue:8;
29 	u_int ext:4;
30 	u_int unused:4;
31 };
32 
33 struct vidc_palette {
34 	u_int red:4;
35 	u_int green:4;
36 	u_int blue:4;
37 	u_int trans:1;
38 	u_int sbz1:13;
39 	u_int reg:4;
40 	u_int sbz2:2;
41 };
42 
43 union palette {
44 	struct vidc20_palette	vidc20;
45 	struct vidc_palette	vidc;
46 	u_int	p;
47 };
48 
49 struct acornfb_par {
50 	unsigned long	screen_base;
51 	unsigned long	screen_base_p;
52 	unsigned long	screen_end;
53 	unsigned long	screen_size;
54 	unsigned int	dram_size;
55 	unsigned int	vram_half_sam;
56 	unsigned int	palette_size;
57 	  signed int	montype;
58 	  signed int	currcon;
59 	unsigned int	using_vram	: 1;
60 	unsigned int	dpms		: 1;
61 
62 	union palette palette[VIDC_PALETTE_SIZE];
63 
64 	union {
65 		unsigned short cfb16[16];
66 		unsigned long  cfb32[16];
67 	} cmap;
68 };
69 
70 struct vidc_timing {
71 	u_int	h_cycle;
72 	u_int	h_sync_width;
73 	u_int	h_border_start;
74 	u_int	h_display_start;
75 	u_int	h_display_end;
76 	u_int	h_border_end;
77 	u_int	h_interlace;
78 
79 	u_int	v_cycle;
80 	u_int	v_sync_width;
81 	u_int	v_border_start;
82 	u_int	v_display_start;
83 	u_int	v_display_end;
84 	u_int	v_border_end;
85 
86 	u_int	control;
87 
88 	/* VIDC20 only */
89 	u_int	pll_ctl;
90 };
91 
92 struct modey_params {
93 	u_int	y_res;
94 	u_int	u_margin;
95 	u_int	b_margin;
96 	u_int	vsync_len;
97 	u_int	vf;
98 };
99 
100 struct modex_params {
101 	u_int	x_res;
102 	u_int	l_margin;
103 	u_int	r_margin;
104 	u_int	hsync_len;
105 	u_int	clock;
106 	u_int	hf;
107 	const struct modey_params *modey;
108 };
109 
110 #ifdef HAS_VIDC
111 
112 #define VID_CTL_VS_NVSYNC	(1 << 3)
113 #define VID_CTL_HS_NHSYNC	(1 << 2)
114 #define VID_CTL_24MHz		(0)
115 #define VID_CTL_25MHz		(1)
116 #define VID_CTL_36MHz		(2)
117 
118 #define VIDC_CTRL_CSYNC		(1 << 7)
119 #define VIDC_CTRL_INTERLACE	(1 << 6)
120 #define VIDC_CTRL_FIFO_0_4	(0 << 4)
121 #define VIDC_CTRL_FIFO_1_5	(1 << 4)
122 #define VIDC_CTRL_FIFO_2_6	(2 << 4)
123 #define VIDC_CTRL_FIFO_3_7	(3 << 4)
124 #define VIDC_CTRL_1BPP		(0 << 2)
125 #define VIDC_CTRL_2BPP		(1 << 2)
126 #define VIDC_CTRL_4BPP		(2 << 2)
127 #define VIDC_CTRL_8BPP		(3 << 2)
128 #define VIDC_CTRL_DIV3		(0 << 0)
129 #define VIDC_CTRL_DIV2		(1 << 0)
130 #define VIDC_CTRL_DIV1_5	(2 << 0)
131 #define VIDC_CTRL_DIV1		(3 << 0)
132 
133 #endif
134 
135 #ifdef HAS_VIDC20
136 /*
137  * VIDC20 registers
138  */
139 #define VIDC20_CTRL		0xe0000000
140 #define VIDC20_CTRL_PIX_VCLK	(0 << 0)
141 #define VIDC20_CTRL_PIX_HCLK	(1 << 0)
142 #define VIDC20_CTRL_PIX_RCLK	(2 << 0)
143 #define VIDC20_CTRL_PIX_CK	(0 << 2)
144 #define VIDC20_CTRL_PIX_CK2	(1 << 2)
145 #define VIDC20_CTRL_PIX_CK3	(2 << 2)
146 #define VIDC20_CTRL_PIX_CK4	(3 << 2)
147 #define VIDC20_CTRL_PIX_CK5	(4 << 2)
148 #define VIDC20_CTRL_PIX_CK6	(5 << 2)
149 #define VIDC20_CTRL_PIX_CK7	(6 << 2)
150 #define VIDC20_CTRL_PIX_CK8	(7 << 2)
151 #define VIDC20_CTRL_1BPP	(0 << 5)
152 #define VIDC20_CTRL_2BPP	(1 << 5)
153 #define VIDC20_CTRL_4BPP	(2 << 5)
154 #define VIDC20_CTRL_8BPP	(3 << 5)
155 #define VIDC20_CTRL_16BPP	(4 << 5)
156 #define VIDC20_CTRL_32BPP	(6 << 5)
157 #define VIDC20_CTRL_FIFO_NS	(0 << 8)
158 #define VIDC20_CTRL_FIFO_4	(1 << 8)
159 #define VIDC20_CTRL_FIFO_8	(2 << 8)
160 #define VIDC20_CTRL_FIFO_12	(3 << 8)
161 #define VIDC20_CTRL_FIFO_16	(4 << 8)
162 #define VIDC20_CTRL_FIFO_20	(5 << 8)
163 #define VIDC20_CTRL_FIFO_24	(6 << 8)
164 #define VIDC20_CTRL_FIFO_28	(7 << 8)
165 #define VIDC20_CTRL_INT		(1 << 12)
166 #define VIDC20_CTRL_DUP		(1 << 13)
167 #define VIDC20_CTRL_PDOWN	(1 << 14)
168 
169 #define VIDC20_ECTL		0xc0000000
170 #define VIDC20_ECTL_REG(x)	((x) & 0xf3)
171 #define VIDC20_ECTL_ECK		(1 << 2)
172 #define VIDC20_ECTL_REDPED	(1 << 8)
173 #define VIDC20_ECTL_GREENPED	(1 << 9)
174 #define VIDC20_ECTL_BLUEPED	(1 << 10)
175 #define VIDC20_ECTL_DAC		(1 << 12)
176 #define VIDC20_ECTL_LCDGS	(1 << 13)
177 #define VIDC20_ECTL_HRM		(1 << 14)
178 
179 #define VIDC20_ECTL_HS_MASK	(3 << 16)
180 #define VIDC20_ECTL_HS_HSYNC	(0 << 16)
181 #define VIDC20_ECTL_HS_NHSYNC	(1 << 16)
182 #define VIDC20_ECTL_HS_CSYNC	(2 << 16)
183 #define VIDC20_ECTL_HS_NCSYNC	(3 << 16)
184 
185 #define VIDC20_ECTL_VS_MASK	(3 << 18)
186 #define VIDC20_ECTL_VS_VSYNC	(0 << 18)
187 #define VIDC20_ECTL_VS_NVSYNC	(1 << 18)
188 #define VIDC20_ECTL_VS_CSYNC	(2 << 18)
189 #define VIDC20_ECTL_VS_NCSYNC	(3 << 18)
190 
191 #define VIDC20_DCTL		0xf0000000
192 /* 0-9 = number of words in scanline */
193 #define VIDC20_DCTL_SNA		(1 << 12)
194 #define VIDC20_DCTL_HDIS	(1 << 13)
195 #define VIDC20_DCTL_BUS_NS	(0 << 16)
196 #define VIDC20_DCTL_BUS_D31_0	(1 << 16)
197 #define VIDC20_DCTL_BUS_D63_32	(2 << 16)
198 #define VIDC20_DCTL_BUS_D63_0	(3 << 16)
199 #define VIDC20_DCTL_VRAM_DIS	(0 << 18)
200 #define VIDC20_DCTL_VRAM_PXCLK	(1 << 18)
201 #define VIDC20_DCTL_VRAM_PXCLK2	(2 << 18)
202 #define VIDC20_DCTL_VRAM_PXCLK4	(3 << 18)
203 
204 #endif
205