1 /* 2 * SL811HS HCD (Host Controller Driver) for USB. 3 * 4 * COPYRIGHT (C) by CYPRESS SEMICONDUCTOR INC 5 * 6 * 7 */ 8 9 #define GET_FRAME_NUMBER(hci) READ_REG32 (hci, HcFmNumber) 10 11 /* 12 * Maximum number of root hub ports 13 */ 14 #define MAX_ROOT_PORTS 15 /* maximum OHCI root hub ports */ 15 16 /* control and status registers */ 17 #define HcRevision 0x00 18 #define HcControl 0x01 19 #define HcCommandStatus 0x02 20 #define HcInterruptStatus 0x03 21 #define HcInterruptEnable 0x04 22 #define HcInterruptDisable 0x05 23 #define HcFmInterval 0x0D 24 #define HcFmRemaining 0x0E 25 #define HcFmNumber 0x0F 26 #define HcLSThreshold 0x11 27 #define HcRhDescriptorA 0x12 28 #define HcRhDescriptorB 0x13 29 #define HcRhStatus 0x14 30 #define HcRhPortStatus 0x15 31 32 #define HcHardwareConfiguration 0x20 33 #define HcDMAConfiguration 0x21 34 #define HcTransferCounter 0x22 35 #define HcuPInterrupt 0x24 36 #define HcuPInterruptEnable 0x25 37 #define HcChipID 0x27 38 #define HcScratch 0x28 39 #define HcSoftwareReset 0x29 40 #define HcITLBufferLength 0x2A 41 #define HcATLBufferLength 0x2B 42 #define HcBufferStatus 0x2C 43 #define HcReadBackITL0Length 0x2D 44 #define HcReadBackITL1Length 0x2E 45 #define HcITLBufferPort 0x40 46 #define HcATLBufferPort 0x41 47 48 /* OHCI CONTROL AND STATUS REGISTER MASKS */ 49 50 /* 51 * HcControl (control) register masks 52 */ 53 #define OHCI_CTRL_HCFS (3 << 6) /* BUS state mask */ 54 #define OHCI_CTRL_RWC (1 << 9) /* remote wakeup connected */ 55 #define OHCI_CTRL_RWE (1 << 10) /* remote wakeup enable */ 56 57 /* pre-shifted values for HCFS */ 58 #define OHCI_USB_RESET (0 << 6) 59 #define OHCI_USB_RESUME (1 << 6) 60 #define OHCI_USB_OPER (2 << 6) 61 #define OHCI_USB_SUSPEND (3 << 6) 62 63 /* 64 * HcCommandStatus (cmdstatus) register masks 65 */ 66 #define OHCI_HCR (1 << 0) /* host controller reset */ 67 #define OHCI_SO (3 << 16) /* scheduling overrun count */ 68 69 /* 70 * masks used with interrupt registers: 71 * HcInterruptStatus (intrstatus) 72 * HcInterruptEnable (intrenable) 73 * HcInterruptDisable (intrdisable) 74 */ 75 #define OHCI_INTR_SO (1 << 0) /* scheduling overrun */ 76 77 #define OHCI_INTR_SF (1 << 2) /* start frame */ 78 #define OHCI_INTR_RD (1 << 3) /* resume detect */ 79 #define OHCI_INTR_UE (1 << 4) /* unrecoverable error */ 80 #define OHCI_INTR_FNO (1 << 5) /* frame number overflow */ 81 #define OHCI_INTR_RHSC (1 << 6) /* root hub status change */ 82 #define OHCI_INTR_ATD (1 << 7) /* scheduling overrun */ 83 84 #define OHCI_INTR_MIE (1 << 31) /* master interrupt enable */ 85 86 /* 87 * HcHardwareConfiguration 88 */ 89 #define InterruptPinEnable (1 << 0) 90 #define InterruptPinTrigger (1 << 1) 91 #define InterruptOutputPolarity (1 << 2) 92 #define DataBusWidth16 (1 << 3) 93 #define DREQOutputPolarity (1 << 5) 94 #define DACKInputPolarity (1 << 6) 95 #define EOTInputPolarity (1 << 7) 96 #define DACKMode (1 << 8) 97 #define AnalogOCEnable (1 << 10) 98 #define SuspendClkNotStop (1 << 11) 99 #define DownstreamPort15KRSel (1 << 12) 100 101 /* 102 * HcDMAConfiguration 103 */ 104 #define DMAReadWriteSelect (1 << 0) 105 #define ITL_ATL_DataSelect (1 << 1) 106 #define DMACounterSelect (1 << 2) 107 #define DMAEnable (1 << 4) 108 #define BurstLen_1 0 109 #define BurstLen_4 (1 << 5) 110 #define BurstLen_8 (2 << 5) 111 112 /* 113 * HcuPInterrupt 114 */ 115 #define SOFITLInt (1 << 0) 116 #define ATLInt (1 << 1) 117 #define AllEOTInterrupt (1 << 2) 118 #define OPR_Reg (1 << 4) 119 #define HCSuspended (1 << 5) 120 #define ClkReady (1 << 6) 121 122 /* 123 * HcBufferStatus 124 */ 125 #define ITL0BufferFull (1 << 0) 126 #define ITL1BufferFull (1 << 1) 127 #define ATLBufferFull (1 << 2) 128 #define ITL0BufferDone (1 << 3) 129 #define ITL1BufferDone (1 << 4) 130 #define ATLBufferDone (1 << 5) 131 132 /* OHCI ROOT HUB REGISTER MASKS */ 133 134 /* roothub.portstatus [i] bits */ 135 #define RH_PS_CCS 0x00000001 /* current connect status */ 136 #define RH_PS_PES 0x00000002 /* port enable status */ 137 #define RH_PS_PSS 0x00000004 /* port suspend status */ 138 #define RH_PS_POCI 0x00000008 /* port over current indicator */ 139 #define RH_PS_PRS 0x00000010 /* port reset status */ 140 #define RH_PS_PPS 0x00000100 /* port power status */ 141 #define RH_PS_LSDA 0x00000200 /* low speed device attached */ 142 #define RH_PS_CSC 0x00010000 /* connect status change */ 143 #define RH_PS_PESC 0x00020000 /* port enable status change */ 144 #define RH_PS_PSSC 0x00040000 /* port suspend status change */ 145 #define RH_PS_OCIC 0x00080000 /* over current indicator change */ 146 #define RH_PS_PRSC 0x00100000 /* port reset status change */ 147 148 /* roothub.status bits */ 149 #define RH_HS_LPS 0x00000001 /* local power status */ 150 #define RH_HS_OCI 0x00000002 /* over current indicator */ 151 #define RH_HS_DRWE 0x00008000 /* device remote wakeup enable */ 152 #define RH_HS_LPSC 0x00010000 /* local power status change */ 153 #define RH_HS_OCIC 0x00020000 /* over current indicator change */ 154 #define RH_HS_CRWE 0x80000000 /* clear remote wakeup enable */ 155 156 /* roothub.b masks */ 157 #define RH_B_DR 0x0000ffff /* device removable flags */ 158 #define RH_B_PPCM 0xffff0000 /* port power control mask */ 159 160 /* roothub.a masks */ 161 #define RH_A_NDP (0xff << 0) /* number of downstream ports */ 162 #define RH_A_PSM (1 << 8) /* power switching mode */ 163 #define RH_A_NPS (1 << 9) /* no power switching */ 164 #define RH_A_DT (1 << 10) /* device type (mbz) */ 165 #define RH_A_OCPM (1 << 11) /* over current protection mode */ 166 #define RH_A_NOCP (1 << 12) /* no over current protection */ 167 #define RH_A_POTPGT (0xff << 24) /* power on to power good time */ 168 169 #define URB_DEL 1 170 171 #define PORT_STAT_DEFAULT 0x0100 172 #define PORT_CONNECT_STAT 0x1 173 #define PORT_ENABLE_STAT 0x2 174 #define PORT_SUSPEND_STAT 0x4 175 #define PORT_OVER_CURRENT_STAT 0x8 176 #define PORT_RESET_STAT 0x10 177 #define PORT_POWER_STAT 0x100 178 #define PORT_LOW_SPEED_DEV_ATTACH_STAT 0x200 179 180 #define PORT_CHANGE_DEFAULT 0x0 181 #define PORT_CONNECT_CHANGE 0x1 182 #define PORT_ENABLE_CHANGE 0x2 183 #define PORT_SUSPEND_CHANGE 0x4 184 #define PORT_OVER_CURRENT_CHANGE 0x8 185 #define PORT_RESET_CHANGE 0x10 186 187 /* Port Status Request info */ 188 189 typedef struct portstat { 190 __u16 portChange; 191 __u16 portStatus; 192 } portstat_t; 193 194 typedef struct hcipriv { 195 int irq; 196 int disabled; /* e.g. got a UE, we're hung */ 197 atomic_t resume_count; /* defending against multiple resumes */ 198 struct ohci_regs *regs; /* OHCI controller's memory */ 199 int hcport; /* I/O base address */ 200 int hcport2; /* I/O data reg addr */ 201 202 struct portstat *RHportStatus; /* root hub port status */ 203 204 int intrstatus; 205 __u32 hc_control; /* copy of the hc control reg */ 206 207 int frame; 208 209 __u8 *tl; 210 int xferPktLen; 211 int atl_len; 212 int atl_buffer_len; 213 int itl0_len; 214 int itl1_len; 215 int itl_buffer_len; 216 int itl_index; 217 int tl_last; 218 int units_left; 219 220 } hcipriv_t; 221 struct hci; 222 223 #define cClt 0 // Control 224 #define cISO 1 // ISO 225 #define cBULK 2 // BULK 226 #define cInt 3 // Interrupt 227 #define ISO_BIT 0x10 228 229 /*------------------------------------------------------------------------- 230 * EP0 use for configuration and Vendor Specific command interface 231 *------------------------------------------------------------------------*/ 232 #define cMemStart 0x10 233 #define EP0Buf 0x40 /* SL11H/SL811H memory start at 0x40 */ 234 #define EP0Len 0x40 /* Length of config buffer EP0Buf */ 235 #define EP1Buf 0x60 236 #define EP1Len 0x40 237 238 /*------------------------------------------------------------------------- 239 * SL11H/SL811H memory from 80h-ffh use as ping-pong buffer. 240 *------------------------------------------------------------------------*/ 241 #define uBufA 0x80 /* buffer A address for DATA0 */ 242 #define uBufB 0xc0 /* buffer B address for DATA1 */ 243 #define uXferLen 0x40 /* xfer length */ 244 #define sMemSize 0xc0 /* Total SL11 memory size */ 245 #define cMemEnd 256 246 247 /*------------------------------------------------------------------------- 248 * SL811H Register Control memory map 249 * --Note: 250 * --SL11H only has one control register set from 0x00-0x04 251 * --SL811H has two control register set from 0x00-0x04 and 0x08-0x0c 252 *------------------------------------------------------------------------*/ 253 254 #define EP0Control 0x00 255 #define EP0Address 0x01 256 #define EP0XferLen 0x02 257 #define EP0Status 0x03 258 #define EP0Counter 0x04 259 260 #define EP1Control 0x08 261 #define EP1Address 0x09 262 #define EP1XferLen 0x0a 263 #define EP1Status 0x0b 264 #define EP1Counter 0x0c 265 266 #define CtrlReg 0x05 267 #define IntEna 0x06 268 // 0x07 is reserved 269 #define IntStatus 0x0d 270 #define cDATASet 0x0e 271 #define cSOFcnt 0x0f 272 #define IntMask 0x57 /* Reset|DMA|EP0|EP2|EP1 for IntEna */ 273 #define HostMask 0x47 /* Host request command for IntStatus */ 274 #define ReadMask 0xd7 /* Read mask interrupt for IntStatus */ 275 276 /*------------------------------------------------------------------------- 277 * Standard Chapter 9 definition 278 *------------------------------------------------------------------------- 279 */ 280 #define GET_STATUS 0x00 281 #define CLEAR_FEATURE 0x01 282 #define SET_FEATURE 0x03 283 #define SET_ADDRESS 0x05 284 #define GET_DESCRIPTOR 0x06 285 #define SET_DESCRIPTOR 0x07 286 #define GET_CONFIG 0x08 287 #define SET_CONFIG 0x09 288 #define GET_INTERFACE 0x0a 289 #define SET_INTERFACE 0x0b 290 #define SYNCH_FRAME 0x0c 291 292 #define DEVICE 0x01 293 #define CONFIGURATION 0x02 294 #define STRING 0x03 295 #define INTERFACE 0x04 296 #define ENDPOINT 0x05 297 298 /*------------------------------------------------------------------------- 299 * SL11H/SL811H definition 300 *------------------------------------------------------------------------- 301 */ 302 #define DATA0_WR 0x07 // (Arm+Enable+tranmist to Host+DATA0) 303 #define DATA1_WR 0x47 // (Arm+Enable+tranmist to Host on DATA1) 304 #define ZDATA0_WR 0x05 // (Arm+Transaction Ignored+tranmist to Host+DATA0) 305 #define ZDATA1_WR 0x45 // (Arm+Transaction Ignored+tranmist to Host+DATA1) 306 #define DATA0_RD 0x03 // (Arm+Enable+received from Host+DATA0) 307 #define DATA1_RD 0x43 // (Arm+Enable+received from Host+DATA1) 308 309 #define PID_SETUP 0x2d // USB Specification 1.1 Standard Definition 310 #define PID_SOF 0xA5 311 #define PID_IN 0x69 312 #define PID_OUT 0xe1 313 314 #define MAX_RETRY 0xffff 315 #define TIMEOUT 5 /* 2 mseconds */ 316 317 #define SL11H_HOSTCTLREG 0 318 #define SL11H_BUFADDRREG 1 319 #define SL11H_BUFLNTHREG 2 320 #define SL11H_PKTSTATREG 3 /* read */ 321 #define SL11H_PIDEPREG 3 /* write */ 322 #define SL11H_XFERCNTREG 4 /* read */ 323 #define SL11H_DEVADDRREG 4 /* write */ 324 #define SL11H_CTLREG1 5 325 #define SL11H_INTENBLREG 6 326 327 // You should not use these registers 328 #define SL11H_HOSTCTLREG_B 8 329 // #define SL11H_BUFADDRREG_B 9 330 #define SL11H_BUFLNTHREG_B 0x0A 331 // #define SL11H_PKTSTATREG_B 0x0B /* read */ 332 #define SL11H_PIDEPREG_B 0x0B /* write */ 333 // #define SL11H_XFERCNTREG_B 0x0C /* read */ 334 #define SL11H_DEVADDRREG_B 0x0C /* write */ 335 336 #define SL11H_INTSTATREG 0x0D /* write clears bitwise */ 337 #define SL11H_HWREVREG 0x0E /* read */ 338 #define SL11H_SOFLOWREG 0x0E /* write */ 339 #define SL11H_SOFTMRREG 0x0F /* read */ 340 #define SL11H_CTLREG2 0x0F /* write */ 341 #define SL11H_DATA_START 0x10 342 343 /* Host control register bits (addr 0) */ 344 #define SL11H_HCTLMASK_ARM 1 345 #define SL11H_HCTLMASK_ENBLEP 2 346 #define SL11H_HCTLMASK_WRITE 4 347 #define SL11H_HCTLMASK_ISOCH 0x10 348 #define SL11H_HCTLMASK_AFTERSOF 0x20 349 #define SL11H_HCTLMASK_SEQ 0x40 350 #define SL11H_HCTLMASK_PREAMBLE 0x80 351 352 /* Packet status register bits (addr 3) */ 353 #define SL11H_STATMASK_ACK 1 354 #define SL11H_STATMASK_ERROR 2 355 #define SL11H_STATMASK_TMOUT 4 356 #define SL11H_STATMASK_SEQ 8 357 #define SL11H_STATMASK_SETUP 0x10 358 #define SL11H_STATMASK_OVF 0x20 359 #define SL11H_STATMASK_NAK 0x40 360 #define SL11H_STATMASK_STALL 0x80 361 362 /* Control register 1 bits (addr 5) */ 363 #define SL11H_CTL1MASK_DSBLSOF 1 364 #define SL11H_CTL1MASK_NOTXEOF2 4 365 #define SL11H_CTL1MASK_DSTATE 0x18 366 #define SL11H_CTL1MASK_NSPD 0x20 367 #define SL11H_CTL1MASK_SUSPEND 0x40 368 #define SL11H_CTL1MASK_CLK12 0x80 369 370 #define SL11H_CTL1VAL_RESET 8 371 372 /* Interrut enable (addr 6) and interrupt status register bits (addr 0xD) */ 373 #define SL11H_INTMASK_XFERDONE 1 374 #define SL11H_INTMASK_SOFINTR 0x10 375 #define SL11H_INTMASK_INSRMV 0x20 376 #define SL11H_INTMASK_USBRESET 0x40 377 #define SL11H_INTMASK_DSTATE 0x80 /* only in status reg */ 378 379 /* HW rev and SOF lo register bits (addr 0xE) */ 380 #define SL11H_HWRMASK_HWREV 0xF0 381 382 /* SOF counter and control reg 2 (addr 0xF) */ 383 #define SL11H_CTL2MASK_SOFHI 0x3F 384 #define SL11H_CTL2MASK_DSWAP 0x40 385 #define SL11H_CTL2MASK_HOSTMODE 0xae 386 387