1 /*
2 * Copyright (c) 2001-2002 by David Brownell
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License as published by the
6 * Free Software Foundation; either version 2 of the License, or (at your
7 * option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful, but
10 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
11 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software Foundation,
16 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
17 */
18
19 #ifndef __LINUX_EHCI_HCD_H
20 #define __LINUX_EHCI_HCD_H
21
22 /* definitions used for the EHCI driver */
23
24 /* statistics can be kept for for tuning/monitoring */
25 struct ehci_stats {
26 /* irq usage */
27 unsigned long normal;
28 unsigned long error;
29 unsigned long reclaim;
30 unsigned long lost_iaa;
31
32 /* termination of urbs from core */
33 unsigned long complete;
34 unsigned long unlink;
35 };
36
37 /* ehci_hcd->lock guards shared data against other CPUs:
38 * ehci_hcd: async, reclaim, periodic (and shadow), ...
39 * hcd_dev: ep[]
40 * ehci_qh: qh_next, qtd_list
41 * ehci_qtd: qtd_list
42 *
43 * Also, hold this lock when talking to HC registers or
44 * when updating hw_* fields in shared qh/qtd/... structures.
45 */
46
47 #define EHCI_MAX_ROOT_PORTS 15 /* see HCS_N_PORTS */
48
49 struct ehci_hcd { /* one per controller */
50 spinlock_t lock;
51
52 /* async schedule support */
53 struct ehci_qh *async;
54 struct ehci_qh *reclaim;
55 int reclaim_ready : 1;
56
57 /* periodic schedule support */
58 #define DEFAULT_I_TDPS 1024 /* some HCs can do less */
59 unsigned periodic_size;
60 u32 *periodic; /* hw periodic table */
61 dma_addr_t periodic_dma;
62 unsigned i_thresh; /* uframes HC might cache */
63
64 union ehci_shadow *pshadow; /* mirror hw periodic table */
65 int next_uframe; /* scan periodic, start here */
66 unsigned periodic_sched; /* periodic activity count */
67
68 /* per root hub port */
69 unsigned long reset_done [EHCI_MAX_ROOT_PORTS];
70
71 /* glue to PCI and HCD framework */
72 struct usb_hcd hcd;
73 struct ehci_caps *caps;
74 struct ehci_regs *regs;
75 u32 hcs_params; /* cached register copy */
76
77 /* per-HC memory pools (could be per-PCI-bus, but ...) */
78 struct pci_pool *qh_pool; /* qh per active urb */
79 struct pci_pool *qtd_pool; /* one or more per qh */
80 struct pci_pool *itd_pool; /* itd per iso urb */
81 struct pci_pool *sitd_pool; /* sitd per split iso urb */
82
83 struct timer_list watchdog;
84 struct notifier_block reboot_notifier;
85 unsigned long actions;
86 unsigned stamp;
87
88 /* irq statistics */
89 #ifdef EHCI_STATS
90 struct ehci_stats stats;
91 # define COUNT(x) do { (x)++; } while (0)
92 #else
93 # define COUNT(x) do {} while (0)
94 #endif
95 };
96
97 /* unwrap an HCD pointer to get an EHCI_HCD pointer */
98 #define hcd_to_ehci(hcd_ptr) container_of(hcd_ptr, struct ehci_hcd, hcd)
99
100 /* NOTE: urb->transfer_flags expected to not use this bit !!! */
101 #define EHCI_STATE_UNLINK 0x8000 /* urb being unlinked */
102
103 enum ehci_timer_action {
104 TIMER_IO_WATCHDOG,
105 TIMER_IAA_WATCHDOG,
106 TIMER_ASYNC_SHRINK,
107 TIMER_ASYNC_OFF,
108 };
109
110 static inline void
timer_action_done(struct ehci_hcd * ehci,enum ehci_timer_action action)111 timer_action_done (struct ehci_hcd *ehci, enum ehci_timer_action action)
112 {
113 clear_bit (action, &ehci->actions);
114 }
115
116 static inline void
timer_action(struct ehci_hcd * ehci,enum ehci_timer_action action)117 timer_action (struct ehci_hcd *ehci, enum ehci_timer_action action)
118 {
119 if (!test_and_set_bit (action, &ehci->actions)) {
120 unsigned long t;
121
122 switch (action) {
123 case TIMER_IAA_WATCHDOG:
124 t = EHCI_IAA_JIFFIES;
125 break;
126 case TIMER_IO_WATCHDOG:
127 t = EHCI_IO_JIFFIES;
128 break;
129 case TIMER_ASYNC_OFF:
130 t = EHCI_ASYNC_JIFFIES;
131 break;
132 // case TIMER_ASYNC_SHRINK:
133 default:
134 t = EHCI_SHRINK_JIFFIES;
135 break;
136 }
137 t += jiffies;
138 // all timings except IAA watchdog can be overridden.
139 // async queue SHRINK often precedes IAA. while it's ready
140 // to go OFF neither can matter, and afterwards the IO
141 // watchdog stops unless there's still periodic traffic.
142 if (action != TIMER_IAA_WATCHDOG
143 && t > ehci->watchdog.expires
144 && timer_pending (&ehci->watchdog))
145 return;
146 mod_timer (&ehci->watchdog, t);
147 }
148 }
149
150 /*-------------------------------------------------------------------------*/
151
152 /* EHCI register interface, corresponds to EHCI Revision 0.95 specification */
153
154 /* Section 2.2 Host Controller Capability Registers */
155 struct ehci_caps {
156 /* these fields are specified as 8 and 16 bit registers,
157 * but some hosts can't perform 8 or 16 bit PCI accesses.
158 */
159 u32 hc_capbase;
160 #define HC_LENGTH(p) (((p)>>00)&0x00ff) /* bits 7:0 */
161 #define HC_VERSION(p) (((p)>>16)&0xffff) /* bits 31:16 */
162 u32 hcs_params; /* HCSPARAMS - offset 0x4 */
163 #define HCS_DEBUG_PORT(p) (((p)>>20)&0xf) /* bits 23:20, debug port? */
164 #define HCS_INDICATOR(p) ((p)&(1 << 16)) /* true: has port indicators */
165 #define HCS_N_CC(p) (((p)>>12)&0xf) /* bits 15:12, #companion HCs */
166 #define HCS_N_PCC(p) (((p)>>8)&0xf) /* bits 11:8, ports per CC */
167 #define HCS_PORTROUTED(p) ((p)&(1 << 7)) /* true: port routing */
168 #define HCS_PPC(p) ((p)&(1 << 4)) /* true: port power control */
169 #define HCS_N_PORTS(p) (((p)>>0)&0xf) /* bits 3:0, ports on HC */
170
171 u32 hcc_params; /* HCCPARAMS - offset 0x8 */
172 #define HCC_EXT_CAPS(p) (((p)>>8)&0xff) /* for pci extended caps */
173 #define HCC_ISOC_CACHE(p) ((p)&(1 << 7)) /* true: can cache isoc frame */
174 #define HCC_ISOC_THRES(p) (((p)>>4)&0x7) /* bits 6:4, uframes cached */
175 #define HCC_CANPARK(p) ((p)&(1 << 2)) /* true: can park on async qh */
176 #define HCC_PGM_FRAMELISTLEN(p) ((p)&(1 << 1)) /* true: periodic_size changes*/
177 #define HCC_64BIT_ADDR(p) ((p)&(1)) /* true: can use 64-bit addr */
178 u8 portroute [8]; /* nibbles for routing - offset 0xC */
179 } __attribute__ ((packed));
180
181
182 /* Section 2.3 Host Controller Operational Registers */
183 struct ehci_regs {
184
185 /* USBCMD: offset 0x00 */
186 u32 command;
187 /* 23:16 is r/w intr rate, in microframes; default "8" == 1/msec */
188 #define CMD_PARK (1<<11) /* enable "park" on async qh */
189 #define CMD_PARK_CNT(c) (((c)>>8)&3) /* how many transfers to park for */
190 #define CMD_LRESET (1<<7) /* partial reset (no ports, etc) */
191 #define CMD_IAAD (1<<6) /* "doorbell" interrupt async advance */
192 #define CMD_ASE (1<<5) /* async schedule enable */
193 #define CMD_PSE (1<<4) /* periodic schedule enable */
194 /* 3:2 is periodic frame list size */
195 #define CMD_RESET (1<<1) /* reset HC not bus */
196 #define CMD_RUN (1<<0) /* start/stop HC */
197
198 /* USBSTS: offset 0x04 */
199 u32 status;
200 #define STS_ASS (1<<15) /* Async Schedule Status */
201 #define STS_PSS (1<<14) /* Periodic Schedule Status */
202 #define STS_RECL (1<<13) /* Reclamation */
203 #define STS_HALT (1<<12) /* Not running (any reason) */
204 /* some bits reserved */
205 /* these STS_* flags are also intr_enable bits (USBINTR) */
206 #define STS_IAA (1<<5) /* Interrupted on async advance */
207 #define STS_FATAL (1<<4) /* such as some PCI access errors */
208 #define STS_FLR (1<<3) /* frame list rolled over */
209 #define STS_PCD (1<<2) /* port change detect */
210 #define STS_ERR (1<<1) /* "error" completion (overflow, ...) */
211 #define STS_INT (1<<0) /* "normal" completion (short, ...) */
212
213 /* USBINTR: offset 0x08 */
214 u32 intr_enable;
215
216 /* FRINDEX: offset 0x0C */
217 u32 frame_index; /* current microframe number */
218 /* CTRLDSSEGMENT: offset 0x10 */
219 u32 segment; /* address bits 63:32 if needed */
220 /* PERIODICLISTBASE: offset 0x14 */
221 u32 frame_list; /* points to periodic list */
222 /* ASYNCICLISTADDR: offset 0x18 */
223 u32 async_next; /* address of next async queue head */
224
225 u32 reserved [9];
226
227 /* CONFIGFLAG: offset 0x40 */
228 u32 configured_flag;
229 #define FLAG_CF (1<<0) /* true: we'll support "high speed" */
230
231 /* PORTSC: offset 0x44 */
232 u32 port_status [0]; /* up to N_PORTS */
233 /* 31:23 reserved */
234 #define PORT_WKOC_E (1<<22) /* wake on overcurrent (enable) */
235 #define PORT_WKDISC_E (1<<21) /* wake on disconnect (enable) */
236 #define PORT_WKCONN_E (1<<20) /* wake on connect (enable) */
237 /* 19:16 for port testing */
238 /* 15:14 for using port indicator leds (if HCS_INDICATOR allows) */
239 #define PORT_OWNER (1<<13) /* true: companion hc owns this port */
240 #define PORT_POWER (1<<12) /* true: has power (see PPC) */
241 #define PORT_USB11(x) (((x)&(3<<10))==(1<<10)) /* USB 1.1 device */
242 /* 11:10 for detecting lowspeed devices (reset vs release ownership) */
243 /* 9 reserved */
244 #define PORT_RESET (1<<8) /* reset port */
245 #define PORT_SUSPEND (1<<7) /* suspend port */
246 #define PORT_RESUME (1<<6) /* resume it */
247 #define PORT_OCC (1<<5) /* over current change */
248 #define PORT_OC (1<<4) /* over current active */
249 #define PORT_PEC (1<<3) /* port enable change */
250 #define PORT_PE (1<<2) /* port enable */
251 #define PORT_CSC (1<<1) /* connect status change */
252 #define PORT_CONNECT (1<<0) /* device connected */
253 } __attribute__ ((packed));
254
255
256 /*-------------------------------------------------------------------------*/
257
258 #define QTD_NEXT(dma) cpu_to_le32((u32)dma)
259
260 /*
261 * EHCI Specification 0.95 Section 3.5
262 * QTD: describe data transfer components (buffer, direction, ...)
263 * See Fig 3-6 "Queue Element Transfer Descriptor Block Diagram".
264 *
265 * These are associated only with "QH" (Queue Head) structures,
266 * used with control, bulk, and interrupt transfers.
267 */
268 struct ehci_qtd {
269 /* first part defined by EHCI spec */
270 u32 hw_next; /* see EHCI 3.5.1 */
271 u32 hw_alt_next; /* see EHCI 3.5.2 */
272 u32 hw_token; /* see EHCI 3.5.3 */
273 #define QTD_TOGGLE (1 << 31) /* data toggle */
274 #define QTD_LENGTH(tok) (((tok)>>16) & 0x7fff)
275 #define QTD_IOC (1 << 15) /* interrupt on complete */
276 #define QTD_CERR(tok) (((tok)>>10) & 0x3)
277 #define QTD_PID(tok) (((tok)>>8) & 0x3)
278 #define QTD_STS_ACTIVE (1 << 7) /* HC may execute this */
279 #define QTD_STS_HALT (1 << 6) /* halted on error */
280 #define QTD_STS_DBE (1 << 5) /* data buffer error (in HC) */
281 #define QTD_STS_BABBLE (1 << 4) /* device was babbling (qtd halted) */
282 #define QTD_STS_XACT (1 << 3) /* device gave illegal response */
283 #define QTD_STS_MMF (1 << 2) /* incomplete split transaction */
284 #define QTD_STS_STS (1 << 1) /* split transaction state */
285 #define QTD_STS_PING (1 << 0) /* issue PING? */
286 u32 hw_buf [5]; /* see EHCI 3.5.4 */
287 u32 hw_buf_hi [5]; /* Appendix B */
288
289 /* the rest is HCD-private */
290 dma_addr_t qtd_dma; /* qtd address */
291 struct list_head qtd_list; /* sw qtd list */
292 struct urb *urb; /* qtd's urb */
293 size_t length; /* length of buffer */
294 } __attribute__ ((aligned (32)));
295
296 /* mask NakCnt+T in qh->hw_alt_next */
297 #define QTD_MASK __constant_cpu_to_le32 (~0x1f)
298
299 #define IS_SHORT_READ(token) (QTD_LENGTH (token) != 0 && QTD_PID (token) == 1)
300
301 /*-------------------------------------------------------------------------*/
302
303 /* type tag from {qh,itd,sitd,fstn}->hw_next */
304 #define Q_NEXT_TYPE(dma) ((dma) & __constant_cpu_to_le32 (3 << 1))
305
306 /* values for that type tag */
307 #define Q_TYPE_ITD __constant_cpu_to_le32 (0 << 1)
308 #define Q_TYPE_QH __constant_cpu_to_le32 (1 << 1)
309 #define Q_TYPE_SITD __constant_cpu_to_le32 (2 << 1)
310 #define Q_TYPE_FSTN __constant_cpu_to_le32 (3 << 1)
311
312 /* next async queue entry, or pointer to interrupt/periodic QH */
313 #define QH_NEXT(dma) (cpu_to_le32(((u32)dma)&~0x01f)|Q_TYPE_QH)
314
315 /* for periodic/async schedules and qtd lists, mark end of list */
316 #define EHCI_LIST_END __constant_cpu_to_le32(1) /* "null pointer" to hw */
317
318 /*
319 * Entries in periodic shadow table are pointers to one of four kinds
320 * of data structure. That's dictated by the hardware; a type tag is
321 * encoded in the low bits of the hardware's periodic schedule. Use
322 * Q_NEXT_TYPE to get the tag.
323 *
324 * For entries in the async schedule, the type tag always says "qh".
325 */
326 union ehci_shadow {
327 struct ehci_qh *qh; /* Q_TYPE_QH */
328 struct ehci_itd *itd; /* Q_TYPE_ITD */
329 struct ehci_sitd *sitd; /* Q_TYPE_SITD */
330 struct ehci_fstn *fstn; /* Q_TYPE_FSTN */
331 u32 *hw_next; /* (all types) */
332 void *ptr;
333 };
334
335 /*-------------------------------------------------------------------------*/
336
337 /*
338 * EHCI Specification 0.95 Section 3.6
339 * QH: describes control/bulk/interrupt endpoints
340 * See Fig 3-7 "Queue Head Structure Layout".
341 *
342 * These appear in both the async and (for interrupt) periodic schedules.
343 */
344
345 struct ehci_qh {
346 /* first part defined by EHCI spec */
347 u32 hw_next; /* see EHCI 3.6.1 */
348 u32 hw_info1; /* see EHCI 3.6.2 */
349 #define QH_HEAD 0x00008000
350 u32 hw_info2; /* see EHCI 3.6.2 */
351 u32 hw_current; /* qtd list - see EHCI 3.6.4 */
352
353 /* qtd overlay (hardware parts of a struct ehci_qtd) */
354 u32 hw_qtd_next;
355 u32 hw_alt_next;
356 u32 hw_token;
357 u32 hw_buf [5];
358 u32 hw_buf_hi [5];
359
360 /* the rest is HCD-private */
361 dma_addr_t qh_dma; /* address of qh */
362 union ehci_shadow qh_next; /* ptr to qh; or periodic */
363 struct list_head qtd_list; /* sw qtd list */
364 struct ehci_qtd *dummy;
365 struct ehci_qh *reclaim; /* next to reclaim */
366
367 atomic_t refcount;
368 unsigned stamp;
369
370 u8 qh_state;
371 #define QH_STATE_LINKED 1 /* HC sees this */
372 #define QH_STATE_UNLINK 2 /* HC may still see this */
373 #define QH_STATE_IDLE 3 /* HC doesn't see this */
374 #define QH_STATE_UNLINK_WAIT 4 /* LINKED and on reclaim q */
375 #define QH_STATE_COMPLETING 5 /* don't touch token.HALT */
376
377 /* periodic schedule info */
378 u8 usecs; /* intr bandwidth */
379 u8 gap_uf; /* uframes split/csplit gap */
380 u8 c_usecs; /* ... split completion bw */
381 unsigned short period; /* polling interval */
382 unsigned short start; /* where polling starts */
383 #define NO_FRAME ((unsigned short)~0) /* pick new start */
384 struct usb_device *dev; /* access to TT */
385 } __attribute__ ((aligned (32)));
386
387 /*-------------------------------------------------------------------------*/
388
389 /* description of one iso highspeed transaction (up to 3 KB data) */
390 struct ehci_iso_uframe {
391 /* These will be copied to iTD when scheduling */
392 u64 bufp; /* itd->hw_bufp{,_hi}[pg] |= */
393 u32 transaction; /* itd->hw_transaction[i] |= */
394 u8 cross; /* buf crosses pages */
395 };
396
397 /* temporary schedule data for highspeed packets from iso urbs
398 * each packet is one uframe's usb transactions, in some itd,
399 * beginning at stream->next_uframe
400 */
401 struct ehci_itd_sched {
402 struct list_head itd_list;
403 unsigned span;
404 struct ehci_iso_uframe packet [0];
405 };
406
407 /*
408 * ehci_iso_stream - groups all (s)itds for this endpoint.
409 * acts like a qh would, if EHCI had them for ISO.
410 */
411 struct ehci_iso_stream {
412 /* first two fields match QH, but info1 == 0 */
413 u32 hw_next;
414 u32 hw_info1;
415
416 u32 refcount;
417 u8 bEndpointAddress;
418 struct list_head itd_list; /* queued itds */
419 struct list_head free_itd_list; /* list of unused itds */
420 struct hcd_dev *dev;
421
422 /* output of (re)scheduling */
423 unsigned long start; /* jiffies */
424 unsigned long rescheduled;
425 int next_uframe;
426
427 /* the rest is derived from the endpoint descriptor,
428 * trusting urb->interval == (1 << (epdesc->bInterval - 1)),
429 * including the extra info for hw_bufp[0..2]
430 */
431 u8 interval;
432 u8 usecs;
433 u16 maxp;
434 unsigned bandwidth;
435
436 /* This is used to initialize iTD's hw_bufp fields */
437 u32 buf0;
438 u32 buf1;
439 u32 buf2;
440
441 /* ... sITD won't use buf[012], and needs TT access ... */
442 };
443
444 /*-------------------------------------------------------------------------*/
445
446 /*
447 * EHCI Specification 0.95 Section 3.3
448 * Fig 3-4 "Isochronous Transaction Descriptor (iTD)"
449 *
450 * Schedule records for high speed iso xfers
451 */
452 struct ehci_itd {
453 /* first part defined by EHCI spec */
454 u32 hw_next; /* see EHCI 3.3.1 */
455 u32 hw_transaction [8]; /* see EHCI 3.3.2 */
456 #define EHCI_ISOC_ACTIVE (1<<31) /* activate transfer this slot */
457 #define EHCI_ISOC_BUF_ERR (1<<30) /* Data buffer error */
458 #define EHCI_ISOC_BABBLE (1<<29) /* babble detected */
459 #define EHCI_ISOC_XACTERR (1<<28) /* XactErr - transaction error */
460 #define EHCI_ITD_LENGTH(tok) (((tok)>>16) & 0x0fff)
461 #define EHCI_ITD_IOC (1 << 15) /* interrupt on complete */
462
463 #define ISO_ACTIVE __constant_cpu_to_le32(EHCI_ISOC_ACTIVE)
464
465 u32 hw_bufp [7]; /* see EHCI 3.3.3 */
466 u32 hw_bufp_hi [7]; /* Appendix B */
467
468 /* the rest is HCD-private */
469 dma_addr_t itd_dma; /* for this itd */
470 union ehci_shadow itd_next; /* ptr to periodic q entry */
471
472 struct urb *urb;
473 struct ehci_iso_stream *stream; /* endpoint's queue */
474 struct list_head itd_list; /* list of stream's itds */
475
476 /* any/all hw_transactions here may be used by that urb */
477 unsigned frame; /* where scheduled */
478 unsigned pg;
479 unsigned index[8]; /* in urb->iso_frame_desc */
480 u8 usecs[8];
481 } __attribute__ ((aligned (32)));
482
483 /*-------------------------------------------------------------------------*/
484
485 /*
486 * EHCI Specification 0.95 Section 3.4
487 * siTD, aka split-transaction isochronous Transfer Descriptor
488 * ... describe low/full speed iso xfers through TT in hubs
489 * see Figure 3-5 "Split-transaction Isochronous Transaction Descriptor (siTD)
490 */
491 struct ehci_sitd {
492 /* first part defined by EHCI spec */
493 u32 hw_next;
494 /* uses bit field macros above - see EHCI 0.95 Table 3-8 */
495 u32 hw_fullspeed_ep; /* see EHCI table 3-9 */
496 u32 hw_uframe; /* see EHCI table 3-10 */
497 u32 hw_tx_results1; /* see EHCI table 3-11 */
498 u32 hw_tx_results2; /* see EHCI table 3-12 */
499 u32 hw_tx_results3; /* see EHCI table 3-12 */
500 u32 hw_backpointer; /* see EHCI table 3-13 */
501 u32 hw_buf_hi [2]; /* Appendix B */
502
503 /* the rest is HCD-private */
504 dma_addr_t sitd_dma;
505 union ehci_shadow sitd_next; /* ptr to periodic q entry */
506 struct urb *urb;
507 dma_addr_t buf_dma; /* buffer address */
508
509 unsigned short usecs; /* start bandwidth */
510 unsigned short c_usecs; /* completion bandwidth */
511 } __attribute__ ((aligned (32)));
512
513 /*-------------------------------------------------------------------------*/
514
515 /*
516 * EHCI Specification 0.96 Section 3.7
517 * Periodic Frame Span Traversal Node (FSTN)
518 *
519 * Manages split interrupt transactions (using TT) that span frame boundaries
520 * into uframes 0/1; see 4.12.2.2. In those uframes, a "save place" FSTN
521 * makes the HC jump (back) to a QH to scan for fs/ls QH completions until
522 * it hits a "restore" FSTN; then it returns to finish other uframe 0/1 work.
523 */
524 struct ehci_fstn {
525 u32 hw_next; /* any periodic q entry */
526 u32 hw_prev; /* qh or EHCI_LIST_END */
527
528 /* the rest is HCD-private */
529 dma_addr_t fstn_dma;
530 union ehci_shadow fstn_next; /* ptr to periodic q entry */
531 } __attribute__ ((aligned (32)));
532
533 /*-------------------------------------------------------------------------*/
534
535 #include <linux/version.h>
536 #if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,32)
537
538 #define SUBMIT_URB(urb,mem_flags) usb_submit_urb(urb)
539 #define STUB_DEBUG_FILES
540
hcd_register_root(struct usb_hcd * hcd)541 static inline int hcd_register_root (struct usb_hcd *hcd)
542 {
543 return usb_new_device (hcd_to_bus (hcd)->root_hub);
544 }
545
546 #else /* LINUX_VERSION_CODE */
547
548 // hcd_to_bus() eventually moves to hcd.h on 2.5 too
hcd_to_bus(struct usb_hcd * hcd)549 static inline struct usb_bus *hcd_to_bus (struct usb_hcd *hcd)
550 { return &hcd->self; }
551 // ... as does hcd_register_root()
hcd_register_root(struct usb_hcd * hcd)552 static inline int hcd_register_root (struct usb_hcd *hcd)
553 {
554 return usb_register_root_hub (
555 hcd_to_bus (hcd)->root_hub, &hcd->pdev->dev);
556 }
557
558 #define SUBMIT_URB(urb,mem_flags) usb_submit_urb(urb,mem_flags)
559
560 #ifndef DEBUG
561 #define STUB_DEBUG_FILES
562 #endif /* DEBUG */
563
564 #endif /* LINUX_VERSION_CODE */
565
566 /*-------------------------------------------------------------------------*/
567
568 #endif /* __LINUX_EHCI_HCD_H */
569