1 /*
2 **********************************************************************
3 * hwaccess.c -- Hardware access layer
4 * Copyright 1999, 2000 Creative Labs, Inc.
5 *
6 **********************************************************************
7 *
8 * Date Author Summary of changes
9 * ---- ------ ------------------
10 * October 20, 1999 Bertrand Lee base code release
11 * December 9, 1999 Jon Taylor rewrote the I/O subsystem
12 *
13 **********************************************************************
14 *
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License as
17 * published by the Free Software Foundation; either version 2 of
18 * the License, or (at your option) any later version.
19 *
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 *
25 * You should have received a copy of the GNU General Public
26 * License along with this program; if not, write to the Free
27 * Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139,
28 * USA.
29 *
30 **********************************************************************
31 */
32
33 #include <asm/io.h>
34
35 #include "hwaccess.h"
36 #include "8010.h"
37 #include "icardmid.h"
38
39 /*************************************************************************
40 * Function : srToPitch *
41 * Input : sampleRate - sampling rate *
42 * Return : pitch value *
43 * About : convert sampling rate to pitch *
44 * Note : for 8010, sampling rate is at 48kHz, this function should *
45 * be changed. *
46 *************************************************************************/
srToPitch(u32 sampleRate)47 u32 srToPitch(u32 sampleRate)
48 {
49 int i;
50
51 /* FIXME: These tables should be defined in a headerfile */
52 static u32 logMagTable[128] = {
53 0x00000, 0x02dfc, 0x05b9e, 0x088e6, 0x0b5d6, 0x0e26f, 0x10eb3, 0x13aa2,
54 0x1663f, 0x1918a, 0x1bc84, 0x1e72e, 0x2118b, 0x23b9a, 0x2655d, 0x28ed5,
55 0x2b803, 0x2e0e8, 0x30985, 0x331db, 0x359eb, 0x381b6, 0x3a93d, 0x3d081,
56 0x3f782, 0x41e42, 0x444c1, 0x46b01, 0x49101, 0x4b6c4, 0x4dc49, 0x50191,
57 0x5269e, 0x54b6f, 0x57006, 0x59463, 0x5b888, 0x5dc74, 0x60029, 0x623a7,
58 0x646ee, 0x66a00, 0x68cdd, 0x6af86, 0x6d1fa, 0x6f43c, 0x7164b, 0x73829,
59 0x759d4, 0x77b4f, 0x79c9a, 0x7bdb5, 0x7dea1, 0x7ff5e, 0x81fed, 0x8404e,
60 0x86082, 0x88089, 0x8a064, 0x8c014, 0x8df98, 0x8fef1, 0x91e20, 0x93d26,
61 0x95c01, 0x97ab4, 0x9993e, 0x9b79f, 0x9d5d9, 0x9f3ec, 0xa11d8, 0xa2f9d,
62 0xa4d3c, 0xa6ab5, 0xa8808, 0xaa537, 0xac241, 0xadf26, 0xafbe7, 0xb1885,
63 0xb3500, 0xb5157, 0xb6d8c, 0xb899f, 0xba58f, 0xbc15e, 0xbdd0c, 0xbf899,
64 0xc1404, 0xc2f50, 0xc4a7b, 0xc6587, 0xc8073, 0xc9b3f, 0xcb5ed, 0xcd07c,
65 0xceaec, 0xd053f, 0xd1f73, 0xd398a, 0xd5384, 0xd6d60, 0xd8720, 0xda0c3,
66 0xdba4a, 0xdd3b4, 0xded03, 0xe0636, 0xe1f4e, 0xe384a, 0xe512c, 0xe69f3,
67 0xe829f, 0xe9b31, 0xeb3a9, 0xecc08, 0xee44c, 0xefc78, 0xf148a, 0xf2c83,
68 0xf4463, 0xf5c2a, 0xf73da, 0xf8b71, 0xfa2f0, 0xfba57, 0xfd1a7, 0xfe8df
69 };
70
71 static char logSlopeTable[128] = {
72 0x5c, 0x5c, 0x5b, 0x5a, 0x5a, 0x59, 0x58, 0x58,
73 0x57, 0x56, 0x56, 0x55, 0x55, 0x54, 0x53, 0x53,
74 0x52, 0x52, 0x51, 0x51, 0x50, 0x50, 0x4f, 0x4f,
75 0x4e, 0x4d, 0x4d, 0x4d, 0x4c, 0x4c, 0x4b, 0x4b,
76 0x4a, 0x4a, 0x49, 0x49, 0x48, 0x48, 0x47, 0x47,
77 0x47, 0x46, 0x46, 0x45, 0x45, 0x45, 0x44, 0x44,
78 0x43, 0x43, 0x43, 0x42, 0x42, 0x42, 0x41, 0x41,
79 0x41, 0x40, 0x40, 0x40, 0x3f, 0x3f, 0x3f, 0x3e,
80 0x3e, 0x3e, 0x3d, 0x3d, 0x3d, 0x3c, 0x3c, 0x3c,
81 0x3b, 0x3b, 0x3b, 0x3b, 0x3a, 0x3a, 0x3a, 0x39,
82 0x39, 0x39, 0x39, 0x38, 0x38, 0x38, 0x38, 0x37,
83 0x37, 0x37, 0x37, 0x36, 0x36, 0x36, 0x36, 0x35,
84 0x35, 0x35, 0x35, 0x34, 0x34, 0x34, 0x34, 0x34,
85 0x33, 0x33, 0x33, 0x33, 0x32, 0x32, 0x32, 0x32,
86 0x32, 0x31, 0x31, 0x31, 0x31, 0x31, 0x30, 0x30,
87 0x30, 0x30, 0x30, 0x2f, 0x2f, 0x2f, 0x2f, 0x2f
88 };
89
90 if (sampleRate == 0)
91 return 0; /* Bail out if no leading "1" */
92
93 sampleRate *= 11185; /* Scale 48000 to 0x20002380 */
94
95 for (i = 31; i > 0; i--) {
96 if (sampleRate & 0x80000000) { /* Detect leading "1" */
97 return (u32) (((s32) (i - 15) << 20) +
98 logMagTable[0x7f & (sampleRate >> 24)] +
99 (0x7f & (sampleRate >> 17)) * logSlopeTable[0x7f & (sampleRate >> 24)]);
100 }
101 sampleRate = sampleRate << 1;
102 }
103
104 DPF(2, "srToPitch: BUG!\n");
105 return 0; /* Should never reach this point */
106 }
107
108 /* Returns an attenuation based upon a cumulative volume value */
109
110 /* Algorithm calculates 0x200 - 0x10 log2 (input) */
sumVolumeToAttenuation(u32 value)111 u8 sumVolumeToAttenuation(u32 value)
112 {
113 u16 count = 16;
114 s16 ans;
115
116 if (value == 0)
117 return 0xFF;
118
119 /* Find first SET bit. This is the integer part of the value */
120 while ((value & 0x10000) == 0) {
121 value <<= 1;
122 count--;
123 }
124
125 /* The REST of the data is the fractional part. */
126 ans = (s16) (0x110 - ((count << 4) + ((value & 0x0FFFFL) >> 12)));
127 if (ans > 0xFF)
128 ans = 0xFF;
129
130 return (u8) ans;
131 }
132
133 /*******************************************
134 * write/read PCI function 0 registers *
135 ********************************************/
emu10k1_writefn0(struct emu10k1_card * card,u32 reg,u32 data)136 void emu10k1_writefn0(struct emu10k1_card *card, u32 reg, u32 data)
137 {
138 unsigned long flags;
139
140 if (reg & 0xff000000) {
141 u32 mask;
142 u8 size, offset;
143
144 size = (reg >> 24) & 0x3f;
145 offset = (reg >> 16) & 0x1f;
146 mask = ((1 << size) - 1) << offset;
147 data = (data << offset) & mask;
148 reg &= 0x7f;
149
150 spin_lock_irqsave(&card->lock, flags);
151 data |= inl(card->iobase + reg) & ~mask;
152 outl(data, card->iobase + reg);
153 spin_unlock_irqrestore(&card->lock, flags);
154 } else {
155 spin_lock_irqsave(&card->lock, flags);
156 outl(data, card->iobase + reg);
157 spin_unlock_irqrestore(&card->lock, flags);
158 }
159
160 return;
161 }
162
emu10k1_readfn0(struct emu10k1_card * card,u32 reg)163 u32 emu10k1_readfn0(struct emu10k1_card * card, u32 reg)
164 {
165 u32 val;
166 unsigned long flags;
167
168 if (reg & 0xff000000) {
169 u32 mask;
170 u8 size, offset;
171
172 size = (reg >> 24) & 0x3f;
173 offset = (reg >> 16) & 0x1f;
174 mask = ((1 << size) - 1) << offset;
175 reg &= 0x7f;
176
177 spin_lock_irqsave(&card->lock, flags);
178 val = inl(card->iobase + reg);
179 spin_unlock_irqrestore(&card->lock, flags);
180
181 return (val & mask) >> offset;
182 } else {
183 spin_lock_irqsave(&card->lock, flags);
184 val = inl(card->iobase + reg);
185 spin_unlock_irqrestore(&card->lock, flags);
186 return val;
187 }
188 }
189
emu10k1_timer_set(struct emu10k1_card * card,u16 data)190 void emu10k1_timer_set(struct emu10k1_card * card, u16 data)
191 {
192 unsigned long flags;
193
194 spin_lock_irqsave(&card->lock, flags);
195 outw(data & TIMER_RATE_MASK, card->iobase + TIMER);
196 spin_unlock_irqrestore(&card->lock, flags);
197 }
198
199 /************************************************************************
200 * write/read Emu10k1 pointer-offset register set, accessed through *
201 * the PTR and DATA registers *
202 *************************************************************************/
sblive_writeptr(struct emu10k1_card * card,u32 reg,u32 channel,u32 data)203 void sblive_writeptr(struct emu10k1_card *card, u32 reg, u32 channel, u32 data)
204 {
205 u32 regptr;
206 unsigned long flags;
207
208 regptr = ((reg << 16) & PTR_ADDRESS_MASK) | (channel & PTR_CHANNELNUM_MASK);
209
210 if (reg & 0xff000000) {
211 u32 mask;
212 u8 size, offset;
213
214 size = (reg >> 24) & 0x3f;
215 offset = (reg >> 16) & 0x1f;
216 mask = ((1 << size) - 1) << offset;
217 data = (data << offset) & mask;
218
219 spin_lock_irqsave(&card->lock, flags);
220 outl(regptr, card->iobase + PTR);
221 data |= inl(card->iobase + DATA) & ~mask;
222 outl(data, card->iobase + DATA);
223 spin_unlock_irqrestore(&card->lock, flags);
224 } else {
225 spin_lock_irqsave(&card->lock, flags);
226 outl(regptr, card->iobase + PTR);
227 outl(data, card->iobase + DATA);
228 spin_unlock_irqrestore(&card->lock, flags);
229 }
230 }
231
232 /* ... : data, reg, ... , TAGLIST_END */
sblive_writeptr_tag(struct emu10k1_card * card,u32 channel,...)233 void sblive_writeptr_tag(struct emu10k1_card *card, u32 channel, ...)
234 {
235 va_list args;
236
237 unsigned long flags;
238 u32 reg;
239
240 va_start(args, channel);
241
242 spin_lock_irqsave(&card->lock, flags);
243 while ((reg = va_arg(args, u32)) != TAGLIST_END) {
244 u32 data = va_arg(args, u32);
245 u32 regptr = (((reg << 16) & PTR_ADDRESS_MASK)
246 | (channel & PTR_CHANNELNUM_MASK));
247 outl(regptr, card->iobase + PTR);
248 if (reg & 0xff000000) {
249 int size = (reg >> 24) & 0x3f;
250 int offset = (reg >> 16) & 0x1f;
251 u32 mask = ((1 << size) - 1) << offset;
252 data = (data << offset) & mask;
253
254 data |= inl(card->iobase + DATA) & ~mask;
255 }
256 outl(data, card->iobase + DATA);
257 }
258 spin_unlock_irqrestore(&card->lock, flags);
259
260 va_end(args);
261
262 return;
263 }
264
sblive_readptr(struct emu10k1_card * card,u32 reg,u32 channel)265 u32 sblive_readptr(struct emu10k1_card * card, u32 reg, u32 channel)
266 {
267 u32 regptr, val;
268 unsigned long flags;
269
270 regptr = ((reg << 16) & PTR_ADDRESS_MASK) | (channel & PTR_CHANNELNUM_MASK);
271
272 if (reg & 0xff000000) {
273 u32 mask;
274 u8 size, offset;
275
276 size = (reg >> 24) & 0x3f;
277 offset = (reg >> 16) & 0x1f;
278 mask = ((1 << size) - 1) << offset;
279
280 spin_lock_irqsave(&card->lock, flags);
281 outl(regptr, card->iobase + PTR);
282 val = inl(card->iobase + DATA);
283 spin_unlock_irqrestore(&card->lock, flags);
284
285 return (val & mask) >> offset;
286 } else {
287 spin_lock_irqsave(&card->lock, flags);
288 outl(regptr, card->iobase + PTR);
289 val = inl(card->iobase + DATA);
290 spin_unlock_irqrestore(&card->lock, flags);
291
292 return val;
293 }
294 }
295
emu10k1_irq_enable(struct emu10k1_card * card,u32 irq_mask)296 void emu10k1_irq_enable(struct emu10k1_card *card, u32 irq_mask)
297 {
298 u32 val;
299 unsigned long flags;
300
301 DPF(2,"emu10k1_irq_enable()\n");
302
303 spin_lock_irqsave(&card->lock, flags);
304 val = inl(card->iobase + INTE) | irq_mask;
305 outl(val, card->iobase + INTE);
306 spin_unlock_irqrestore(&card->lock, flags);
307 return;
308 }
309
emu10k1_irq_disable(struct emu10k1_card * card,u32 irq_mask)310 void emu10k1_irq_disable(struct emu10k1_card *card, u32 irq_mask)
311 {
312 u32 val;
313 unsigned long flags;
314
315 DPF(2,"emu10k1_irq_disable()\n");
316
317 spin_lock_irqsave(&card->lock, flags);
318 val = inl(card->iobase + INTE) & ~irq_mask;
319 outl(val, card->iobase + INTE);
320 spin_unlock_irqrestore(&card->lock, flags);
321 return;
322 }
323
emu10k1_set_stop_on_loop(struct emu10k1_card * card,u32 voicenum)324 void emu10k1_set_stop_on_loop(struct emu10k1_card *card, u32 voicenum)
325 {
326 /* Voice interrupt */
327 if (voicenum >= 32)
328 sblive_writeptr(card, SOLEH | ((0x0100 | (voicenum - 32)) << 16), 0, 1);
329 else
330 sblive_writeptr(card, SOLEL | ((0x0100 | voicenum) << 16), 0, 1);
331
332 return;
333 }
334
emu10k1_clear_stop_on_loop(struct emu10k1_card * card,u32 voicenum)335 void emu10k1_clear_stop_on_loop(struct emu10k1_card *card, u32 voicenum)
336 {
337 /* Voice interrupt */
338 if (voicenum >= 32)
339 sblive_writeptr(card, SOLEH | ((0x0100 | (voicenum - 32)) << 16), 0, 0);
340 else
341 sblive_writeptr(card, SOLEL | ((0x0100 | voicenum) << 16), 0, 0);
342
343 return;
344 }
345
sblive_wcwait(struct emu10k1_card * card,u32 wait)346 static void sblive_wcwait(struct emu10k1_card *card, u32 wait)
347 {
348 volatile unsigned uCount;
349 u32 newtime = 0, curtime;
350
351 curtime = emu10k1_readfn0(card, WC_SAMPLECOUNTER);
352 while (wait--) {
353 uCount = 0;
354 while (uCount++ < TIMEOUT) {
355 newtime = emu10k1_readfn0(card, WC_SAMPLECOUNTER);
356 if (newtime != curtime)
357 break;
358 }
359
360 if (uCount >= TIMEOUT)
361 break;
362
363 curtime = newtime;
364 }
365 }
366
emu10k1_ac97_read(struct ac97_codec * codec,u8 reg)367 u16 emu10k1_ac97_read(struct ac97_codec *codec, u8 reg)
368 {
369 struct emu10k1_card *card = codec->private_data;
370 u16 data;
371 unsigned long flags;
372
373 spin_lock_irqsave(&card->lock, flags);
374
375 outb(reg, card->iobase + AC97ADDRESS);
376 data = inw(card->iobase + AC97DATA);
377
378 spin_unlock_irqrestore(&card->lock, flags);
379
380 return data;
381 }
382
emu10k1_ac97_write(struct ac97_codec * codec,u8 reg,u16 value)383 void emu10k1_ac97_write(struct ac97_codec *codec, u8 reg, u16 value)
384 {
385 struct emu10k1_card *card = codec->private_data;
386 unsigned long flags;
387
388 spin_lock_irqsave(&card->lock, flags);
389
390 outb(reg, card->iobase + AC97ADDRESS);
391 outw(value, card->iobase + AC97DATA);
392
393 spin_unlock_irqrestore(&card->lock, flags);
394 }
395
396 /*********************************************************
397 * MPU access functions *
398 **********************************************************/
399
emu10k1_mpu_write_data(struct emu10k1_card * card,u8 data)400 int emu10k1_mpu_write_data(struct emu10k1_card *card, u8 data)
401 {
402 unsigned long flags;
403 int ret;
404
405 spin_lock_irqsave(&card->lock, flags);
406
407 if ((inb(card->iobase + MUSTAT) & MUSTAT_ORDYN) == 0) {
408 outb(data, card->iobase + MUDATA);
409 ret = 0;
410 } else
411 ret = -1;
412
413 spin_unlock_irqrestore(&card->lock, flags);
414
415 return ret;
416 }
417
emu10k1_mpu_read_data(struct emu10k1_card * card,u8 * data)418 int emu10k1_mpu_read_data(struct emu10k1_card *card, u8 * data)
419 {
420 unsigned long flags;
421 int ret;
422
423 spin_lock_irqsave(&card->lock, flags);
424
425 if ((inb(card->iobase + MUSTAT) & MUSTAT_IRDYN) == 0) {
426 *data = inb(card->iobase + MUDATA);
427 ret = 0;
428 } else
429 ret = -1;
430
431 spin_unlock_irqrestore(&card->lock, flags);
432
433 return ret;
434 }
435
emu10k1_mpu_reset(struct emu10k1_card * card)436 int emu10k1_mpu_reset(struct emu10k1_card *card)
437 {
438 u8 status;
439 unsigned long flags;
440
441 DPF(2, "emu10k1_mpu_reset()\n");
442
443 if (card->mpuacqcount == 0) {
444 spin_lock_irqsave(&card->lock, flags);
445 outb(MUCMD_RESET, card->iobase + MUCMD);
446 spin_unlock_irqrestore(&card->lock, flags);
447
448 sblive_wcwait(card, 8);
449
450 spin_lock_irqsave(&card->lock, flags);
451 outb(MUCMD_RESET, card->iobase + MUCMD);
452 spin_unlock_irqrestore(&card->lock, flags);
453
454 sblive_wcwait(card, 8);
455
456 spin_lock_irqsave(&card->lock, flags);
457 outb(MUCMD_ENTERUARTMODE, card->iobase + MUCMD);
458 spin_unlock_irqrestore(&card->lock, flags);
459
460 sblive_wcwait(card, 8);
461
462 spin_lock_irqsave(&card->lock, flags);
463 status = inb(card->iobase + MUDATA);
464 spin_unlock_irqrestore(&card->lock, flags);
465
466 if (status == 0xfe)
467 return 0;
468 else
469 return -1;
470 }
471
472 return 0;
473 }
474
emu10k1_mpu_acquire(struct emu10k1_card * card)475 int emu10k1_mpu_acquire(struct emu10k1_card *card)
476 {
477 /* FIXME: This should be a macro */
478 ++card->mpuacqcount;
479
480 return 0;
481 }
482
emu10k1_mpu_release(struct emu10k1_card * card)483 int emu10k1_mpu_release(struct emu10k1_card *card)
484 {
485 /* FIXME: this should be a macro */
486 --card->mpuacqcount;
487
488 return 0;
489 }
490