1 /* 2 * mesh.h: definitions for the driver for the MESH SCSI bus adaptor 3 * (Macintosh Enhanced SCSI Hardware) found on Power Macintosh computers. 4 * 5 * Copyright (C) 1996 Paul Mackerras. 6 */ 7 #ifndef _MESH_H 8 #define _MESH_H 9 10 int mesh_detect(Scsi_Host_Template *); 11 int mesh_release(struct Scsi_Host *); 12 int mesh_queue(Scsi_Cmnd *, void (*done)(Scsi_Cmnd *)); 13 int mesh_abort(Scsi_Cmnd *); 14 int mesh_host_reset(Scsi_Cmnd *); 15 16 #define SCSI_MESH { \ 17 proc_name: "mesh", \ 18 name: "MESH", \ 19 detect: mesh_detect, \ 20 release: mesh_release, \ 21 command: NULL, \ 22 queuecommand: mesh_queue, \ 23 eh_abort_handler: mesh_abort, \ 24 eh_device_reset_handler: NULL, \ 25 eh_bus_reset_handler: NULL, \ 26 eh_host_reset_handler: mesh_host_reset, \ 27 can_queue: 20, \ 28 this_id: 7, \ 29 sg_tablesize: SG_ALL, \ 30 cmd_per_lun: 2, \ 31 use_clustering: DISABLE_CLUSTERING, \ 32 use_new_eh_code: 1, \ 33 } 34 35 /* 36 * Registers in the MESH controller. 37 */ 38 39 struct mesh_regs { 40 unsigned char count_lo; 41 char pad0[15]; 42 unsigned char count_hi; 43 char pad1[15]; 44 unsigned char fifo; 45 char pad2[15]; 46 unsigned char sequence; 47 char pad3[15]; 48 unsigned char bus_status0; 49 char pad4[15]; 50 unsigned char bus_status1; 51 char pad5[15]; 52 unsigned char fifo_count; 53 char pad6[15]; 54 unsigned char exception; 55 char pad7[15]; 56 unsigned char error; 57 char pad8[15]; 58 unsigned char intr_mask; 59 char pad9[15]; 60 unsigned char interrupt; 61 char pad10[15]; 62 unsigned char source_id; 63 char pad11[15]; 64 unsigned char dest_id; 65 char pad12[15]; 66 unsigned char sync_params; 67 char pad13[15]; 68 unsigned char mesh_id; 69 char pad14[15]; 70 unsigned char sel_timeout; 71 char pad15[15]; 72 }; 73 74 /* Bits in the sequence register. */ 75 #define SEQ_DMA_MODE 0x80 /* use DMA for data transfer */ 76 #define SEQ_TARGET 0x40 /* put the controller into target mode */ 77 #define SEQ_ATN 0x20 /* assert ATN signal */ 78 #define SEQ_ACTIVE_NEG 0x10 /* use active negation on REQ/ACK */ 79 #define SEQ_CMD 0x0f /* command bits: */ 80 #define SEQ_ARBITRATE 1 /* get the bus */ 81 #define SEQ_SELECT 2 /* select a target */ 82 #define SEQ_COMMAND 3 /* send a command */ 83 #define SEQ_STATUS 4 /* receive status */ 84 #define SEQ_DATAOUT 5 /* send data */ 85 #define SEQ_DATAIN 6 /* receive data */ 86 #define SEQ_MSGOUT 7 /* send a message */ 87 #define SEQ_MSGIN 8 /* receive a message */ 88 #define SEQ_BUSFREE 9 /* look for bus free */ 89 #define SEQ_ENBPARITY 0x0a /* enable parity checking */ 90 #define SEQ_DISPARITY 0x0b /* disable parity checking */ 91 #define SEQ_ENBRESEL 0x0c /* enable reselection */ 92 #define SEQ_DISRESEL 0x0d /* disable reselection */ 93 #define SEQ_RESETMESH 0x0e /* reset the controller */ 94 #define SEQ_FLUSHFIFO 0x0f /* clear out the FIFO */ 95 96 /* Bits in the bus_status0 and bus_status1 registers: 97 these correspond directly to the SCSI bus control signals. */ 98 #define BS0_REQ 0x20 99 #define BS0_ACK 0x10 100 #define BS0_ATN 0x08 101 #define BS0_MSG 0x04 102 #define BS0_CD 0x02 103 #define BS0_IO 0x01 104 #define BS1_RST 0x80 105 #define BS1_BSY 0x40 106 #define BS1_SEL 0x20 107 108 /* Bus phases defined by the bits in bus_status0 */ 109 #define BS0_PHASE (BS0_MSG+BS0_CD+BS0_IO) 110 #define BP_DATAOUT 0 111 #define BP_DATAIN BS0_IO 112 #define BP_COMMAND BS0_CD 113 #define BP_STATUS (BS0_CD+BS0_IO) 114 #define BP_MSGOUT (BS0_MSG+BS0_CD) 115 #define BP_MSGIN (BS0_MSG+BS0_CD+BS0_IO) 116 117 /* Bits in the exception register. */ 118 #define EXC_SELWATN 0x20 /* (as target) we were selected with ATN */ 119 #define EXC_SELECTED 0x10 /* (as target) we were selected w/o ATN */ 120 #define EXC_RESELECTED 0x08 /* (as initiator) we were reselected */ 121 #define EXC_ARBLOST 0x04 /* we lost arbitration */ 122 #define EXC_PHASEMM 0x02 /* SCSI phase mismatch */ 123 #define EXC_SELTO 0x01 /* selection timeout */ 124 125 /* Bits in the error register */ 126 #define ERR_UNEXPDISC 0x40 /* target unexpectedly disconnected */ 127 #define ERR_SCSIRESET 0x20 /* SCSI bus got reset on us */ 128 #define ERR_SEQERR 0x10 /* we did something the chip didn't like */ 129 #define ERR_PARITY 0x01 /* parity error was detected */ 130 131 /* Bits in the interrupt and intr_mask registers */ 132 #define INT_ERROR 0x04 /* error interrupt */ 133 #define INT_EXCEPTION 0x02 /* exception interrupt */ 134 #define INT_CMDDONE 0x01 /* command done interrupt */ 135 136 /* Fields in the sync_params register */ 137 #define SYNC_OFF(x) ((x) >> 4) /* offset field */ 138 #define SYNC_PER(x) ((x) & 0xf) /* period field */ 139 #define SYNC_PARAMS(o, p) (((o) << 4) | (p)) 140 #define ASYNC_PARAMS 2 /* sync_params value for async xfers */ 141 142 /* 143 * Assuming a clock frequency of 50MHz: 144 * 145 * The transfer period with SYNC_PER(sync_params) == x 146 * is (x + 2) * 40ns, except that x == 0 gives 100ns. 147 * 148 * The units of the sel_timeout register are 10ms. 149 */ 150 151 152 #endif /* _MESH_H */ 153