1 /*======================================================================
2
3 Device driver for the PCMCIA control functionality of StrongARM
4 SA-1100 microprocessors.
5
6 The contents of this file are subject to the Mozilla Public
7 License Version 1.1 (the "License"); you may not use this file
8 except in compliance with the License. You may obtain a copy of
9 the License at http://www.mozilla.org/MPL/
10
11 Software distributed under the License is distributed on an "AS
12 IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
13 implied. See the License for the specific language governing
14 rights and limitations under the License.
15
16 The initial developer of the original code is John G. Dorsey
17 <john+@cs.cmu.edu>. Portions created by John G. Dorsey are
18 Copyright (C) 1999 John G. Dorsey. All Rights Reserved.
19
20 Alternatively, the contents of this file may be used under the
21 terms of the GNU Public License version 2 (the "GPL"), in which
22 case the provisions of the GPL are applicable instead of the
23 above. If you wish to allow the use of your version of this file
24 only under the terms of the GPL and not to allow others to use
25 your version of this file under the MPL, indicate your decision
26 by deleting the provisions above and replace them with the notice
27 and other provisions required by the GPL. If you do not delete
28 the provisions above, a recipient may use your version of this
29 file under either the MPL or the GPL.
30
31 ======================================================================*/
32
33 #if !defined(_PCMCIA_SA1100_H)
34 # define _PCMCIA_SA1100_H
35
36 #include <pcmcia/cs_types.h>
37 #include <pcmcia/ss.h>
38 #include <pcmcia/bulkmem.h>
39 #include <pcmcia/cistpl.h>
40 #include "cs_internal.h"
41 #include "sa1100_generic.h"
42
43 /* MECR: Expansion Memory Configuration Register
44 * (SA-1100 Developers Manual, p.10-13; SA-1110 Developers Manual, p.10-24)
45 *
46 * MECR layout is:
47 *
48 * FAST1 BSM1<4:0> BSA1<4:0> BSIO1<4:0> FAST0 BSM0<4:0> BSA0<4:0> BSIO0<4:0>
49 *
50 * (This layout is actually true only for the SA-1110; the FASTn bits are
51 * reserved on the SA-1100.)
52 */
53
54 #define MECR_SOCKET_0_SHIFT (0)
55 #define MECR_SOCKET_1_SHIFT (16)
56
57 #define MECR_BS_MASK (0x1f)
58 #define MECR_FAST_MODE_MASK (0x01)
59
60 #define MECR_BSIO_SHIFT (0)
61 #define MECR_BSA_SHIFT (5)
62 #define MECR_BSM_SHIFT (10)
63 #define MECR_FAST_SHIFT (15)
64
65 #define MECR_SET(mecr, sock, shift, mask, bs) \
66 ((mecr)=((mecr)&~(((mask)<<(shift))<<\
67 ((sock)==0?MECR_SOCKET_0_SHIFT:MECR_SOCKET_1_SHIFT)))|\
68 (((bs)<<(shift))<<((sock)==0?MECR_SOCKET_0_SHIFT:MECR_SOCKET_1_SHIFT)))
69
70 #define MECR_GET(mecr, sock, shift, mask) \
71 ((((mecr)>>(((sock)==0)?MECR_SOCKET_0_SHIFT:MECR_SOCKET_1_SHIFT))>>\
72 (shift))&(mask))
73
74 #define MECR_BSIO_SET(mecr, sock, bs) \
75 MECR_SET((mecr), (sock), MECR_BSIO_SHIFT, MECR_BS_MASK, (bs))
76
77 #define MECR_BSIO_GET(mecr, sock) \
78 MECR_GET((mecr), (sock), MECR_BSIO_SHIFT, MECR_BS_MASK)
79
80 #define MECR_BSA_SET(mecr, sock, bs) \
81 MECR_SET((mecr), (sock), MECR_BSA_SHIFT, MECR_BS_MASK, (bs))
82
83 #define MECR_BSA_GET(mecr, sock) \
84 MECR_GET((mecr), (sock), MECR_BSA_SHIFT, MECR_BS_MASK)
85
86 #define MECR_BSM_SET(mecr, sock, bs) \
87 MECR_SET((mecr), (sock), MECR_BSM_SHIFT, MECR_BS_MASK, (bs))
88
89 #define MECR_BSM_GET(mecr, sock) \
90 MECR_GET((mecr), (sock), MECR_BSM_SHIFT, MECR_BS_MASK)
91
92 #define MECR_FAST_SET(mecr, sock, fast) \
93 MECR_SET((mecr), (sock), MECR_FAST_SHIFT, MECR_FAST_MODE_MASK, (fast))
94
95 #define MECR_FAST_GET(mecr, sock) \
96 MECR_GET((mecr), (sock), MECR_FAST_SHIFT, MECR_FAST_MODE_MASK)
97
98
99 /* This function implements the BS value calculation for setting the MECR
100 * using integer arithmetic:
101 */
sa1100_pcmcia_mecr_bs(unsigned int pcmcia_cycle_ns,unsigned int cpu_clock_khz)102 static inline unsigned int sa1100_pcmcia_mecr_bs(unsigned int pcmcia_cycle_ns,
103 unsigned int cpu_clock_khz){
104 unsigned int t = ((pcmcia_cycle_ns * cpu_clock_khz) / 6) - 1000000;
105 return (t / 1000000) + (((t % 1000000) == 0) ? 0 : 1);
106 }
107
108 /* This function returns the (approxmiate) command assertion period, in
109 * nanoseconds, for a given CPU clock frequency and MECR BS value:
110 */
sa1100_pcmcia_cmd_time(unsigned int cpu_clock_khz,unsigned int pcmcia_mecr_bs)111 static inline unsigned int sa1100_pcmcia_cmd_time(unsigned int cpu_clock_khz,
112 unsigned int pcmcia_mecr_bs){
113 return (((10000000 * 2) / cpu_clock_khz) * (3 * (pcmcia_mecr_bs + 1))) / 10;
114 }
115
116
117 /* SA-1100 PCMCIA Memory and I/O timing
118 * ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
119 * The SA-1110 Developer's Manual, section 10.2.5, says the following:
120 *
121 * "To calculate the recommended BS_xx value for each address space:
122 * divide the command width time (the greater of twIOWR and twIORD,
123 * or the greater of twWE and twOE) by processor cycle time; divide
124 * by 2; divide again by 3 (number of BCLK's per command assertion);
125 * round up to the next whole number; and subtract 1."
126 *
127 * The PC Card Standard, Release 7, section 4.13.4, says that twIORD
128 * has a minimum value of 165ns. Section 4.13.5 says that twIOWR has
129 * a minimum value of 165ns, as well. Section 4.7.2 (describing
130 * common and attribute memory write timing) says that twWE has a
131 * minimum value of 150ns for a 250ns cycle time (for 5V operation;
132 * see section 4.7.4), or 300ns for a 600ns cycle time (for 3.3V
133 * operation, also section 4.7.4). Section 4.7.3 says that taOE
134 * has a maximum value of 150ns for a 300ns cycle time (for 5V
135 * operation), or 300ns for a 600ns cycle time (for 3.3V operation).
136 *
137 * When configuring memory maps, Card Services appears to adopt the policy
138 * that a memory access time of "0" means "use the default." The default
139 * PCMCIA I/O command width time is 165ns. The default PCMCIA 5V attribute
140 * and memory command width time is 150ns; the PCMCIA 3.3V attribute and
141 * memory command width time is 300ns.
142 */
143 #define SA1100_PCMCIA_IO_ACCESS (165)
144 #define SA1100_PCMCIA_5V_MEM_ACCESS (150)
145 #define SA1100_PCMCIA_3V_MEM_ACCESS (300)
146
147
148 /* The socket driver actually works nicely in interrupt-driven form,
149 * so the (relatively infrequent) polling is "just to be sure."
150 */
151 #define SA1100_PCMCIA_POLL_PERIOD (2*HZ)
152
153
154 /* This structure encapsulates per-socket state which we might need to
155 * use when responding to a Card Services query of some kind.
156 */
157 struct sa1100_pcmcia_socket {
158 /*
159 * Core PCMCIA state
160 */
161 socket_state_t cs_state;
162 pccard_io_map io_map[MAX_IO_WIN];
163 pccard_mem_map mem_map[MAX_WIN];
164 void (*handler)(void *, unsigned int);
165 void *handler_info;
166
167 struct pcmcia_state k_state;
168 ioaddr_t phys_attr, phys_mem;
169 void *virt_io;
170 unsigned short speed_io, speed_attr, speed_mem;
171
172 /*
173 * Info from low level handler
174 */
175 unsigned int irq;
176 };
177
178
179 /* I/O pins replacing memory pins
180 * (PCMCIA System Architecture, 2nd ed., by Don Anderson, p.75)
181 *
182 * These signals change meaning when going from memory-only to
183 * memory-or-I/O interface:
184 */
185 #define iostschg bvd1
186 #define iospkr bvd2
187
188
189 /*
190 * Declaration for all implementation specific low_level operations.
191 */
192 extern struct pcmcia_low_level assabet_pcmcia_ops;
193 extern struct pcmcia_low_level neponset_pcmcia_ops;
194 extern struct pcmcia_low_level h3600_pcmcia_ops;
195 extern struct pcmcia_low_level cerf_pcmcia_ops;
196 extern struct pcmcia_low_level gcplus_pcmcia_ops;
197 extern struct pcmcia_low_level xp860_pcmcia_ops;
198 extern struct pcmcia_low_level yopy_pcmcia_ops;
199 extern struct pcmcia_low_level shannon_pcmcia_ops;
200 extern struct pcmcia_low_level pangolin_pcmcia_ops;
201 extern struct pcmcia_low_level freebird_pcmcia_ops;
202 extern struct pcmcia_low_level pfs168_pcmcia_ops;
203 extern struct pcmcia_low_level jornada720_pcmcia_ops;
204 extern struct pcmcia_low_level flexanet_pcmcia_ops;
205 extern struct pcmcia_low_level simpad_pcmcia_ops;
206 extern struct pcmcia_low_level graphicsmaster_pcmcia_ops;
207 extern struct pcmcia_low_level adsbitsy_pcmcia_ops;
208 extern struct pcmcia_low_level stork_pcmcia_ops;
209 extern struct pcmcia_low_level badge4_pcmcia_ops;
210
211 #endif /* !defined(_PCMCIA_SA1100_H) */
212