1 /*
2 *
3 * Copyright (C) 2002 Intersil Americas Inc.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 *
18 */
19
20 #ifndef _ISL_38XX_H
21 #define _ISL_38XX_H
22
23 #include <linux/version.h>
24 #include <asm/io.h>
25 #include <asm/byteorder.h>
26
27 #define ISL38XX_CB_RX_QSIZE 8
28 #define ISL38XX_CB_TX_QSIZE 32
29
30 /* ISL38XX Access Point Specific definitions */
31 #define ISL38XX_MAX_WDS_LINKS 8
32
33 /* ISL38xx Client Specific definitions */
34 #define ISL38XX_PSM_ACTIVE_STATE 0
35 #define ISL38XX_PSM_POWERSAVE_STATE 1
36
37 /* ISL38XX Host Interface Definitions */
38 #define ISL38XX_PCI_MEM_SIZE 0x02000
39 #define ISL38XX_MEMORY_WINDOW_SIZE 0x01000
40 #define ISL38XX_DEV_FIRMWARE_ADDRES 0x20000
41 #define ISL38XX_WRITEIO_DELAY 10 /* in us */
42 #define ISL38XX_RESET_DELAY 50 /* in ms */
43 #define ISL38XX_WAIT_CYCLE 10 /* in 10ms */
44 #define ISL38XX_MAX_WAIT_CYCLES 10
45
46 /* PCI Memory Area */
47 #define ISL38XX_HARDWARE_REG 0x0000
48 #define ISL38XX_CARDBUS_CIS 0x0800
49 #define ISL38XX_DIRECT_MEM_WIN 0x1000
50
51 /* Hardware registers */
52 #define ISL38XX_DEV_INT_REG 0x0000
53 #define ISL38XX_INT_IDENT_REG 0x0010
54 #define ISL38XX_INT_ACK_REG 0x0014
55 #define ISL38XX_INT_EN_REG 0x0018
56 #define ISL38XX_GEN_PURP_COM_REG_1 0x0020
57 #define ISL38XX_GEN_PURP_COM_REG_2 0x0024
58 #define ISL38XX_CTRL_BLK_BASE_REG ISL38XX_GEN_PURP_COM_REG_1
59 #define ISL38XX_DIR_MEM_BASE_REG 0x0030
60 #define ISL38XX_CTRL_STAT_REG 0x0078
61
62 /* High end mobos queue up pci writes, the following
63 * is used to "read" from after a write to force flush */
64 #define ISL38XX_PCI_POSTING_FLUSH ISL38XX_INT_EN_REG
65
66 /**
67 * isl38xx_w32_flush - PCI iomem write helper
68 * @base: (host) memory base address of the device
69 * @val: 32bit value (host order) to write
70 * @offset: byte offset into @base to write value to
71 *
72 * This helper takes care of writing a 32bit datum to the
73 * specified offset into the device's pci memory space, and making sure
74 * the pci memory buffers get flushed by performing one harmless read
75 * from the %ISL38XX_PCI_POSTING_FLUSH offset.
76 */
77 static inline void
isl38xx_w32_flush(void __iomem * base,u32 val,unsigned long offset)78 isl38xx_w32_flush(void __iomem *base, u32 val, unsigned long offset)
79 {
80 writel(val, base + offset);
81 (void) readl(base + ISL38XX_PCI_POSTING_FLUSH);
82 }
83
84 /* Device Interrupt register bits */
85 #define ISL38XX_DEV_INT_RESET 0x0001
86 #define ISL38XX_DEV_INT_UPDATE 0x0002
87 #define ISL38XX_DEV_INT_WAKEUP 0x0008
88 #define ISL38XX_DEV_INT_SLEEP 0x0010
89
90 /* Interrupt Identification/Acknowledge/Enable register bits */
91 #define ISL38XX_INT_IDENT_UPDATE 0x0002
92 #define ISL38XX_INT_IDENT_INIT 0x0004
93 #define ISL38XX_INT_IDENT_WAKEUP 0x0008
94 #define ISL38XX_INT_IDENT_SLEEP 0x0010
95 #define ISL38XX_INT_SOURCES 0x001E
96
97 /* Control/Status register bits */
98 /* Looks like there are other meaningful bits
99 0x20004400 seen in normal operation,
100 0x200044db at 'timeout waiting for mgmt response'
101 */
102 #define ISL38XX_CTRL_STAT_SLEEPMODE 0x00000200
103 #define ISL38XX_CTRL_STAT_CLKRUN 0x00800000
104 #define ISL38XX_CTRL_STAT_RESET 0x10000000
105 #define ISL38XX_CTRL_STAT_RAMBOOT 0x20000000
106 #define ISL38XX_CTRL_STAT_STARTHALTED 0x40000000
107 #define ISL38XX_CTRL_STAT_HOST_OVERRIDE 0x80000000
108
109 /* Control Block definitions */
110 #define ISL38XX_CB_RX_DATA_LQ 0
111 #define ISL38XX_CB_TX_DATA_LQ 1
112 #define ISL38XX_CB_RX_DATA_HQ 2
113 #define ISL38XX_CB_TX_DATA_HQ 3
114 #define ISL38XX_CB_RX_MGMTQ 4
115 #define ISL38XX_CB_TX_MGMTQ 5
116 #define ISL38XX_CB_QCOUNT 6
117 #define ISL38XX_CB_MGMT_QSIZE 4
118 #define ISL38XX_MIN_QTHRESHOLD 4 /* fragments */
119
120 /* Memory Manager definitions */
121 #define MGMT_FRAME_SIZE 1500 /* >= size struct obj_bsslist */
122 #define MGMT_TX_FRAME_COUNT 24 /* max 4 + spare 4 + 8 init */
123 #define MGMT_RX_FRAME_COUNT 24 /* 4*4 + spare 8 */
124 #define MGMT_FRAME_COUNT (MGMT_TX_FRAME_COUNT + MGMT_RX_FRAME_COUNT)
125 #define CONTROL_BLOCK_SIZE 1024 /* should be enough */
126 #define PSM_FRAME_SIZE 1536
127 #define PSM_MINIMAL_STATION_COUNT 64
128 #define PSM_FRAME_COUNT PSM_MINIMAL_STATION_COUNT
129 #define PSM_BUFFER_SIZE PSM_FRAME_SIZE * PSM_FRAME_COUNT
130 #define MAX_TRAP_RX_QUEUE 4
131 #define HOST_MEM_BLOCK CONTROL_BLOCK_SIZE + PSM_BUFFER_SIZE
132
133 /* Fragment package definitions */
134 #define FRAGMENT_FLAG_MF 0x0001
135 #define MAX_FRAGMENT_SIZE 1536
136
137 /* In monitor mode frames have a header. I don't know exactly how big those
138 * frame can be but I've never seen any frame bigger than 1584... :
139 */
140 #define MAX_FRAGMENT_SIZE_RX 1600
141
142 typedef struct {
143 u32 address; /* physical address on host */
144 u16 size; /* packet size */
145 u16 flags; /* set of bit-wise flags */
146 } isl38xx_fragment;
147
148 struct isl38xx_cb {
149 u32 driver_curr_frag[ISL38XX_CB_QCOUNT];
150 u32 device_curr_frag[ISL38XX_CB_QCOUNT];
151 isl38xx_fragment rx_data_low[ISL38XX_CB_RX_QSIZE];
152 isl38xx_fragment tx_data_low[ISL38XX_CB_TX_QSIZE];
153 isl38xx_fragment rx_data_high[ISL38XX_CB_RX_QSIZE];
154 isl38xx_fragment tx_data_high[ISL38XX_CB_TX_QSIZE];
155 isl38xx_fragment rx_data_mgmt[ISL38XX_CB_MGMT_QSIZE];
156 isl38xx_fragment tx_data_mgmt[ISL38XX_CB_MGMT_QSIZE];
157 };
158
159 typedef struct isl38xx_cb isl38xx_control_block;
160
161 /* determine number of entries currently in queue */
162 int isl38xx_in_queue(isl38xx_control_block *cb, int queue);
163
164 void isl38xx_disable_interrupts(void __iomem *);
165 void isl38xx_enable_common_interrupts(void __iomem *);
166
167 void isl38xx_handle_sleep_request(isl38xx_control_block *, int *,
168 void __iomem *);
169 void isl38xx_handle_wakeup(isl38xx_control_block *, int *, void __iomem *);
170 void isl38xx_trigger_device(int, void __iomem *);
171 void isl38xx_interface_reset(void __iomem *, dma_addr_t);
172
173 #endif /* _ISL_38XX_H */
174