1 /******************************************************************************
2 *
3 * (C)Copyright 1998,1999 SysKonnect,
4 * a business unit of Schneider & Koch & Co. Datensysteme GmbH.
5 *
6 * See the file "skfddi.c" for further information.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * The information in this file is provided "AS IS" without warranty.
14 *
15 ******************************************************************************/
16
17 #ifndef lint
18 static char const ID_sccs[] = "@(#)hwmtm.c 1.40 99/05/31 (C) SK" ;
19 #endif
20
21 #define HWMTM
22
23 #ifndef FDDI
24 #define FDDI
25 #endif
26
27 #include "h/types.h"
28 #include "h/fddi.h"
29 #include "h/smc.h"
30 #include "h/supern_2.h"
31 #include "h/skfbiinc.h"
32
33 /*
34 -------------------------------------------------------------
35 DOCUMENTATION
36 -------------------------------------------------------------
37 BEGIN_MANUAL_ENTRY(DOCUMENTATION)
38
39 T B D
40
41 END_MANUAL_ENTRY
42 */
43 /*
44 -------------------------------------------------------------
45 LOCAL VARIABLES:
46 -------------------------------------------------------------
47 */
48 #ifdef COMMON_MB_POOL
49 static SMbuf *mb_start = 0 ;
50 static SMbuf *mb_free = 0 ;
51 static int mb_init = FALSE ;
52 static int call_count = 0 ;
53 #endif
54
55 /*
56 -------------------------------------------------------------
57 EXTERNE VARIABLES:
58 -------------------------------------------------------------
59 */
60
61 #ifdef DEBUG
62 #ifndef DEBUG_BRD
63 extern struct smt_debug debug ;
64 #endif
65 #endif
66
67 #ifdef NDIS_OS2
68 extern u_char offDepth ;
69 extern u_char force_irq_pending ;
70 #endif
71
72 /*
73 -------------------------------------------------------------
74 LOCAL FUNCTIONS:
75 -------------------------------------------------------------
76 */
77
78 static void queue_llc_rx(), smt_to_llc(),
79 init_txd_ring(), init_rxd_ring(),
80 queue_txd_mb() ;
81
82 static u_long init_descr_ring(), repair_txd_ring(),
83 repair_rxd_ring() ;
84
85 static SMbuf *get_llc_rx(), *get_txd_mb() ;
86
87
88 /*
89 -------------------------------------------------------------
90 EXTERNAL FUNCTIONS:
91 -------------------------------------------------------------
92 */
93 /* The external SMT functions are listed in cmtdef.h */
94
95 extern void *mac_drv_get_space(), *mac_drv_get_desc_mem(),
96 init_board(), mac_drv_fill_rxd(),
97 plc1_irq(), mac_drv_tx_complete(),
98 plc2_irq(), mac1_irq(),
99 mac2_irq(), mac3_irq(),
100 timer_irq(), mac_drv_rx_complete(),
101 mac_drv_requeue_rxd(), init_plc(),
102 mac_drv_clear_rxd(), llc_restart_tx(),
103 ev_dispatcher(), smt_force_irq() ;
104
105 #ifdef USE_OS_CPY
106 extern void hwm_cpy_rxd2mb(), hwm_cpy_txd2mb() ;
107 #endif
108 #ifdef ALL_RX_COMPLETE
109 extern void mac_drv_all_receives_complete() ;
110 #endif
111
112 extern u_long mac_drv_virt2phys(), dma_master() ;
113
114 #ifdef NDIS_OS2
115 extern void post_proc() ;
116 #else
117 extern void dma_complete() ;
118 #endif
119
120 extern int init_fplus(), mac_drv_rx_init() ;
121
122 /*
123 -------------------------------------------------------------
124 PUBLIC FUNCTIONS:
125 -------------------------------------------------------------
126 */
127 void process_receive(), smt_send_mbuf(),
128 fddi_isr(), mac_drv_clear_txd(),
129 smt_free_mbuf(), init_driver_fplus(),
130 mac_drv_rx_mode(), init_fddi_driver(),
131 mac_drv_clear_tx_queue(),
132 mac_drv_clear_rx_queue(),
133 hwm_tx_frag(), hwm_rx_frag() ;
134
135 int mac_drv_rx_frag(), mac_drv_init(),
136 hwm_tx_init() ;
137
138 u_int mac_drv_check_space() ;
139
140 SMbuf *smt_get_mbuf() ;
141
142 #ifdef DEBUG
143 void mac_drv_debug_lev() ;
144 #endif
145
146 /*
147 -------------------------------------------------------------
148 MACROS:
149 -------------------------------------------------------------
150 */
151 #ifndef UNUSED
152 #ifdef lint
153 #define UNUSED(x) (x) = (x)
154 #else
155 #define UNUSED(x)
156 #endif
157 #endif
158
159 #ifdef USE_CAN_ADDR
160 #define MA smc->hw.fddi_canon_addr.a
161 #define GROUP_ADDR_BIT 0x01
162 #else
163 #define MA smc->hw.fddi_home_addr.a
164 #define GROUP_ADDR_BIT 0x80
165 #endif
166
167 #define RXD_TXD_COUNT (HWM_ASYNC_TXD_COUNT+HWM_SYNC_TXD_COUNT+\
168 SMT_R1_RXD_COUNT+SMT_R2_RXD_COUNT)
169
170 #ifdef MB_OUTSIDE_SMC
171 #define EXT_VIRT_MEM ((RXD_TXD_COUNT+1)*sizeof(struct s_smt_fp_txd) +\
172 MAX_MBUF*sizeof(SMbuf))
173 #define EXT_VIRT_MEM_2 ((RXD_TXD_COUNT+1)*sizeof(struct s_smt_fp_txd))
174 #else
175 #define EXT_VIRT_MEM ((RXD_TXD_COUNT+1)*sizeof(struct s_smt_fp_txd))
176 #endif
177
178 /*
179 * define critical read for 16 Bit drivers
180 */
181 #if defined(NDIS_OS2) || defined(ODI2)
182 #define CR_READ(var) ((var) & 0xffff0000 | ((var) & 0xffff))
183 #else
184 #define CR_READ(var) (u_long)(var)
185 #endif
186
187 #define IMASK_SLOW (IS_PLINT1 | IS_PLINT2 | IS_TIMINT | IS_TOKEN | \
188 IS_MINTR1 | IS_MINTR2 | IS_MINTR3 | IS_R1_P | \
189 IS_R1_C | IS_XA_C | IS_XS_C)
190
191 /*
192 -------------------------------------------------------------
193 INIT- AND SMT FUNCTIONS:
194 -------------------------------------------------------------
195 */
196
197
198 /*
199 * BEGIN_MANUAL_ENTRY(mac_drv_check_space)
200 * u_int mac_drv_check_space()
201 *
202 * function DOWNCALL (drvsr.c)
203 * This function calculates the needed non virtual
204 * memory for MBufs, RxD and TxD descriptors etc.
205 * needed by the driver.
206 *
207 * return u_int memory in bytes
208 *
209 * END_MANUAL_ENTRY
210 */
mac_drv_check_space()211 u_int mac_drv_check_space()
212 {
213 #ifdef MB_OUTSIDE_SMC
214 #ifdef COMMON_MB_POOL
215 call_count++ ;
216 if (call_count == 1) {
217 return(EXT_VIRT_MEM) ;
218 }
219 else {
220 return(EXT_VIRT_MEM_2) ;
221 }
222 #else
223 return (EXT_VIRT_MEM) ;
224 #endif
225 #else
226 return (0) ;
227 #endif
228 }
229
230 /*
231 * BEGIN_MANUAL_ENTRY(mac_drv_init)
232 * void mac_drv_init(smc)
233 *
234 * function DOWNCALL (drvsr.c)
235 * In this function the hardware module allocates it's
236 * memory.
237 * The operating system dependent module should call
238 * mac_drv_init once, after the adatper is detected.
239 * END_MANUAL_ENTRY
240 */
mac_drv_init(smc)241 int mac_drv_init(smc)
242 struct s_smc *smc ;
243 {
244 if (sizeof(struct s_smt_fp_rxd) % 16) {
245 SMT_PANIC(smc,HWM_E0001,HWM_E0001_MSG) ;
246 }
247 if (sizeof(struct s_smt_fp_txd) % 16) {
248 SMT_PANIC(smc,HWM_E0002,HWM_E0002_MSG) ;
249 }
250
251 /*
252 * get the required memory for the RxDs and TxDs
253 */
254 if (!(smc->os.hwm.descr_p = (union s_fp_descr volatile *)
255 mac_drv_get_desc_mem(smc,(u_int)
256 (RXD_TXD_COUNT+1)*sizeof(struct s_smt_fp_txd)))) {
257 return(1) ; /* no space the hwm modul can't work */
258 }
259
260 /*
261 * get the memory for the SMT MBufs
262 */
263 #ifndef MB_OUTSIDE_SMC
264 smc->os.hwm.mbuf_pool.mb_start=(SMbuf *)(&smc->os.hwm.mbuf_pool.mb[0]) ;
265 #else
266 #ifndef COMMON_MB_POOL
267 if (!(smc->os.hwm.mbuf_pool.mb_start = (SMbuf *) mac_drv_get_space(smc,
268 MAX_MBUF*sizeof(SMbuf)))) {
269 return(1) ; /* no space the hwm modul can't work */
270 }
271 #else
272 if (!mb_start) {
273 if (!(mb_start = (SMbuf *) mac_drv_get_space(smc,
274 MAX_MBUF*sizeof(SMbuf)))) {
275 return(1) ; /* no space the hwm modul can't work */
276 }
277 }
278 #endif
279 #endif
280 return (0) ;
281 }
282
283 /*
284 * BEGIN_MANUAL_ENTRY(init_driver_fplus)
285 * init_driver_fplus(smc)
286 *
287 * Sets hardware modul specific values for the mode register 2
288 * (e.g. the byte alignment for the received frames, the position of the
289 * least significant byte etc.)
290 * END_MANUAL_ENTRY
291 */
init_driver_fplus(smc)292 void init_driver_fplus(smc)
293 struct s_smc *smc ;
294 {
295 smc->hw.fp.mdr2init = FM_LSB | FM_BMMODE | FM_ENNPRQ | FM_ENHSRQ | 3 ;
296
297 #ifdef PCI
298 smc->hw.fp.mdr2init |= FM_CHKPAR | FM_PARITY ;
299 #endif
300 smc->hw.fp.mdr3init = FM_MENRQAUNLCK | FM_MENRS ;
301
302 #ifdef USE_CAN_ADDR
303 /* enable address bit swapping */
304 smc->hw.fp.frselreg_init = FM_ENXMTADSWAP | FM_ENRCVADSWAP ;
305 #endif
306 }
307
init_descr_ring(smc,start,count)308 static u_long init_descr_ring(smc,start,count)
309 struct s_smc *smc ;
310 union s_fp_descr volatile *start;
311 int count ;
312 {
313 int i ;
314 union s_fp_descr volatile *d1 ;
315 union s_fp_descr volatile *d2 ;
316 u_long phys ;
317
318 DB_GEN("descr ring starts at = %x ",(void *)start,0,3) ;
319 for (i=count-1, d1=start; i ; i--) {
320 d2 = d1 ;
321 d1++ ; /* descr is owned by the host */
322 d2->r.rxd_rbctrl = AIX_REVERSE(BMU_CHECK) ;
323 d2->r.rxd_next = &d1->r ;
324 phys = mac_drv_virt2phys(smc,(void *)d1) ;
325 d2->r.rxd_nrdadr = AIX_REVERSE(phys) ;
326 }
327 DB_GEN("descr ring ends at = %x ",(void *)d1,0,3) ;
328 d1->r.rxd_rbctrl = AIX_REVERSE(BMU_CHECK) ;
329 d1->r.rxd_next = &start->r ;
330 phys = mac_drv_virt2phys(smc,(void *)start) ;
331 d1->r.rxd_nrdadr = AIX_REVERSE(phys) ;
332
333 for (i=count, d1=start; i ; i--) {
334 DRV_BUF_FLUSH(&d1->r,DDI_DMA_SYNC_FORDEV) ;
335 d1++;
336 }
337 return(phys) ;
338 }
339
init_txd_ring(smc)340 static void init_txd_ring(smc)
341 struct s_smc *smc ;
342 {
343 struct s_smt_fp_txd volatile *ds ;
344 struct s_smt_tx_queue *queue ;
345 u_long phys ;
346
347 /*
348 * initialize the transmit descriptors
349 */
350 ds = (struct s_smt_fp_txd volatile *) ((char *)smc->os.hwm.descr_p +
351 SMT_R1_RXD_COUNT*sizeof(struct s_smt_fp_rxd)) ;
352 queue = smc->hw.fp.tx[QUEUE_A0] ;
353 DB_GEN("Init async TxD ring, %d TxDs ",HWM_ASYNC_TXD_COUNT,0,3) ;
354 (void)init_descr_ring(smc,(union s_fp_descr volatile *)ds,
355 HWM_ASYNC_TXD_COUNT) ;
356 phys = AIX_REVERSE(ds->txd_ntdadr) ;
357 ds++ ;
358 queue->tx_curr_put = queue->tx_curr_get = ds ;
359 ds-- ;
360 queue->tx_free = HWM_ASYNC_TXD_COUNT ;
361 queue->tx_used = 0 ;
362 outpd(ADDR(B5_XA_DA),phys) ;
363
364 ds = (struct s_smt_fp_txd volatile *) ((char *)ds +
365 HWM_ASYNC_TXD_COUNT*sizeof(struct s_smt_fp_txd)) ;
366 queue = smc->hw.fp.tx[QUEUE_S] ;
367 DB_GEN("Init sync TxD ring, %d TxDs ",HWM_SYNC_TXD_COUNT,0,3) ;
368 (void)init_descr_ring(smc,(union s_fp_descr volatile *)ds,
369 HWM_SYNC_TXD_COUNT) ;
370 phys = AIX_REVERSE(ds->txd_ntdadr) ;
371 ds++ ;
372 queue->tx_curr_put = queue->tx_curr_get = ds ;
373 queue->tx_free = HWM_SYNC_TXD_COUNT ;
374 queue->tx_used = 0 ;
375 outpd(ADDR(B5_XS_DA),phys) ;
376 }
377
init_rxd_ring(smc)378 static void init_rxd_ring(smc)
379 struct s_smc *smc ;
380 {
381 struct s_smt_fp_rxd volatile *ds ;
382 struct s_smt_rx_queue *queue ;
383 u_long phys ;
384
385 /*
386 * initialize the receive descriptors
387 */
388 ds = (struct s_smt_fp_rxd volatile *) smc->os.hwm.descr_p ;
389 queue = smc->hw.fp.rx[QUEUE_R1] ;
390 DB_GEN("Init RxD ring, %d RxDs ",SMT_R1_RXD_COUNT,0,3) ;
391 (void)init_descr_ring(smc,(union s_fp_descr volatile *)ds,
392 SMT_R1_RXD_COUNT) ;
393 phys = AIX_REVERSE(ds->rxd_nrdadr) ;
394 ds++ ;
395 queue->rx_curr_put = queue->rx_curr_get = ds ;
396 queue->rx_free = SMT_R1_RXD_COUNT ;
397 queue->rx_used = 0 ;
398 outpd(ADDR(B4_R1_DA),phys) ;
399 }
400
401 /*
402 * BEGIN_MANUAL_ENTRY(init_fddi_driver)
403 * void init_fddi_driver(smc,mac_addr)
404 *
405 * initializes the driver and it's variables
406 *
407 * END_MANUAL_ENTRY
408 */
init_fddi_driver(smc,mac_addr)409 void init_fddi_driver(smc,mac_addr)
410 struct s_smc *smc ;
411 u_char *mac_addr ; /* canonical address */
412 {
413 SMbuf *mb ;
414 int i ;
415
416 init_board(smc,mac_addr) ;
417 (void)init_fplus(smc) ;
418
419 /*
420 * initialize the SMbufs for the SMT
421 */
422 #ifndef COMMON_MB_POOL
423 mb = smc->os.hwm.mbuf_pool.mb_start ;
424 smc->os.hwm.mbuf_pool.mb_free = (SMbuf *)NULL ;
425 for (i = 0; i < MAX_MBUF; i++) {
426 mb->sm_use_count = 1 ;
427 smt_free_mbuf(smc,mb) ;
428 mb++ ;
429 }
430 #else
431 mb = mb_start ;
432 if (!mb_init) {
433 mb_free = 0 ;
434 for (i = 0; i < MAX_MBUF; i++) {
435 mb->sm_use_count = 1 ;
436 smt_free_mbuf(smc,mb) ;
437 mb++ ;
438 }
439 mb_init = TRUE ;
440 }
441 #endif
442
443 /*
444 * initialize the other variables
445 */
446 smc->os.hwm.llc_rx_pipe = smc->os.hwm.llc_rx_tail = (SMbuf *)NULL ;
447 smc->os.hwm.txd_tx_pipe = smc->os.hwm.txd_tx_tail = NULL ;
448 smc->os.hwm.pass_SMT = smc->os.hwm.pass_NSA = smc->os.hwm.pass_DB = 0 ;
449 smc->os.hwm.pass_llc_promisc = TRUE ;
450 smc->os.hwm.queued_rx_frames = smc->os.hwm.queued_txd_mb = 0 ;
451 smc->os.hwm.detec_count = 0 ;
452 smc->os.hwm.rx_break = 0 ;
453 smc->os.hwm.rx_len_error = 0 ;
454 smc->os.hwm.isr_flag = FALSE ;
455
456 /*
457 * make sure that the start pointer is 16 byte aligned
458 */
459 i = 16 - ((long)smc->os.hwm.descr_p & 0xf) ;
460 if (i != 16) {
461 DB_GEN("i = %d",i,0,3) ;
462 smc->os.hwm.descr_p = (union s_fp_descr volatile *)
463 ((char *)smc->os.hwm.descr_p+i) ;
464 }
465 DB_GEN("pt to descr area = %x",(void *)smc->os.hwm.descr_p,0,3) ;
466
467 init_txd_ring(smc) ;
468 init_rxd_ring(smc) ;
469 mac_drv_fill_rxd(smc) ;
470
471 init_plc(smc) ;
472 }
473
474
smt_get_mbuf(smc)475 SMbuf *smt_get_mbuf(smc)
476 struct s_smc *smc ;
477 {
478 register SMbuf *mb ;
479
480 #ifndef COMMON_MB_POOL
481 mb = smc->os.hwm.mbuf_pool.mb_free ;
482 #else
483 mb = mb_free ;
484 #endif
485 if (mb) {
486 #ifndef COMMON_MB_POOL
487 smc->os.hwm.mbuf_pool.mb_free = mb->sm_next ;
488 #else
489 mb_free = mb->sm_next ;
490 #endif
491 mb->sm_off = 8 ;
492 mb->sm_use_count = 1 ;
493 }
494 DB_GEN("get SMbuf: mb = %x",(void *)mb,0,3) ;
495 return (mb) ; /* May be NULL */
496 }
497
smt_free_mbuf(smc,mb)498 void smt_free_mbuf(smc, mb)
499 struct s_smc *smc ;
500 SMbuf *mb;
501 {
502
503 if (mb) {
504 mb->sm_use_count-- ;
505 DB_GEN("free_mbuf: sm_use_count = %d",mb->sm_use_count,0,3) ;
506 /*
507 * If the use_count is != zero the MBuf is queued
508 * more than once and must not queued into the
509 * free MBuf queue
510 */
511 if (!mb->sm_use_count) {
512 DB_GEN("free SMbuf: mb = %x",(void *)mb,0,3) ;
513 #ifndef COMMON_MB_POOL
514 mb->sm_next = smc->os.hwm.mbuf_pool.mb_free ;
515 smc->os.hwm.mbuf_pool.mb_free = mb ;
516 #else
517 mb->sm_next = mb_free ;
518 mb_free = mb ;
519 #endif
520 }
521 }
522 else
523 SMT_PANIC(smc,HWM_E0003,HWM_E0003_MSG) ;
524 }
525
526
527 /*
528 * BEGIN_MANUAL_ENTRY(mac_drv_repair_descr)
529 * void mac_drv_repair_descr(smc)
530 *
531 * function called from SMT (HWM / hwmtm.c)
532 * The BMU is idle when this function is called.
533 * Mac_drv_repair_descr sets up the physical address
534 * for all receive and transmit queues where the BMU
535 * should continue.
536 * It may be that the BMU was reseted during a fragmented
537 * transfer. In this case there are some fragments which will
538 * never completed by the BMU. The OWN bit of this fragments
539 * must be switched to be owned by the host.
540 *
541 * Give a start command to the receive BMU.
542 * Start the transmit BMUs if transmit frames pending.
543 *
544 * END_MANUAL_ENTRY
545 */
mac_drv_repair_descr(smc)546 void mac_drv_repair_descr(smc)
547 struct s_smc *smc ;
548 {
549 u_long phys ;
550
551 if (smc->hw.hw_state != STOPPED) {
552 SK_BREAK() ;
553 SMT_PANIC(smc,HWM_E0013,HWM_E0013_MSG) ;
554 return ;
555 }
556
557 /*
558 * repair tx queues: don't start
559 */
560 phys = repair_txd_ring(smc,smc->hw.fp.tx[QUEUE_A0]) ;
561 outpd(ADDR(B5_XA_DA),phys) ;
562 if (smc->hw.fp.tx_q[QUEUE_A0].tx_used) {
563 outpd(ADDR(B0_XA_CSR),CSR_START) ;
564 }
565 phys = repair_txd_ring(smc,smc->hw.fp.tx[QUEUE_S]) ;
566 outpd(ADDR(B5_XS_DA),phys) ;
567 if (smc->hw.fp.tx_q[QUEUE_S].tx_used) {
568 outpd(ADDR(B0_XS_CSR),CSR_START) ;
569 }
570
571 /*
572 * repair rx queues
573 */
574 phys = repair_rxd_ring(smc,smc->hw.fp.rx[QUEUE_R1]) ;
575 outpd(ADDR(B4_R1_DA),phys) ;
576 outpd(ADDR(B0_R1_CSR),CSR_START) ;
577 }
578
repair_txd_ring(smc,queue)579 static u_long repair_txd_ring(smc,queue)
580 struct s_smc *smc ;
581 struct s_smt_tx_queue *queue ;
582 {
583 int i ;
584 int tx_used ;
585 u_long phys ;
586 u_long tbctrl ;
587 struct s_smt_fp_txd volatile *t ;
588
589 SK_UNUSED(smc) ;
590
591 t = queue->tx_curr_get ;
592 tx_used = queue->tx_used ;
593 for (i = tx_used+queue->tx_free-1 ; i ; i-- ) {
594 t = t->txd_next ;
595 }
596 phys = AIX_REVERSE(t->txd_ntdadr) ;
597
598 t = queue->tx_curr_get ;
599 while (tx_used) {
600 DRV_BUF_FLUSH(t,DDI_DMA_SYNC_FORCPU) ;
601 tbctrl = AIX_REVERSE(t->txd_tbctrl) ;
602
603 if (tbctrl & BMU_OWN) {
604 if (tbctrl & BMU_STF) {
605 break ; /* exit the loop */
606 }
607 else {
608 /*
609 * repair the descriptor
610 */
611 t->txd_tbctrl &= AIX_REVERSE(~BMU_OWN) ;
612 }
613 }
614 phys = AIX_REVERSE(t->txd_ntdadr) ;
615 DRV_BUF_FLUSH(t,DDI_DMA_SYNC_FORDEV) ;
616 t = t->txd_next ;
617 tx_used-- ;
618 }
619 return(phys) ;
620 }
621
622 /*
623 * Repairs the receive descriptor ring and returns the physical address
624 * where the BMU should continue working.
625 *
626 * o The physical address where the BMU was stopped has to be
627 * determined. This is the next RxD after rx_curr_get with an OWN
628 * bit set.
629 * o The BMU should start working at beginning of the next frame.
630 * RxDs with an OWN bit set but with a reset STF bit should be
631 * skipped and owned by the driver (OWN = 0).
632 */
repair_rxd_ring(smc,queue)633 static u_long repair_rxd_ring(smc,queue)
634 struct s_smc *smc ;
635 struct s_smt_rx_queue *queue ;
636 {
637 int i ;
638 int rx_used ;
639 u_long phys ;
640 u_long rbctrl ;
641 struct s_smt_fp_rxd volatile *r ;
642
643 SK_UNUSED(smc) ;
644
645 r = queue->rx_curr_get ;
646 rx_used = queue->rx_used ;
647 for (i = SMT_R1_RXD_COUNT-1 ; i ; i-- ) {
648 r = r->rxd_next ;
649 }
650 phys = AIX_REVERSE(r->rxd_nrdadr) ;
651
652 r = queue->rx_curr_get ;
653 while (rx_used) {
654 DRV_BUF_FLUSH(r,DDI_DMA_SYNC_FORCPU) ;
655 rbctrl = AIX_REVERSE(r->rxd_rbctrl) ;
656
657 if (rbctrl & BMU_OWN) {
658 if (rbctrl & BMU_STF) {
659 break ; /* exit the loop */
660 }
661 else {
662 /*
663 * repair the descriptor
664 */
665 r->rxd_rbctrl &= AIX_REVERSE(~BMU_OWN) ;
666 }
667 }
668 phys = AIX_REVERSE(r->rxd_nrdadr) ;
669 DRV_BUF_FLUSH(r,DDI_DMA_SYNC_FORDEV) ;
670 r = r->rxd_next ;
671 rx_used-- ;
672 }
673 return(phys) ;
674 }
675
676
677 /*
678 -------------------------------------------------------------
679 INTERRUPT SERVICE ROUTINE:
680 -------------------------------------------------------------
681 */
682
683 /*
684 * BEGIN_MANUAL_ENTRY(fddi_isr)
685 * void fddi_isr(smc)
686 *
687 * function DOWNCALL (drvsr.c)
688 * interrupt service routine, handles the interrupt requests
689 * generated by the FDDI adapter.
690 *
691 * NOTE: The operating system dependent module must garantee that the
692 * interrupts of the adapter are disabled when it calls fddi_isr.
693 *
694 * About the USE_BREAK_ISR mechanismn:
695 *
696 * The main requirement of this mechanismn is to force an timer IRQ when
697 * leaving process_receive() with leave_isr set. process_receive() may
698 * be called at any time from anywhere!
699 * To be sure we don't miss such event we set 'force_irq' per default.
700 * We have to force and Timer IRQ if 'smc->os.hwm.leave_isr' AND
701 * 'force_irq' are set. 'force_irq' may be reset if a receive complete
702 * IRQ is pending.
703 *
704 * END_MANUAL_ENTRY
705 */
fddi_isr(smc)706 void fddi_isr(smc)
707 struct s_smc *smc ;
708 {
709 u_long is ; /* ISR source */
710 u_short stu, stl ;
711 SMbuf *mb ;
712
713 #ifdef USE_BREAK_ISR
714 int force_irq ;
715 #endif
716
717 #ifdef ODI2
718 if (smc->os.hwm.rx_break) {
719 mac_drv_fill_rxd(smc) ;
720 if (smc->hw.fp.rx_q[QUEUE_R1].rx_used > 0) {
721 smc->os.hwm.rx_break = 0 ;
722 process_receive(smc) ;
723 }
724 else {
725 smc->os.hwm.detec_count = 0 ;
726 smt_force_irq(smc) ;
727 }
728 }
729 #endif
730 smc->os.hwm.isr_flag = TRUE ;
731
732 #ifdef USE_BREAK_ISR
733 force_irq = TRUE ;
734 if (smc->os.hwm.leave_isr) {
735 smc->os.hwm.leave_isr = FALSE ;
736 process_receive(smc) ;
737 }
738 #endif
739
740 while ((is = GET_ISR() & ISR_MASK)) {
741 NDD_TRACE("CH0B",is,0,0) ;
742 DB_GEN("ISA = 0x%x",is,0,7) ;
743
744 if (is & IMASK_SLOW) {
745 NDD_TRACE("CH1b",is,0,0) ;
746 if (is & IS_PLINT1) { /* PLC1 */
747 plc1_irq(smc) ;
748 }
749 if (is & IS_PLINT2) { /* PLC2 */
750 plc2_irq(smc) ;
751 }
752 if (is & IS_MINTR1) { /* FORMAC+ STU1(U/L) */
753 stu = inpw(FM_A(FM_ST1U)) ;
754 stl = inpw(FM_A(FM_ST1L)) ;
755 DB_GEN("Slow transmit complete",0,0,6) ;
756 mac1_irq(smc,stu,stl) ;
757 }
758 if (is & IS_MINTR2) { /* FORMAC+ STU2(U/L) */
759 stu= inpw(FM_A(FM_ST2U)) ;
760 stl= inpw(FM_A(FM_ST2L)) ;
761 DB_GEN("Slow receive complete",0,0,6) ;
762 DB_GEN("stl = %x : stu = %x",stl,stu,7) ;
763 mac2_irq(smc,stu,stl) ;
764 }
765 if (is & IS_MINTR3) { /* FORMAC+ STU3(U/L) */
766 stu= inpw(FM_A(FM_ST3U)) ;
767 stl= inpw(FM_A(FM_ST3L)) ;
768 DB_GEN("FORMAC Mode Register 3",0,0,6) ;
769 mac3_irq(smc,stu,stl) ;
770 }
771 if (is & IS_TIMINT) { /* Timer 82C54-2 */
772 timer_irq(smc) ;
773 #ifdef NDIS_OS2
774 force_irq_pending = 0 ;
775 #endif
776 /*
777 * out of RxD detection
778 */
779 if (++smc->os.hwm.detec_count > 4) {
780 /*
781 * check out of RxD condition
782 */
783 process_receive(smc) ;
784 }
785 }
786 if (is & IS_TOKEN) { /* Restricted Token Monitor */
787 rtm_irq(smc) ;
788 }
789 if (is & IS_R1_P) { /* Parity error rx queue 1 */
790 /* clear IRQ */
791 outpd(ADDR(B4_R1_CSR),CSR_IRQ_CL_P) ;
792 SMT_PANIC(smc,HWM_E0004,HWM_E0004_MSG) ;
793 }
794 if (is & IS_R1_C) { /* Encoding error rx queue 1 */
795 /* clear IRQ */
796 outpd(ADDR(B4_R1_CSR),CSR_IRQ_CL_C) ;
797 SMT_PANIC(smc,HWM_E0005,HWM_E0005_MSG) ;
798 }
799 if (is & IS_XA_C) { /* Encoding error async tx q */
800 /* clear IRQ */
801 outpd(ADDR(B5_XA_CSR),CSR_IRQ_CL_C) ;
802 SMT_PANIC(smc,HWM_E0006,HWM_E0006_MSG) ;
803 }
804 if (is & IS_XS_C) { /* Encoding error sync tx q */
805 /* clear IRQ */
806 outpd(ADDR(B5_XS_CSR),CSR_IRQ_CL_C) ;
807 SMT_PANIC(smc,HWM_E0007,HWM_E0007_MSG) ;
808 }
809 }
810
811 /*
812 * Fast Tx complete Async/Sync Queue (BMU service)
813 */
814 if (is & (IS_XS_F|IS_XA_F)) {
815 DB_GEN("Fast tx complete queue",0,0,6) ;
816 /*
817 * clear IRQ, Note: no IRQ is lost, because
818 * we always service both queues
819 */
820 outpd(ADDR(B5_XS_CSR),CSR_IRQ_CL_F) ;
821 outpd(ADDR(B5_XA_CSR),CSR_IRQ_CL_F) ;
822 mac_drv_clear_txd(smc) ;
823 llc_restart_tx(smc) ;
824 }
825
826 /*
827 * Fast Rx Complete (BMU service)
828 */
829 if (is & IS_R1_F) {
830 DB_GEN("Fast receive complete",0,0,6) ;
831 /* clear IRQ */
832 #ifndef USE_BREAK_ISR
833 outpd(ADDR(B4_R1_CSR),CSR_IRQ_CL_F) ;
834 process_receive(smc) ;
835 #else
836 process_receive(smc) ;
837 if (smc->os.hwm.leave_isr) {
838 force_irq = FALSE ;
839 } else {
840 outpd(ADDR(B4_R1_CSR),CSR_IRQ_CL_F) ;
841 process_receive(smc) ;
842 }
843 #endif
844 }
845
846 #ifndef NDIS_OS2
847 while ((mb = get_llc_rx(smc))) {
848 smt_to_llc(smc,mb) ;
849 }
850 #else
851 if (offDepth)
852 post_proc() ;
853
854 while (!offDepth && (mb = get_llc_rx(smc))) {
855 smt_to_llc(smc,mb) ;
856 }
857
858 if (!offDepth && smc->os.hwm.rx_break) {
859 process_receive(smc) ;
860 }
861 #endif
862 if (smc->q.ev_get != smc->q.ev_put) {
863 NDD_TRACE("CH2a",0,0,0) ;
864 ev_dispatcher(smc) ;
865 }
866 #ifdef NDIS_OS2
867 post_proc() ;
868 if (offDepth) { /* leave fddi_isr because */
869 break ; /* indications not allowed */
870 }
871 #endif
872 #ifdef USE_BREAK_ISR
873 if (smc->os.hwm.leave_isr) {
874 break ; /* leave fddi_isr */
875 }
876 #endif
877
878 /* NOTE: when the isr is left, no rx is pending */
879 } /* end of interrupt source polling loop */
880
881 #ifdef USE_BREAK_ISR
882 if (smc->os.hwm.leave_isr && force_irq) {
883 smt_force_irq(smc) ;
884 }
885 #endif
886 smc->os.hwm.isr_flag = FALSE ;
887 NDD_TRACE("CH0E",0,0,0) ;
888 }
889
890
891 /*
892 -------------------------------------------------------------
893 RECEIVE FUNCTIONS:
894 -------------------------------------------------------------
895 */
896
897 #ifndef NDIS_OS2
898 /*
899 * BEGIN_MANUAL_ENTRY(mac_drv_rx_mode)
900 * void mac_drv_rx_mode(smc,mode)
901 *
902 * function DOWNCALL (fplus.c)
903 * Corresponding to the parameter mode, the operating system
904 * dependent module can activate several receive modes.
905 *
906 * para mode = 1: RX_ENABLE_ALLMULTI enable all multicasts
907 * = 2: RX_DISABLE_ALLMULTI disable "enable all multicasts"
908 * = 3: RX_ENABLE_PROMISC enable promiscuous
909 * = 4: RX_DISABLE_PROMISC disable promiscuous
910 * = 5: RX_ENABLE_NSA enable rec. of all NSA frames
911 * (disabled after 'driver reset' & 'set station address')
912 * = 6: RX_DISABLE_NSA disable rec. of all NSA frames
913 *
914 * = 21: RX_ENABLE_PASS_SMT ( see description )
915 * = 22: RX_DISABLE_PASS_SMT ( " " )
916 * = 23: RX_ENABLE_PASS_NSA ( " " )
917 * = 24: RX_DISABLE_PASS_NSA ( " " )
918 * = 25: RX_ENABLE_PASS_DB ( " " )
919 * = 26: RX_DISABLE_PASS_DB ( " " )
920 * = 27: RX_DISABLE_PASS_ALL ( " " )
921 * = 28: RX_DISABLE_LLC_PROMISC ( " " )
922 * = 29: RX_ENABLE_LLC_PROMISC ( " " )
923 *
924 *
925 * RX_ENABLE_PASS_SMT / RX_DISABLE_PASS_SMT
926 *
927 * If the operating system dependent module activates the
928 * mode RX_ENABLE_PASS_SMT, the hardware module
929 * duplicates all SMT frames with the frame control
930 * FC_SMT_INFO and passes them to the LLC receive channel
931 * by calling mac_drv_rx_init.
932 * The SMT Frames which are sent by the local SMT and the NSA
933 * frames whose A- and C-Indicator is not set are also duplicated
934 * and passed.
935 * The receive mode RX_DISABLE_PASS_SMT disables the passing
936 * of SMT frames.
937 *
938 * RX_ENABLE_PASS_NSA / RX_DISABLE_PASS_NSA
939 *
940 * If the operating system dependent module activates the
941 * mode RX_ENABLE_PASS_NSA, the hardware module
942 * duplicates all NSA frames with frame control FC_SMT_NSA
943 * and a set A-Indicator and passed them to the LLC
944 * receive channel by calling mac_drv_rx_init.
945 * All NSA Frames which are sent by the local SMT
946 * are also duplicated and passed.
947 * The receive mode RX_DISABLE_PASS_NSA disables the passing
948 * of NSA frames with the A- or C-Indicator set.
949 *
950 * NOTE: For fear that the hardware module receives NSA frames with
951 * a reset A-Indicator, the operating system dependent module
952 * has to call mac_drv_rx_mode with the mode RX_ENABLE_NSA
953 * before activate the RX_ENABLE_PASS_NSA mode and after every
954 * 'driver reset' and 'set station address'.
955 *
956 * RX_ENABLE_PASS_DB / RX_DISABLE_PASS_DB
957 *
958 * If the operating system dependent module activates the
959 * mode RX_ENABLE_PASS_DB, direct BEACON frames
960 * (FC_BEACON frame control) are passed to the LLC receive
961 * channel by mac_drv_rx_init.
962 * The receive mode RX_DISABLE_PASS_DB disables the passing
963 * of direct BEACON frames.
964 *
965 * RX_DISABLE_PASS_ALL
966 *
967 * Disables all special receives modes. It is equal to
968 * call mac_drv_set_rx_mode successively with the
969 * parameters RX_DISABLE_NSA, RX_DISABLE_PASS_SMT,
970 * RX_DISABLE_PASS_NSA and RX_DISABLE_PASS_DB.
971 *
972 * RX_ENABLE_LLC_PROMISC
973 *
974 * (default) all received LLC frames and all SMT/NSA/DBEACON
975 * frames depending on the attitude of the flags
976 * PASS_SMT/PASS_NSA/PASS_DBEACON will be delivered to the
977 * LLC layer
978 *
979 * RX_DISABLE_LLC_PROMISC
980 *
981 * all received SMT/NSA/DBEACON frames depending on the
982 * attitude of the flags PASS_SMT/PASS_NSA/PASS_DBEACON
983 * will be delivered to the LLC layer.
984 * all received LLC frames with a directed address, Multicast
985 * or Broadcast address will be delivered to the LLC
986 * layer too.
987 *
988 * END_MANUAL_ENTRY
989 */
mac_drv_rx_mode(smc,mode)990 void mac_drv_rx_mode(smc,mode)
991 struct s_smc *smc ;
992 int mode ;
993 {
994 switch(mode) {
995 case RX_ENABLE_PASS_SMT:
996 smc->os.hwm.pass_SMT = TRUE ;
997 break ;
998 case RX_DISABLE_PASS_SMT:
999 smc->os.hwm.pass_SMT = FALSE ;
1000 break ;
1001 case RX_ENABLE_PASS_NSA:
1002 smc->os.hwm.pass_NSA = TRUE ;
1003 break ;
1004 case RX_DISABLE_PASS_NSA:
1005 smc->os.hwm.pass_NSA = FALSE ;
1006 break ;
1007 case RX_ENABLE_PASS_DB:
1008 smc->os.hwm.pass_DB = TRUE ;
1009 break ;
1010 case RX_DISABLE_PASS_DB:
1011 smc->os.hwm.pass_DB = FALSE ;
1012 break ;
1013 case RX_DISABLE_PASS_ALL:
1014 smc->os.hwm.pass_SMT = smc->os.hwm.pass_NSA = FALSE ;
1015 smc->os.hwm.pass_DB = FALSE ;
1016 smc->os.hwm.pass_llc_promisc = TRUE ;
1017 mac_set_rx_mode(smc,RX_DISABLE_NSA) ;
1018 break ;
1019 case RX_DISABLE_LLC_PROMISC:
1020 smc->os.hwm.pass_llc_promisc = FALSE ;
1021 break ;
1022 case RX_ENABLE_LLC_PROMISC:
1023 smc->os.hwm.pass_llc_promisc = TRUE ;
1024 break ;
1025 case RX_ENABLE_ALLMULTI:
1026 case RX_DISABLE_ALLMULTI:
1027 case RX_ENABLE_PROMISC:
1028 case RX_DISABLE_PROMISC:
1029 case RX_ENABLE_NSA:
1030 case RX_DISABLE_NSA:
1031 default:
1032 mac_set_rx_mode(smc,mode) ;
1033 break ;
1034 }
1035 }
1036 #endif /* ifndef NDIS_OS2 */
1037
1038 /*
1039 * process receive queue
1040 */
process_receive(smc)1041 void process_receive(smc)
1042 struct s_smc *smc ;
1043 {
1044 int i ;
1045 int n ;
1046 int frag_count ; /* number of RxDs of the curr rx buf */
1047 int used_frags ; /* number of RxDs of the curr frame */
1048 struct s_smt_rx_queue *queue ; /* points to the queue ctl struct */
1049 struct s_smt_fp_rxd volatile *r ; /* rxd pointer */
1050 struct s_smt_fp_rxd volatile *rxd ; /* first rxd of rx frame */
1051 u_long rbctrl ; /* receive buffer control word */
1052 u_long rfsw ; /* receive frame status word */
1053 u_short rx_used ;
1054 u_char far *virt ;
1055 char far *data ;
1056 SMbuf *mb ;
1057 u_char fc ; /* Frame control */
1058 int len ; /* Frame length */
1059
1060 smc->os.hwm.detec_count = 0 ;
1061 queue = smc->hw.fp.rx[QUEUE_R1] ;
1062 NDD_TRACE("RHxB",0,0,0) ;
1063 for ( ; ; ) {
1064 r = queue->rx_curr_get ;
1065 rx_used = queue->rx_used ;
1066 frag_count = 0 ;
1067
1068 #ifdef USE_BREAK_ISR
1069 if (smc->os.hwm.leave_isr) {
1070 goto rx_end ;
1071 }
1072 #endif
1073 #ifdef NDIS_OS2
1074 if (offDepth) {
1075 smc->os.hwm.rx_break = 1 ;
1076 goto rx_end ;
1077 }
1078 smc->os.hwm.rx_break = 0 ;
1079 #endif
1080 #ifdef ODI2
1081 if (smc->os.hwm.rx_break) {
1082 goto rx_end ;
1083 }
1084 #endif
1085 n = 0 ;
1086 do {
1087 DB_RX("Check RxD %x for OWN and EOF",(void *)r,0,5) ;
1088 DRV_BUF_FLUSH(r,DDI_DMA_SYNC_FORCPU) ;
1089 rbctrl = CR_READ(r->rxd_rbctrl) ;
1090 rbctrl = AIX_REVERSE(rbctrl) ;
1091
1092 if (rbctrl & BMU_OWN) {
1093 NDD_TRACE("RHxE",r,rfsw,rbctrl) ;
1094 DB_RX("End of RxDs",0,0,4) ;
1095 goto rx_end ;
1096 }
1097 /*
1098 * out of RxD detection
1099 */
1100 if (!rx_used) {
1101 SK_BREAK() ;
1102 SMT_PANIC(smc,HWM_E0009,HWM_E0009_MSG) ;
1103 /* Either we don't have an RxD or all
1104 * RxDs are filled. Therefore it's allowed
1105 * for to set the STOPPED flag */
1106 smc->hw.hw_state = STOPPED ;
1107 mac_drv_clear_rx_queue(smc) ;
1108 smc->hw.hw_state = STARTED ;
1109 mac_drv_fill_rxd(smc) ;
1110 smc->os.hwm.detec_count = 0 ;
1111 goto rx_end ;
1112 }
1113 rfsw = AIX_REVERSE(r->rxd_rfsw) ;
1114 if ((rbctrl & BMU_STF) != ((rbctrl & BMU_ST_BUF) <<5)) {
1115 /*
1116 * The BMU_STF bit is deleted, 1 frame is
1117 * placed into more than 1 rx buffer
1118 *
1119 * skip frame by setting the rx len to 0
1120 *
1121 * if fragment count == 0
1122 * The missing STF bit belongs to the
1123 * current frame, search for the
1124 * EOF bit to complete the frame
1125 * else
1126 * the fragment belongs to the next frame,
1127 * exit the loop and process the frame
1128 */
1129 SK_BREAK() ;
1130 rfsw = 0 ;
1131 if (frag_count) {
1132 break ;
1133 }
1134 }
1135 n += rbctrl & 0xffff ;
1136 r = r->rxd_next ;
1137 frag_count++ ;
1138 rx_used-- ;
1139 } while (!(rbctrl & BMU_EOF)) ;
1140 used_frags = frag_count ;
1141 DB_RX("EOF set in RxD, used_frags = %d ",used_frags,0,5) ;
1142
1143 /* may be next 2 DRV_BUF_FLUSH() can be skipped, because */
1144 /* BMU_ST_BUF will not be changed by the ASIC */
1145 DRV_BUF_FLUSH(r,DDI_DMA_SYNC_FORCPU) ;
1146 while (rx_used && !(r->rxd_rbctrl & AIX_REVERSE(BMU_ST_BUF))) {
1147 DB_RX("Check STF bit in %x",(void *)r,0,5) ;
1148 r = r->rxd_next ;
1149 DRV_BUF_FLUSH(r,DDI_DMA_SYNC_FORCPU) ;
1150 frag_count++ ;
1151 rx_used-- ;
1152 }
1153 DB_RX("STF bit found",0,0,5) ;
1154
1155 /*
1156 * The received frame is finished for the process receive
1157 */
1158 rxd = queue->rx_curr_get ;
1159 queue->rx_curr_get = r ;
1160 queue->rx_free += frag_count ;
1161 queue->rx_used = rx_used ;
1162
1163 /*
1164 * ASIC Errata no. 7 (STF - Bit Bug)
1165 */
1166 rxd->rxd_rbctrl &= AIX_REVERSE(~BMU_STF) ;
1167
1168 for (r=rxd, i=frag_count ; i ; r=r->rxd_next, i--){
1169 DB_RX("dma_complete for RxD %x",(void *)r,0,5) ;
1170 dma_complete(smc,(union s_fp_descr volatile *)r,DMA_WR);
1171 }
1172 smc->hw.fp.err_stats.err_valid++ ;
1173 smc->mib.m[MAC0].fddiMACCopied_Ct++ ;
1174
1175 /* the length of the data including the FC */
1176 len = (rfsw & RD_LENGTH) - 4 ;
1177
1178 DB_RX("frame length = %d",len,0,4) ;
1179 /*
1180 * check the frame_lenght and all error flags
1181 */
1182 if (rfsw & (RX_MSRABT|RX_FS_E|RX_FS_CRC|RX_FS_IMPL)){
1183 if (rfsw & RD_S_MSRABT) {
1184 DB_RX("Frame aborted by the FORMAC",0,0,2) ;
1185 smc->hw.fp.err_stats.err_abort++ ;
1186 }
1187 /*
1188 * check frame status
1189 */
1190 if (rfsw & RD_S_SEAC2) {
1191 DB_RX("E-Indicator set",0,0,2) ;
1192 smc->hw.fp.err_stats.err_e_indicator++ ;
1193 }
1194 if (rfsw & RD_S_SFRMERR) {
1195 DB_RX("CRC error",0,0,2) ;
1196 smc->hw.fp.err_stats.err_crc++ ;
1197 }
1198 if (rfsw & RX_FS_IMPL) {
1199 DB_RX("Implementer frame",0,0,2) ;
1200 smc->hw.fp.err_stats.err_imp_frame++ ;
1201 }
1202 goto abort_frame ;
1203 }
1204 if (len > FDDI_RAW_MTU-4) {
1205 DB_RX("Frame to long error",0,0,2) ;
1206 smc->hw.fp.err_stats.err_too_long++ ;
1207 goto abort_frame ;
1208 }
1209 /*
1210 * SUPERNET 3 Bug: FORMAC delivers status words
1211 * of aborded frames to the BMU
1212 */
1213 if (len <= 4) {
1214 DB_RX("Frame length = 0",0,0,2) ;
1215 goto abort_frame ;
1216 }
1217
1218 if (len != (n-4)) {
1219 DB_RX("BMU: rx len differs: [%d:%d]",len,n,4);
1220 smc->os.hwm.rx_len_error++ ;
1221 goto abort_frame ;
1222 }
1223
1224 /*
1225 * Check SA == MA
1226 */
1227 virt = (u_char far *) rxd->rxd_virt ;
1228 DB_RX("FC = %x",*virt,0,2) ;
1229 if (virt[12] == MA[5] &&
1230 virt[11] == MA[4] &&
1231 virt[10] == MA[3] &&
1232 virt[9] == MA[2] &&
1233 virt[8] == MA[1] &&
1234 (virt[7] & ~GROUP_ADDR_BIT) == MA[0]) {
1235 goto abort_frame ;
1236 }
1237
1238 /*
1239 * test if LLC frame
1240 */
1241 if (rfsw & RX_FS_LLC) {
1242 /*
1243 * if pass_llc_promisc is disable
1244 * if DA != Multicast or Broadcast or DA!=MA
1245 * abort the frame
1246 */
1247 if (!smc->os.hwm.pass_llc_promisc) {
1248 if(!(virt[1] & GROUP_ADDR_BIT)) {
1249 if (virt[6] != MA[5] ||
1250 virt[5] != MA[4] ||
1251 virt[4] != MA[3] ||
1252 virt[3] != MA[2] ||
1253 virt[2] != MA[1] ||
1254 virt[1] != MA[0]) {
1255 DB_RX("DA != MA and not multi- or broadcast",0,0,2) ;
1256 goto abort_frame ;
1257 }
1258 }
1259 }
1260
1261 /*
1262 * LLC frame received
1263 */
1264 DB_RX("LLC - receive",0,0,4) ;
1265 mac_drv_rx_complete(smc,rxd,frag_count,len) ;
1266 }
1267 else {
1268 if (!(mb = smt_get_mbuf(smc))) {
1269 smc->hw.fp.err_stats.err_no_buf++ ;
1270 DB_RX("No SMbuf; receive terminated",0,0,4) ;
1271 goto abort_frame ;
1272 }
1273 data = smtod(mb,char *) - 1 ;
1274
1275 /*
1276 * copy the frame into a SMT_MBuf
1277 */
1278 #ifdef USE_OS_CPY
1279 hwm_cpy_rxd2mb(rxd,data,len) ;
1280 #else
1281 for (r=rxd, i=used_frags ; i ; r=r->rxd_next, i--){
1282 n = AIX_REVERSE(r->rxd_rbctrl) & RD_LENGTH ;
1283 DB_RX("cp SMT frame to mb: len = %d",n,0,6) ;
1284 memcpy(data,r->rxd_virt,n) ;
1285 data += n ;
1286 }
1287 data = smtod(mb,char *) - 1 ;
1288 #endif
1289 fc = *(char *)mb->sm_data = *data ;
1290 mb->sm_len = len - 1 ; /* len - fc */
1291 data++ ;
1292
1293 /*
1294 * SMT frame received
1295 */
1296 switch(fc) {
1297 case FC_SMT_INFO :
1298 smc->hw.fp.err_stats.err_smt_frame++ ;
1299 DB_RX("SMT frame received ",0,0,5) ;
1300
1301 if (smc->os.hwm.pass_SMT) {
1302 DB_RX("pass SMT frame ",0,0,5) ;
1303 mac_drv_rx_complete(smc, rxd,
1304 frag_count,len) ;
1305 }
1306 else {
1307 DB_RX("requeue RxD",0,0,5) ;
1308 mac_drv_requeue_rxd(smc,rxd,frag_count);
1309 }
1310
1311 smt_received_pack(smc,mb,(int)(rfsw>>25)) ;
1312 break ;
1313 case FC_SMT_NSA :
1314 smc->hw.fp.err_stats.err_smt_frame++ ;
1315 DB_RX("SMT frame received ",0,0,5) ;
1316
1317 /* if pass_NSA set pass the NSA frame or */
1318 /* pass_SMT set and the A-Indicator */
1319 /* is not set, pass the NSA frame */
1320 if (smc->os.hwm.pass_NSA ||
1321 (smc->os.hwm.pass_SMT &&
1322 !(rfsw & A_INDIC))) {
1323 DB_RX("pass SMT frame ",0,0,5) ;
1324 mac_drv_rx_complete(smc, rxd,
1325 frag_count,len) ;
1326 }
1327 else {
1328 DB_RX("requeue RxD",0,0,5) ;
1329 mac_drv_requeue_rxd(smc,rxd,frag_count);
1330 }
1331
1332 smt_received_pack(smc,mb,(int)(rfsw>>25)) ;
1333 break ;
1334 case FC_BEACON :
1335 if (smc->os.hwm.pass_DB) {
1336 DB_RX("pass DB frame ",0,0,5) ;
1337 mac_drv_rx_complete(smc, rxd,
1338 frag_count,len) ;
1339 }
1340 else {
1341 DB_RX("requeue RxD",0,0,5) ;
1342 mac_drv_requeue_rxd(smc,rxd,frag_count);
1343 }
1344 smt_free_mbuf(smc,mb) ;
1345 break ;
1346 default :
1347 /*
1348 * unknown FC abord the frame
1349 */
1350 DB_RX("unknown FC error",0,0,2) ;
1351 smt_free_mbuf(smc,mb) ;
1352 DB_RX("requeue RxD",0,0,5) ;
1353 mac_drv_requeue_rxd(smc,rxd,frag_count) ;
1354 if ((fc & 0xf0) == FC_MAC)
1355 smc->hw.fp.err_stats.err_mac_frame++ ;
1356 else
1357 smc->hw.fp.err_stats.err_imp_frame++ ;
1358
1359 break ;
1360 }
1361 }
1362
1363 DB_RX("next RxD is %x ",queue->rx_curr_get,0,3) ;
1364 NDD_TRACE("RHx1",queue->rx_curr_get,0,0) ;
1365
1366 continue ;
1367 /*--------------------------------------------------------------------*/
1368 abort_frame:
1369 DB_RX("requeue RxD",0,0,5) ;
1370 mac_drv_requeue_rxd(smc,rxd,frag_count) ;
1371
1372 DB_RX("next RxD is %x ",queue->rx_curr_get,0,3) ;
1373 NDD_TRACE("RHx2",queue->rx_curr_get,0,0) ;
1374 }
1375 rx_end:
1376 #ifdef ALL_RX_COMPLETE
1377 mac_drv_all_receives_complete(smc) ;
1378 #endif
1379 return ; /* lint bug: needs return detect end of function */
1380 }
1381
smt_to_llc(smc,mb)1382 static void smt_to_llc(smc,mb)
1383 struct s_smc *smc ;
1384 SMbuf *mb ;
1385 {
1386 u_char fc ;
1387
1388 DB_RX("send a queued frame to the llc layer",0,0,4) ;
1389 smc->os.hwm.r.len = mb->sm_len ;
1390 smc->os.hwm.r.mb_pos = smtod(mb,char *) ;
1391 fc = *smc->os.hwm.r.mb_pos ;
1392 (void)mac_drv_rx_init(smc,(int)mb->sm_len,(int)fc,
1393 smc->os.hwm.r.mb_pos,(int)mb->sm_len) ;
1394 smt_free_mbuf(smc,mb) ;
1395 }
1396
1397 /*
1398 * BEGIN_MANUAL_ENTRY(hwm_rx_frag)
1399 * void hwm_rx_frag(smc,virt,phys,len,frame_status)
1400 *
1401 * function MACRO (hardware module, hwmtm.h)
1402 * This function calls dma_master for preparing the
1403 * system hardware for the DMA transfer and initializes
1404 * the current RxD with the length and the physical and
1405 * virtual address of the fragment. Furthermore, it sets the
1406 * STF and EOF bits depending on the frame status byte,
1407 * switches the OWN flag of the RxD, so that it is owned by the
1408 * adapter and issues an rx_start.
1409 *
1410 * para virt virtual pointer to the fragment
1411 * len the length of the fragment
1412 * frame_status status of the frame, see design description
1413 *
1414 * NOTE: It is possible to call this function with a fragment length
1415 * of zero.
1416 *
1417 * END_MANUAL_ENTRY
1418 */
hwm_rx_frag(smc,virt,phys,len,frame_status)1419 void hwm_rx_frag(smc,virt,phys,len,frame_status)
1420 struct s_smc *smc ;
1421 char far *virt ;
1422 u_long phys ;
1423 int len ;
1424 int frame_status ;
1425 {
1426 struct s_smt_fp_rxd volatile *r ;
1427 u_int rbctrl ;
1428
1429 NDD_TRACE("RHfB",virt,len,frame_status) ;
1430 DB_RX("hwm_rx_frag: len = %d, frame_status = %x\n",len,frame_status,2) ;
1431 r = smc->hw.fp.rx_q[QUEUE_R1].rx_curr_put ;
1432 r->rxd_virt = virt ;
1433 r->rxd_rbadr = AIX_REVERSE(phys) ;
1434 rbctrl = AIX_REVERSE( (((u_long)frame_status &
1435 (FIRST_FRAG|LAST_FRAG))<<26) |
1436 (((u_long) frame_status & FIRST_FRAG) << 21) |
1437 BMU_OWN | BMU_CHECK | BMU_EN_IRQ_EOF | len) ;
1438 r->rxd_rbctrl = rbctrl ;
1439
1440 DRV_BUF_FLUSH(r,DDI_DMA_SYNC_FORDEV) ;
1441 outpd(ADDR(B0_R1_CSR),CSR_START) ;
1442 smc->hw.fp.rx_q[QUEUE_R1].rx_free-- ;
1443 smc->hw.fp.rx_q[QUEUE_R1].rx_used++ ;
1444 smc->hw.fp.rx_q[QUEUE_R1].rx_curr_put = r->rxd_next ;
1445 NDD_TRACE("RHfE",r,AIX_REVERSE(r->rxd_rbadr),0) ;
1446 }
1447
1448 #ifndef NDIS_OS2
1449 /*
1450 * BEGIN_MANUAL_ENTRY(mac_drv_rx_frag)
1451 * int mac_drv_rx_frag(smc,virt,len)
1452 *
1453 * function DOWNCALL (hwmtm.c)
1454 * mac_drv_rx_frag fills the fragment with a part of the frame.
1455 *
1456 * para virt the virtual address of the fragment
1457 * len the length in bytes of the fragment
1458 *
1459 * return 0: success code, no errors possible
1460 *
1461 * END_MANUAL_ENTRY
1462 */
mac_drv_rx_frag(smc,virt,len)1463 int mac_drv_rx_frag(smc,virt,len)
1464 struct s_smc *smc ;
1465 void far *virt ;
1466 int len ;
1467 {
1468 NDD_TRACE("RHSB",virt,len,smc->os.hwm.r.mb_pos) ;
1469
1470 DB_RX("receive from queue: len/virt: = %d/%x",len,virt,4) ;
1471 memcpy((char far *)virt,smc->os.hwm.r.mb_pos,len) ;
1472 smc->os.hwm.r.mb_pos += len ;
1473
1474 NDD_TRACE("RHSE",smc->os.hwm.r.mb_pos,0,0) ;
1475 return(0) ;
1476 }
1477 #endif
1478
1479
1480 /*
1481 * BEGINN_MANUAL_ENTRY(mac_drv_clear_rx_queue)
1482 *
1483 * void mac_drv_clear_rx_queue(smc)
1484 * struct s_smc *smc ;
1485 *
1486 * function DOWNCALL (hardware module, hwmtm.c)
1487 * mac_drv_clear_rx_queue is called by the OS-specific module
1488 * after it has issued a card_stop.
1489 * In this case, the frames in the receive queue are obsolete and
1490 * should be removed. For removing mac_drv_clear_rx_queue
1491 * calls dma_master for each RxD and mac_drv_clear_rxd for each
1492 * receive buffer.
1493 *
1494 * NOTE: calling sequence card_stop:
1495 * CLI_FBI(), card_stop(),
1496 * mac_drv_clear_tx_queue(), mac_drv_clear_rx_queue(),
1497 *
1498 * NOTE: The caller is responsible that the BMUs are idle
1499 * when this function is called.
1500 *
1501 * END_MANUAL_ENTRY
1502 */
mac_drv_clear_rx_queue(smc)1503 void mac_drv_clear_rx_queue(smc)
1504 struct s_smc *smc ;
1505 {
1506 struct s_smt_fp_rxd volatile *r ;
1507 struct s_smt_fp_rxd volatile *next_rxd ;
1508 struct s_smt_rx_queue *queue ;
1509 int frag_count ;
1510 int i ;
1511
1512 if (smc->hw.hw_state != STOPPED) {
1513 SK_BREAK() ;
1514 SMT_PANIC(smc,HWM_E0012,HWM_E0012_MSG) ;
1515 return ;
1516 }
1517
1518 queue = smc->hw.fp.rx[QUEUE_R1] ;
1519 DB_RX("clear_rx_queue",0,0,5) ;
1520
1521 /*
1522 * dma_complete and mac_drv_clear_rxd for all RxDs / receive buffers
1523 */
1524 r = queue->rx_curr_get ;
1525 while (queue->rx_used) {
1526 DRV_BUF_FLUSH(r,DDI_DMA_SYNC_FORCPU) ;
1527 DB_RX("switch OWN bit of RxD 0x%x ",r,0,5) ;
1528 r->rxd_rbctrl &= AIX_REVERSE(~BMU_OWN) ;
1529 frag_count = 1 ;
1530 DRV_BUF_FLUSH(r,DDI_DMA_SYNC_FORDEV) ;
1531 r = r->rxd_next ;
1532 DRV_BUF_FLUSH(r,DDI_DMA_SYNC_FORCPU) ;
1533 while (r != queue->rx_curr_put &&
1534 !(r->rxd_rbctrl & AIX_REVERSE(BMU_ST_BUF))) {
1535 DB_RX("Check STF bit in %x",(void *)r,0,5) ;
1536 r->rxd_rbctrl &= AIX_REVERSE(~BMU_OWN) ;
1537 DRV_BUF_FLUSH(r,DDI_DMA_SYNC_FORDEV) ;
1538 r = r->rxd_next ;
1539 DRV_BUF_FLUSH(r,DDI_DMA_SYNC_FORCPU) ;
1540 frag_count++ ;
1541 }
1542 DB_RX("STF bit found",0,0,5) ;
1543 next_rxd = r ;
1544
1545 for (r=queue->rx_curr_get,i=frag_count; i ; r=r->rxd_next,i--){
1546 DB_RX("dma_complete for RxD %x",(void *)r,0,5) ;
1547 dma_complete(smc,(union s_fp_descr volatile *)r,DMA_WR);
1548 }
1549
1550 DB_RX("mac_drv_clear_rxd: RxD %x frag_count %d ",
1551 (void *)queue->rx_curr_get,frag_count,5) ;
1552 mac_drv_clear_rxd(smc,queue->rx_curr_get,frag_count) ;
1553
1554 queue->rx_curr_get = next_rxd ;
1555 queue->rx_used -= frag_count ;
1556 queue->rx_free += frag_count ;
1557 }
1558 }
1559
1560
1561 /*
1562 -------------------------------------------------------------
1563 SEND FUNCTIONS:
1564 -------------------------------------------------------------
1565 */
1566
1567 /*
1568 * BEGIN_MANUAL_ENTRY(hwm_tx_init)
1569 * int hwm_tx_init(smc,fc,frag_count,frame_len,frame_status)
1570 *
1571 * function DOWN_CALL (hardware module, hwmtm.c)
1572 * hwm_tx_init checks if the frame can be sent through the
1573 * corresponding send queue.
1574 *
1575 * para fc the frame control. To determine through which
1576 * send queue the frame should be transmitted.
1577 * 0x50 - 0x57: asynchronous LLC frame
1578 * 0xD0 - 0xD7: synchronous LLC frame
1579 * 0x41, 0x4F: SMT frame to the network
1580 * 0x42: SMT frame to the network and to the local SMT
1581 * 0x43: SMT frame to the local SMT
1582 * frag_count count of the fragments for this frame
1583 * frame_len length of the frame
1584 * frame_status status of the frame, the send queue bit is already
1585 * specified
1586 *
1587 * return frame_status
1588 *
1589 * END_MANUAL_ENTRY
1590 */
hwm_tx_init(smc,fc,frag_count,frame_len,frame_status)1591 int hwm_tx_init(smc,fc,frag_count,frame_len,frame_status)
1592 struct s_smc *smc ;
1593 u_char fc ;
1594 int frag_count ;
1595 int frame_len ;
1596 int frame_status ;
1597 {
1598 NDD_TRACE("THiB",fc,frag_count,frame_len) ;
1599 smc->os.hwm.tx_p = smc->hw.fp.tx[frame_status & QUEUE_A0] ;
1600 smc->os.hwm.tx_descr = TX_DESCRIPTOR | (((u_long)(frame_len-1)&3)<<27) ;
1601 smc->os.hwm.tx_len = frame_len ;
1602 DB_TX("hwm_tx_init: fc = %x, len = %d",fc,frame_len,3) ;
1603 if ((fc & ~(FC_SYNC_BIT|FC_LLC_PRIOR)) == FC_ASYNC_LLC) {
1604 frame_status |= LAN_TX ;
1605 }
1606 else {
1607 switch (fc) {
1608 case FC_SMT_INFO :
1609 case FC_SMT_NSA :
1610 frame_status |= LAN_TX ;
1611 break ;
1612 case FC_SMT_LOC :
1613 frame_status |= LOC_TX ;
1614 break ;
1615 case FC_SMT_LAN_LOC :
1616 frame_status |= LAN_TX | LOC_TX ;
1617 break ;
1618 default :
1619 SMT_PANIC(smc,HWM_E0010,HWM_E0010_MSG) ;
1620 }
1621 }
1622 if (!smc->hw.mac_ring_is_up) {
1623 frame_status &= ~LAN_TX ;
1624 frame_status |= RING_DOWN ;
1625 DB_TX("Ring is down: terminate LAN_TX",0,0,2) ;
1626 }
1627 if (frag_count > smc->os.hwm.tx_p->tx_free) {
1628 #ifndef NDIS_OS2
1629 mac_drv_clear_txd(smc) ;
1630 if (frag_count > smc->os.hwm.tx_p->tx_free) {
1631 DB_TX("Out of TxDs, terminate LAN_TX",0,0,2) ;
1632 frame_status &= ~LAN_TX ;
1633 frame_status |= OUT_OF_TXD ;
1634 }
1635 #else
1636 DB_TX("Out of TxDs, terminate LAN_TX",0,0,2) ;
1637 frame_status &= ~LAN_TX ;
1638 frame_status |= OUT_OF_TXD ;
1639 #endif
1640 }
1641 DB_TX("frame_status = %x",frame_status,0,3) ;
1642 NDD_TRACE("THiE",frame_status,smc->os.hwm.tx_p->tx_free,0) ;
1643 return(frame_status) ;
1644 }
1645
1646 /*
1647 * BEGIN_MANUAL_ENTRY(hwm_tx_frag)
1648 * void hwm_tx_frag(smc,virt,phys,len,frame_status)
1649 *
1650 * function DOWNCALL (hardware module, hwmtm.c)
1651 * If the frame should be sent to the LAN, this function calls
1652 * dma_master, fills the current TxD with the virtual and the
1653 * physical address, sets the STF and EOF bits dependent on
1654 * the frame status, and requests the BMU to start the
1655 * transmit.
1656 * If the frame should be sent to the local SMT, an SMT_MBuf
1657 * is allocated if the FIRST_FRAG bit is set in the frame_status.
1658 * The fragment of the frame is copied into the SMT MBuf.
1659 * The function smt_received_pack is called if the LAST_FRAG
1660 * bit is set in the frame_status word.
1661 *
1662 * para virt virtual pointer to the fragment
1663 * len the length of the fragment
1664 * frame_status status of the frame, see design description
1665 *
1666 * return nothing returned, no parameter is modified
1667 *
1668 * NOTE: It is possible to invoke this macro with a fragment length
1669 * of zero.
1670 *
1671 * END_MANUAL_ENTRY
1672 */
hwm_tx_frag(smc,virt,phys,len,frame_status)1673 void hwm_tx_frag(smc,virt,phys,len,frame_status)
1674 struct s_smc *smc ;
1675 char far *virt ;
1676 u_long phys ;
1677 int len ;
1678 int frame_status ;
1679 {
1680 struct s_smt_fp_txd volatile *t ;
1681 struct s_smt_tx_queue *queue ;
1682 u_int tbctrl ;
1683
1684 queue = smc->os.hwm.tx_p ;
1685
1686 NDD_TRACE("THfB",virt,len,frame_status) ;
1687 /* Bug fix: AF / May 31 1999 (#missing)
1688 * snmpinfo problem reported by IBM is caused by invalid
1689 * t-pointer (txd) if LAN_TX is not set but LOC_TX only.
1690 * Set: t = queue->tx_curr_put here !
1691 */
1692 t = queue->tx_curr_put ;
1693
1694 DB_TX("hwm_tx_frag: len = %d, frame_status = %x ",len,frame_status,2) ;
1695 if (frame_status & LAN_TX) {
1696 /* '*t' is already defined */
1697 DB_TX("LAN_TX: TxD = %x, virt = %x ",t,virt,3) ;
1698 t->txd_virt = virt ;
1699 t->txd_txdscr = AIX_REVERSE(smc->os.hwm.tx_descr) ;
1700 t->txd_tbadr = AIX_REVERSE(phys) ;
1701 tbctrl = AIX_REVERSE((((u_long)frame_status &
1702 (FIRST_FRAG|LAST_FRAG|EN_IRQ_EOF))<< 26) |
1703 BMU_OWN|BMU_CHECK |len) ;
1704 t->txd_tbctrl = tbctrl ;
1705
1706 #ifndef AIX
1707 DRV_BUF_FLUSH(t,DDI_DMA_SYNC_FORDEV) ;
1708 outpd(queue->tx_bmu_ctl,CSR_START) ;
1709 #else /* ifndef AIX */
1710 DRV_BUF_FLUSH(t,DDI_DMA_SYNC_FORDEV) ;
1711 if (frame_status & QUEUE_A0) {
1712 outpd(ADDR(B0_XA_CSR),CSR_START) ;
1713 }
1714 else {
1715 outpd(ADDR(B0_XS_CSR),CSR_START) ;
1716 }
1717 #endif
1718 queue->tx_free-- ;
1719 queue->tx_used++ ;
1720 queue->tx_curr_put = t->txd_next ;
1721 if (frame_status & LAST_FRAG) {
1722 smc->mib.m[MAC0].fddiMACTransmit_Ct++ ;
1723 }
1724 }
1725 if (frame_status & LOC_TX) {
1726 DB_TX("LOC_TX: ",0,0,3) ;
1727 if (frame_status & FIRST_FRAG) {
1728 if(!(smc->os.hwm.tx_mb = smt_get_mbuf(smc))) {
1729 smc->hw.fp.err_stats.err_no_buf++ ;
1730 DB_TX("No SMbuf; transmit terminated",0,0,4) ;
1731 }
1732 else {
1733 smc->os.hwm.tx_data =
1734 smtod(smc->os.hwm.tx_mb,char *) - 1 ;
1735 #ifdef USE_OS_CPY
1736 #ifdef PASS_1ST_TXD_2_TX_COMP
1737 hwm_cpy_txd2mb(t,smc->os.hwm.tx_data,
1738 smc->os.hwm.tx_len) ;
1739 #endif
1740 #endif
1741 }
1742 }
1743 if (smc->os.hwm.tx_mb) {
1744 #ifndef USE_OS_CPY
1745 DB_TX("copy fragment into MBuf ",0,0,3) ;
1746 memcpy(smc->os.hwm.tx_data,virt,len) ;
1747 smc->os.hwm.tx_data += len ;
1748 #endif
1749 if (frame_status & LAST_FRAG) {
1750 #ifdef USE_OS_CPY
1751 #ifndef PASS_1ST_TXD_2_TX_COMP
1752 /*
1753 * hwm_cpy_txd2mb(txd,data,len) copies 'len'
1754 * bytes from the virtual pointer in 'rxd'
1755 * to 'data'. The virtual pointer of the
1756 * os-specific tx-buffer should be written
1757 * in the LAST txd.
1758 */
1759 hwm_cpy_txd2mb(t,smc->os.hwm.tx_data,
1760 smc->os.hwm.tx_len) ;
1761 #endif /* nPASS_1ST_TXD_2_TX_COMP */
1762 #endif /* USE_OS_CPY */
1763 smc->os.hwm.tx_data =
1764 smtod(smc->os.hwm.tx_mb,char *) - 1 ;
1765 *(char *)smc->os.hwm.tx_mb->sm_data =
1766 *smc->os.hwm.tx_data ;
1767 smc->os.hwm.tx_data++ ;
1768 smc->os.hwm.tx_mb->sm_len =
1769 smc->os.hwm.tx_len - 1 ;
1770 DB_TX("pass LLC frame to SMT ",0,0,3) ;
1771 smt_received_pack(smc,smc->os.hwm.tx_mb,
1772 RD_FS_LOCAL) ;
1773 }
1774 }
1775 }
1776 NDD_TRACE("THfE",t,queue->tx_free,0) ;
1777 }
1778
1779
1780 /*
1781 * queues a receive for later send
1782 */
queue_llc_rx(smc,mb)1783 static void queue_llc_rx(smc,mb)
1784 struct s_smc *smc ;
1785 SMbuf *mb ;
1786 {
1787 DB_GEN("queue_llc_rx: mb = %x",(void *)mb,0,4) ;
1788 smc->os.hwm.queued_rx_frames++ ;
1789 mb->sm_next = (SMbuf *)NULL ;
1790 if (smc->os.hwm.llc_rx_pipe == 0) {
1791 smc->os.hwm.llc_rx_pipe = mb ;
1792 }
1793 else {
1794 smc->os.hwm.llc_rx_tail->sm_next = mb ;
1795 }
1796 smc->os.hwm.llc_rx_tail = mb ;
1797
1798 /*
1799 * force an timer IRQ to receive the data
1800 */
1801 if (!smc->os.hwm.isr_flag) {
1802 smt_force_irq(smc) ;
1803 }
1804 }
1805
1806 /*
1807 * get a SMbuf from the llc_rx_queue
1808 */
get_llc_rx(smc)1809 static SMbuf *get_llc_rx(smc)
1810 struct s_smc *smc ;
1811 {
1812 SMbuf *mb ;
1813
1814 if ((mb = smc->os.hwm.llc_rx_pipe)) {
1815 smc->os.hwm.queued_rx_frames-- ;
1816 smc->os.hwm.llc_rx_pipe = mb->sm_next ;
1817 }
1818 DB_GEN("get_llc_rx: mb = 0x%x",(void *)mb,0,4) ;
1819 return(mb) ;
1820 }
1821
1822 /*
1823 * queues a transmit SMT MBuf during the time were the MBuf is
1824 * queued the TxD ring
1825 */
queue_txd_mb(smc,mb)1826 static void queue_txd_mb(smc,mb)
1827 struct s_smc *smc ;
1828 SMbuf *mb ;
1829 {
1830 DB_GEN("_rx: queue_txd_mb = %x",(void *)mb,0,4) ;
1831 smc->os.hwm.queued_txd_mb++ ;
1832 mb->sm_next = (SMbuf *)NULL ;
1833 if (smc->os.hwm.txd_tx_pipe == 0) {
1834 smc->os.hwm.txd_tx_pipe = mb ;
1835 }
1836 else {
1837 smc->os.hwm.txd_tx_tail->sm_next = mb ;
1838 }
1839 smc->os.hwm.txd_tx_tail = mb ;
1840 }
1841
1842 /*
1843 * get a SMbuf from the txd_tx_queue
1844 */
get_txd_mb(smc)1845 static SMbuf *get_txd_mb(smc)
1846 struct s_smc *smc ;
1847 {
1848 SMbuf *mb ;
1849
1850 if ((mb = smc->os.hwm.txd_tx_pipe)) {
1851 smc->os.hwm.queued_txd_mb-- ;
1852 smc->os.hwm.txd_tx_pipe = mb->sm_next ;
1853 }
1854 DB_GEN("get_txd_mb: mb = 0x%x",(void *)mb,0,4) ;
1855 return(mb) ;
1856 }
1857
1858 /*
1859 * SMT Send function
1860 */
smt_send_mbuf(smc,mb,fc)1861 void smt_send_mbuf(smc,mb,fc)
1862 struct s_smc *smc;
1863 SMbuf *mb;
1864 int fc;
1865 {
1866 char far *data ;
1867 int len ;
1868 int n ;
1869 int i ;
1870 int frag_count ;
1871 int frame_status ;
1872 SK_LOC_DECL(char far,*virt[3]) ;
1873 int frag_len[3] ;
1874 struct s_smt_tx_queue *queue ;
1875 struct s_smt_fp_txd volatile *t ;
1876 u_long phys ;
1877 u_int tbctrl ;
1878
1879 NDD_TRACE("THSB",mb,fc,0) ;
1880 DB_TX("smt_send_mbuf: mb = 0x%x, fc = 0x%x",mb,fc,4) ;
1881
1882 mb->sm_off-- ; /* set to fc */
1883 mb->sm_len++ ; /* + fc */
1884 data = smtod(mb,char *) ;
1885 *data = fc ;
1886 if (fc == FC_SMT_LOC)
1887 *data = FC_SMT_INFO ;
1888
1889 /*
1890 * determine the frag count and the virt addresses of the frags
1891 */
1892 frag_count = 0 ;
1893 len = mb->sm_len ;
1894 while (len) {
1895 n = SMT_PAGESIZE - ((long)data & (SMT_PAGESIZE-1)) ;
1896 if (n >= len) {
1897 n = len ;
1898 }
1899 DB_TX("frag: virt/len = 0x%x/%d ",(void *)data,n,5) ;
1900 virt[frag_count] = data ;
1901 frag_len[frag_count] = n ;
1902 frag_count++ ;
1903 len -= n ;
1904 data += n ;
1905 }
1906
1907 /*
1908 * determine the frame status
1909 */
1910 queue = smc->hw.fp.tx[QUEUE_A0] ;
1911 if (fc == FC_BEACON || fc == FC_SMT_LOC) {
1912 frame_status = LOC_TX ;
1913 }
1914 else {
1915 frame_status = LAN_TX ;
1916 if ((smc->os.hwm.pass_NSA &&(fc == FC_SMT_NSA)) ||
1917 (smc->os.hwm.pass_SMT &&(fc == FC_SMT_INFO)))
1918 frame_status |= LOC_TX ;
1919 }
1920
1921 if (!smc->hw.mac_ring_is_up || frag_count > queue->tx_free) {
1922 if (frame_status &= ~LAN_TX) {
1923 DB_TX("Ring is down: terminate LAN_TX",0,0,2) ;
1924 }
1925 else {
1926 DB_TX("Ring is down: terminate transmission",0,0,2) ;
1927 smt_free_mbuf(smc,mb) ;
1928 return ;
1929 }
1930 }
1931 DB_TX("frame_status = 0x%x ",frame_status,0,5) ;
1932
1933 if ((frame_status & LAN_TX) && (frame_status & LOC_TX)) {
1934 mb->sm_use_count = 2 ;
1935 }
1936
1937 if (frame_status & LAN_TX) {
1938 t = queue->tx_curr_put ;
1939 frame_status |= FIRST_FRAG ;
1940 for (i = 0; i < frag_count; i++) {
1941 DB_TX("init TxD = 0x%x",(void *)t,0,5) ;
1942 if (i == frag_count-1) {
1943 frame_status |= LAST_FRAG ;
1944 t->txd_txdscr = AIX_REVERSE(TX_DESCRIPTOR |
1945 (((u_long)(mb->sm_len-1)&3) << 27)) ;
1946 }
1947 t->txd_virt = virt[i] ;
1948 phys = dma_master(smc, (void far *)virt[i],
1949 frag_len[i], DMA_RD|SMT_BUF) ;
1950 t->txd_tbadr = AIX_REVERSE(phys) ;
1951 tbctrl = AIX_REVERSE((((u_long) frame_status &
1952 (FIRST_FRAG|LAST_FRAG)) << 26) |
1953 BMU_OWN | BMU_CHECK | BMU_SMT_TX |frag_len[i]) ;
1954 t->txd_tbctrl = tbctrl ;
1955 #ifndef AIX
1956 DRV_BUF_FLUSH(t,DDI_DMA_SYNC_FORDEV) ;
1957 outpd(queue->tx_bmu_ctl,CSR_START) ;
1958 #else
1959 DRV_BUF_FLUSH(t,DDI_DMA_SYNC_FORDEV) ;
1960 outpd(ADDR(B0_XA_CSR),CSR_START) ;
1961 #endif
1962 frame_status &= ~FIRST_FRAG ;
1963 queue->tx_curr_put = t = t->txd_next ;
1964 queue->tx_free-- ;
1965 queue->tx_used++ ;
1966 }
1967 smc->mib.m[MAC0].fddiMACTransmit_Ct++ ;
1968 queue_txd_mb(smc,mb) ;
1969 }
1970
1971 if (frame_status & LOC_TX) {
1972 DB_TX("pass Mbuf to LLC queue",0,0,5) ;
1973 queue_llc_rx(smc,mb) ;
1974 }
1975
1976 /*
1977 * We need to unqueue the free SMT_MBUFs here, because it may
1978 * be that the SMT want's to send more than 1 frame for one down call
1979 */
1980 mac_drv_clear_txd(smc) ;
1981 NDD_TRACE("THSE",t,queue->tx_free,frag_count) ;
1982 }
1983
1984 /* BEGIN_MANUAL_ENTRY(mac_drv_clear_txd)
1985 * void mac_drv_clear_txd(smc)
1986 *
1987 * function DOWNCALL (hardware module, hwmtm.c)
1988 * mac_drv_clear_txd searches in both send queues for TxD's
1989 * which were finished by the adapter. It calls dma_complete
1990 * for each TxD. If the last fragment of an LLC frame is
1991 * reached, it calls mac_drv_tx_complete to release the
1992 * send buffer.
1993 *
1994 * return nothing
1995 *
1996 * END_MANUAL_ENTRY
1997 */
mac_drv_clear_txd(smc)1998 void mac_drv_clear_txd(smc)
1999 struct s_smc *smc ;
2000 {
2001 struct s_smt_tx_queue *queue ;
2002 struct s_smt_fp_txd volatile *t1 ;
2003 struct s_smt_fp_txd volatile *t2=0 ;
2004 SMbuf *mb ;
2005 u_long tbctrl ;
2006 int i ;
2007 int frag_count ;
2008 int n ;
2009
2010 NDD_TRACE("THcB",0,0,0) ;
2011 for (i = QUEUE_S; i <= QUEUE_A0; i++) {
2012 queue = smc->hw.fp.tx[i] ;
2013 t1 = queue->tx_curr_get ;
2014 DB_TX("clear_txd: QUEUE = %d (0=sync/1=async)",i,0,5) ;
2015
2016 for ( ; ; ) {
2017 frag_count = 0 ;
2018
2019 do {
2020 DRV_BUF_FLUSH(t1,DDI_DMA_SYNC_FORCPU) ;
2021 DB_TX("check OWN/EOF bit of TxD 0x%x",t1,0,5) ;
2022 tbctrl = CR_READ(t1->txd_tbctrl) ;
2023 tbctrl = AIX_REVERSE(tbctrl) ;
2024
2025 if (tbctrl & BMU_OWN || !queue->tx_used){
2026 DB_TX("End of TxDs queue %d",i,0,4) ;
2027 goto free_next_queue ; /* next queue */
2028 }
2029 t1 = t1->txd_next ;
2030 frag_count++ ;
2031 } while (!(tbctrl & BMU_EOF)) ;
2032
2033 t1 = queue->tx_curr_get ;
2034 for (n = frag_count; n; n--) {
2035 tbctrl = AIX_REVERSE(t1->txd_tbctrl) ;
2036 dma_complete(smc,
2037 (union s_fp_descr volatile *) t1,
2038 (int) (DMA_RD |
2039 ((tbctrl & BMU_SMT_TX) >> 18))) ;
2040 t2 = t1 ;
2041 t1 = t1->txd_next ;
2042 }
2043
2044 if (tbctrl & BMU_SMT_TX) {
2045 mb = get_txd_mb(smc) ;
2046 smt_free_mbuf(smc,mb) ;
2047 }
2048 else {
2049 #ifndef PASS_1ST_TXD_2_TX_COMP
2050 DB_TX("mac_drv_tx_comp for TxD 0x%x",t2,0,4) ;
2051 mac_drv_tx_complete(smc,t2) ;
2052 #else
2053 DB_TX("mac_drv_tx_comp for TxD 0x%x",
2054 queue->tx_curr_get,0,4) ;
2055 mac_drv_tx_complete(smc,queue->tx_curr_get) ;
2056 #endif
2057 }
2058 queue->tx_curr_get = t1 ;
2059 queue->tx_free += frag_count ;
2060 queue->tx_used -= frag_count ;
2061 }
2062 free_next_queue: ;
2063 }
2064 NDD_TRACE("THcE",0,0,0) ;
2065 }
2066
2067 /*
2068 * BEGINN_MANUAL_ENTRY(mac_drv_clear_tx_queue)
2069 *
2070 * void mac_drv_clear_tx_queue(smc)
2071 * struct s_smc *smc ;
2072 *
2073 * function DOWNCALL (hardware module, hwmtm.c)
2074 * mac_drv_clear_tx_queue is called from the SMT when
2075 * the RMT state machine has entered the ISOLATE state.
2076 * This function is also called by the os-specific module
2077 * after it has called the function card_stop().
2078 * In this case, the frames in the send queues are obsolete and
2079 * should be removed.
2080 *
2081 * note calling sequence:
2082 * CLI_FBI(), card_stop(),
2083 * mac_drv_clear_tx_queue(), mac_drv_clear_rx_queue(),
2084 *
2085 * NOTE: The caller is responsible that the BMUs are idle
2086 * when this function is called.
2087 *
2088 * END_MANUAL_ENTRY
2089 */
mac_drv_clear_tx_queue(smc)2090 void mac_drv_clear_tx_queue(smc)
2091 struct s_smc *smc ;
2092 {
2093 struct s_smt_fp_txd volatile *t ;
2094 struct s_smt_tx_queue *queue ;
2095 int tx_used ;
2096 int i ;
2097
2098 if (smc->hw.hw_state != STOPPED) {
2099 SK_BREAK() ;
2100 SMT_PANIC(smc,HWM_E0011,HWM_E0011_MSG) ;
2101 return ;
2102 }
2103
2104 for (i = QUEUE_S; i <= QUEUE_A0; i++) {
2105 queue = smc->hw.fp.tx[i] ;
2106 DB_TX("clear_tx_queue: QUEUE = %d (0=sync/1=async)",i,0,5) ;
2107
2108 /*
2109 * switch the OWN bit of all pending frames to the host
2110 */
2111 t = queue->tx_curr_get ;
2112 tx_used = queue->tx_used ;
2113 while (tx_used) {
2114 DRV_BUF_FLUSH(t,DDI_DMA_SYNC_FORCPU) ;
2115 DB_TX("switch OWN bit of TxD 0x%x ",t,0,5) ;
2116 t->txd_tbctrl &= AIX_REVERSE(~BMU_OWN) ;
2117 DRV_BUF_FLUSH(t,DDI_DMA_SYNC_FORDEV) ;
2118 t = t->txd_next ;
2119 tx_used-- ;
2120 }
2121 }
2122
2123 /*
2124 * release all TxD's for both send queues
2125 */
2126 mac_drv_clear_txd(smc) ;
2127
2128 for (i = QUEUE_S; i <= QUEUE_A0; i++) {
2129 queue = smc->hw.fp.tx[i] ;
2130 t = queue->tx_curr_get ;
2131
2132 /*
2133 * write the phys pointer of the NEXT descriptor into the
2134 * BMU's current address descriptor pointer and set
2135 * tx_curr_get and tx_curr_put to this position
2136 */
2137 if (i == QUEUE_S) {
2138 outpd(ADDR(B5_XS_DA),AIX_REVERSE(t->txd_ntdadr)) ;
2139 }
2140 else {
2141 outpd(ADDR(B5_XA_DA),AIX_REVERSE(t->txd_ntdadr)) ;
2142 }
2143
2144 queue->tx_curr_put = queue->tx_curr_get->txd_next ;
2145 queue->tx_curr_get = queue->tx_curr_put ;
2146 }
2147 }
2148
2149
2150 /*
2151 -------------------------------------------------------------
2152 TEST FUNCTIONS:
2153 -------------------------------------------------------------
2154 */
2155
2156 #ifdef DEBUG
2157 /*
2158 * BEGIN_MANUAL_ENTRY(mac_drv_debug_lev)
2159 * void mac_drv_debug_lev(smc,flag,lev)
2160 *
2161 * function DOWNCALL (drvsr.c)
2162 * To get a special debug info the user can assign a debug level
2163 * to any debug flag.
2164 *
2165 * para flag debug flag, possible values are:
2166 * = 0: reset all debug flags (the defined level is
2167 * ignored)
2168 * = 1: debug.d_smtf
2169 * = 2: debug.d_smt
2170 * = 3: debug.d_ecm
2171 * = 4: debug.d_rmt
2172 * = 5: debug.d_cfm
2173 * = 6: debug.d_pcm
2174 *
2175 * = 10: debug.d_os.hwm_rx (hardware module receive path)
2176 * = 11: debug.d_os.hwm_tx(hardware module transmit path)
2177 * = 12: debug.d_os.hwm_gen(hardware module general flag)
2178 *
2179 * lev debug level
2180 *
2181 * END_MANUAL_ENTRY
2182 */
mac_drv_debug_lev(smc,flag,lev)2183 void mac_drv_debug_lev(smc,flag,lev)
2184 struct s_smc *smc ;
2185 int flag ;
2186 int lev ;
2187 {
2188 switch(flag) {
2189 case (int)NULL:
2190 DB_P.d_smtf = DB_P.d_smt = DB_P.d_ecm = DB_P.d_rmt = 0 ;
2191 DB_P.d_cfm = 0 ;
2192 DB_P.d_os.hwm_rx = DB_P.d_os.hwm_tx = DB_P.d_os.hwm_gen = 0 ;
2193 #ifdef SBA
2194 DB_P.d_sba = 0 ;
2195 #endif
2196 #ifdef ESS
2197 DB_P.d_ess = 0 ;
2198 #endif
2199 break ;
2200 case DEBUG_SMTF:
2201 DB_P.d_smtf = lev ;
2202 break ;
2203 case DEBUG_SMT:
2204 DB_P.d_smt = lev ;
2205 break ;
2206 case DEBUG_ECM:
2207 DB_P.d_ecm = lev ;
2208 break ;
2209 case DEBUG_RMT:
2210 DB_P.d_rmt = lev ;
2211 break ;
2212 case DEBUG_CFM:
2213 DB_P.d_cfm = lev ;
2214 break ;
2215 case DEBUG_PCM:
2216 DB_P.d_pcm = lev ;
2217 break ;
2218 case DEBUG_SBA:
2219 #ifdef SBA
2220 DB_P.d_sba = lev ;
2221 #endif
2222 break ;
2223 case DEBUG_ESS:
2224 #ifdef ESS
2225 DB_P.d_ess = lev ;
2226 #endif
2227 break ;
2228 case DB_HWM_RX:
2229 DB_P.d_os.hwm_rx = lev ;
2230 break ;
2231 case DB_HWM_TX:
2232 DB_P.d_os.hwm_tx = lev ;
2233 break ;
2234 case DB_HWM_GEN:
2235 DB_P.d_os.hwm_gen = lev ;
2236 break ;
2237 default:
2238 break ;
2239 }
2240 }
2241 #endif
2242