1 /******************************************************************************
2 *
3 * Name: skgeinit.c
4 * Project: Gigabit Ethernet Adapters, Common Modules
5 * Purpose: Contains functions to initialize the adapter
6 *
7 ******************************************************************************/
8
9 /******************************************************************************
10 *
11 * (C)Copyright 1998-2002 SysKonnect.
12 * (C)Copyright 2002-2003 Marvell.
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
18 *
19 * The information in this file is provided "AS IS" without warranty.
20 *
21 ******************************************************************************/
22
23
24 #include "h/skdrv1st.h"
25 #include "h/skdrv2nd.h"
26
27 /* global variables ***********************************************************/
28
29 /* local variables ************************************************************/
30
31 #if (defined(DEBUG) || ((!defined(LINT)) && (!defined(SK_SLIM))))
32 static const char SysKonnectFileId[] =
33 "@(#) $Id: skgeinit.c,v 1.97 2003/10/02 16:45:31 rschmidt Exp $ (C) Marvell.";
34 #endif
35
36 struct s_QOffTab {
37 int RxQOff; /* Receive Queue Address Offset */
38 int XsQOff; /* Sync Tx Queue Address Offset */
39 int XaQOff; /* Async Tx Queue Address Offset */
40 };
41 static struct s_QOffTab QOffTab[] = {
42 {Q_R1, Q_XS1, Q_XA1}, {Q_R2, Q_XS2, Q_XA2}
43 };
44
45 struct s_Config {
46 char ScanString[8];
47 SK_U32 Value;
48 };
49
50 static struct s_Config OemConfig = {
51 {'O','E','M','_','C','o','n','f'},
52 #ifdef SK_OEM_CONFIG
53 OEM_CONFIG_VALUE,
54 #else
55 0,
56 #endif
57 };
58
59 /******************************************************************************
60 *
61 * SkGePollRxD() - Enable / Disable Descriptor Polling of RxD Ring
62 *
63 * Description:
64 * Enable or disable the descriptor polling of the receive descriptor
65 * ring (RxD) for port 'Port'.
66 * The new configuration is *not* saved over any SkGeStopPort() and
67 * SkGeInitPort() calls.
68 *
69 * Returns:
70 * nothing
71 */
SkGePollRxD(SK_AC * pAC,SK_IOC IoC,int Port,SK_BOOL PollRxD)72 void SkGePollRxD(
73 SK_AC *pAC, /* adapter context */
74 SK_IOC IoC, /* IO context */
75 int Port, /* Port Index (MAC_1 + n) */
76 SK_BOOL PollRxD) /* SK_TRUE (enable pol.), SK_FALSE (disable pol.) */
77 {
78 SK_GEPORT *pPrt;
79
80 pPrt = &pAC->GIni.GP[Port];
81
82 SK_OUT32(IoC, Q_ADDR(pPrt->PRxQOff, Q_CSR), (PollRxD) ?
83 CSR_ENA_POL : CSR_DIS_POL);
84 } /* SkGePollRxD */
85
86
87 /******************************************************************************
88 *
89 * SkGePollTxD() - Enable / Disable Descriptor Polling of TxD Rings
90 *
91 * Description:
92 * Enable or disable the descriptor polling of the transmit descriptor
93 * ring(s) (TxD) for port 'Port'.
94 * The new configuration is *not* saved over any SkGeStopPort() and
95 * SkGeInitPort() calls.
96 *
97 * Returns:
98 * nothing
99 */
SkGePollTxD(SK_AC * pAC,SK_IOC IoC,int Port,SK_BOOL PollTxD)100 void SkGePollTxD(
101 SK_AC *pAC, /* adapter context */
102 SK_IOC IoC, /* IO context */
103 int Port, /* Port Index (MAC_1 + n) */
104 SK_BOOL PollTxD) /* SK_TRUE (enable pol.), SK_FALSE (disable pol.) */
105 {
106 SK_GEPORT *pPrt;
107 SK_U32 DWord;
108
109 pPrt = &pAC->GIni.GP[Port];
110
111 DWord = (SK_U32)(PollTxD ? CSR_ENA_POL : CSR_DIS_POL);
112
113 if (pPrt->PXSQSize != 0) {
114 SK_OUT32(IoC, Q_ADDR(pPrt->PXsQOff, Q_CSR), DWord);
115 }
116
117 if (pPrt->PXAQSize != 0) {
118 SK_OUT32(IoC, Q_ADDR(pPrt->PXaQOff, Q_CSR), DWord);
119 }
120 } /* SkGePollTxD */
121
122
123 /******************************************************************************
124 *
125 * SkGeYellowLED() - Switch the yellow LED on or off.
126 *
127 * Description:
128 * Switch the yellow LED on or off.
129 *
130 * Note:
131 * This function may be called any time after SkGeInit(Level 1).
132 *
133 * Returns:
134 * nothing
135 */
SkGeYellowLED(SK_AC * pAC,SK_IOC IoC,int State)136 void SkGeYellowLED(
137 SK_AC *pAC, /* adapter context */
138 SK_IOC IoC, /* IO context */
139 int State) /* yellow LED state, 0 = OFF, 0 != ON */
140 {
141 if (State == 0) {
142 /* Switch yellow LED OFF */
143 SK_OUT8(IoC, B0_LED, LED_STAT_OFF);
144 }
145 else {
146 /* Switch yellow LED ON */
147 SK_OUT8(IoC, B0_LED, LED_STAT_ON);
148 }
149 } /* SkGeYellowLED */
150
151
152 #if (!defined(SK_SLIM) || defined(GENESIS))
153 /******************************************************************************
154 *
155 * SkGeXmitLED() - Modify the Operational Mode of a transmission LED.
156 *
157 * Description:
158 * The Rx or Tx LED which is specified by 'Led' will be
159 * enabled, disabled or switched on in test mode.
160 *
161 * Note:
162 * 'Led' must contain the address offset of the LEDs INI register.
163 *
164 * Usage:
165 * SkGeXmitLED(pAC, IoC, MR_ADDR(Port, TX_LED_INI), SK_LED_ENA);
166 *
167 * Returns:
168 * nothing
169 */
SkGeXmitLED(SK_AC * pAC,SK_IOC IoC,int Led,int Mode)170 void SkGeXmitLED(
171 SK_AC *pAC, /* adapter context */
172 SK_IOC IoC, /* IO context */
173 int Led, /* offset to the LED Init Value register */
174 int Mode) /* Mode may be SK_LED_DIS, SK_LED_ENA, SK_LED_TST */
175 {
176 SK_U32 LedIni;
177
178 switch (Mode) {
179 case SK_LED_ENA:
180 LedIni = SK_XMIT_DUR * (SK_U32)pAC->GIni.GIHstClkFact / 100;
181 SK_OUT32(IoC, Led + XMIT_LED_INI, LedIni);
182 SK_OUT8(IoC, Led + XMIT_LED_CTRL, LED_START);
183 break;
184 case SK_LED_TST:
185 SK_OUT8(IoC, Led + XMIT_LED_TST, LED_T_ON);
186 SK_OUT32(IoC, Led + XMIT_LED_CNT, 100);
187 SK_OUT8(IoC, Led + XMIT_LED_CTRL, LED_START);
188 break;
189 case SK_LED_DIS:
190 default:
191 /*
192 * Do NOT stop the LED Timer here. The LED might be
193 * in on state. But it needs to go off.
194 */
195 SK_OUT32(IoC, Led + XMIT_LED_CNT, 0);
196 SK_OUT8(IoC, Led + XMIT_LED_TST, LED_T_OFF);
197 break;
198 }
199
200 /*
201 * 1000BT: The Transmit LED is driven by the PHY.
202 * But the default LED configuration is used for
203 * Level One and Broadcom PHYs.
204 * (Broadcom: It may be that PHY_B_PEC_EN_LTR has to be set.)
205 * (In this case it has to be added here. But we will see. XXX)
206 */
207 } /* SkGeXmitLED */
208 #endif /* !SK_SLIM || GENESIS */
209
210
211 /******************************************************************************
212 *
213 * DoCalcAddr() - Calculates the start and the end address of a queue.
214 *
215 * Description:
216 * This function calculates the start and the end address of a queue.
217 * Afterwards the 'StartVal' is incremented to the next start position.
218 * If the port is already initialized the calculated values
219 * will be checked against the configured values and an
220 * error will be returned, if they are not equal.
221 * If the port is not initialized the values will be written to
222 * *StartAdr and *EndAddr.
223 *
224 * Returns:
225 * 0: success
226 * 1: configuration error
227 */
DoCalcAddr(SK_AC * pAC,SK_GEPORT SK_FAR * pPrt,int QuSize,SK_U32 SK_FAR * StartVal,SK_U32 SK_FAR * QuStartAddr,SK_U32 SK_FAR * QuEndAddr)228 static int DoCalcAddr(
229 SK_AC *pAC, /* adapter context */
230 SK_GEPORT SK_FAR *pPrt, /* port index */
231 int QuSize, /* size of the queue to configure in kB */
232 SK_U32 SK_FAR *StartVal, /* start value for address calculation */
233 SK_U32 SK_FAR *QuStartAddr,/* start addr to calculate */
234 SK_U32 SK_FAR *QuEndAddr) /* end address to calculate */
235 {
236 SK_U32 EndVal;
237 SK_U32 NextStart;
238 int Rtv;
239
240 Rtv = 0;
241 if (QuSize == 0) {
242 EndVal = *StartVal;
243 NextStart = EndVal;
244 }
245 else {
246 EndVal = *StartVal + ((SK_U32)QuSize * 1024) - 1;
247 NextStart = EndVal + 1;
248 }
249
250 if (pPrt->PState >= SK_PRT_INIT) {
251 if (*StartVal != *QuStartAddr || EndVal != *QuEndAddr) {
252 Rtv = 1;
253 }
254 }
255 else {
256 *QuStartAddr = *StartVal;
257 *QuEndAddr = EndVal;
258 }
259
260 *StartVal = NextStart;
261 return(Rtv);
262 } /* DoCalcAddr */
263
264 /******************************************************************************
265 *
266 * SkGeInitAssignRamToQueues() - allocate default queue sizes
267 *
268 * Description:
269 * This function assigns the memory to the different queues and ports.
270 * When DualNet is set to SK_TRUE all ports get the same amount of memory.
271 * Otherwise the first port gets most of the memory and all the
272 * other ports just the required minimum.
273 * This function can only be called when pAC->GIni.GIRamSize and
274 * pAC->GIni.GIMacsFound have been initialized, usually this happens
275 * at init level 1
276 *
277 * Returns:
278 * 0 - ok
279 * 1 - invalid input values
280 * 2 - not enough memory
281 */
282
SkGeInitAssignRamToQueues(SK_AC * pAC,int ActivePort,SK_BOOL DualNet)283 int SkGeInitAssignRamToQueues(
284 SK_AC *pAC, /* Adapter context */
285 int ActivePort, /* Active Port in RLMT mode */
286 SK_BOOL DualNet) /* adapter context */
287 {
288 int i;
289 int UsedKilobytes; /* memory already assigned */
290 int ActivePortKilobytes; /* memory available for active port */
291 SK_GEPORT *pGePort;
292
293 UsedKilobytes = 0;
294
295 if (ActivePort >= pAC->GIni.GIMacsFound) {
296 SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_INIT,
297 ("SkGeInitAssignRamToQueues: ActivePort (%d) invalid\n",
298 ActivePort));
299 return(1);
300 }
301 if (((pAC->GIni.GIMacsFound * (SK_MIN_RXQ_SIZE + SK_MIN_TXQ_SIZE)) +
302 ((RAM_QUOTA_SYNC == 0) ? 0 : SK_MIN_TXQ_SIZE)) > pAC->GIni.GIRamSize) {
303 SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_INIT,
304 ("SkGeInitAssignRamToQueues: Not enough memory (%d)\n",
305 pAC->GIni.GIRamSize));
306 return(2);
307 }
308
309 if (DualNet) {
310 /* every port gets the same amount of memory */
311 ActivePortKilobytes = pAC->GIni.GIRamSize / pAC->GIni.GIMacsFound;
312 for (i = 0; i < pAC->GIni.GIMacsFound; i++) {
313
314 pGePort = &pAC->GIni.GP[i];
315
316 /* take away the minimum memory for active queues */
317 ActivePortKilobytes -= (SK_MIN_RXQ_SIZE + SK_MIN_TXQ_SIZE);
318
319 /* receive queue gets the minimum + 80% of the rest */
320 pGePort->PRxQSize = (int) (ROUND_QUEUE_SIZE_KB((
321 ActivePortKilobytes * (unsigned long) RAM_QUOTA_RX) / 100))
322 + SK_MIN_RXQ_SIZE;
323
324 ActivePortKilobytes -= (pGePort->PRxQSize - SK_MIN_RXQ_SIZE);
325
326 /* synchronous transmit queue */
327 pGePort->PXSQSize = 0;
328
329 /* asynchronous transmit queue */
330 pGePort->PXAQSize = (int) ROUND_QUEUE_SIZE_KB(ActivePortKilobytes +
331 SK_MIN_TXQ_SIZE);
332 }
333 }
334 else {
335 /* Rlmt Mode or single link adapter */
336
337 /* Set standby queue size defaults for all standby ports */
338 for (i = 0; i < pAC->GIni.GIMacsFound; i++) {
339
340 if (i != ActivePort) {
341 pGePort = &pAC->GIni.GP[i];
342
343 pGePort->PRxQSize = SK_MIN_RXQ_SIZE;
344 pGePort->PXAQSize = SK_MIN_TXQ_SIZE;
345 pGePort->PXSQSize = 0;
346
347 /* Count used RAM */
348 UsedKilobytes += pGePort->PRxQSize + pGePort->PXAQSize;
349 }
350 }
351 /* what's left? */
352 ActivePortKilobytes = pAC->GIni.GIRamSize - UsedKilobytes;
353
354 /* assign it to the active port */
355 /* first take away the minimum memory */
356 ActivePortKilobytes -= (SK_MIN_RXQ_SIZE + SK_MIN_TXQ_SIZE);
357 pGePort = &pAC->GIni.GP[ActivePort];
358
359 /* receive queue get's the minimum + 80% of the rest */
360 pGePort->PRxQSize = (int) (ROUND_QUEUE_SIZE_KB((ActivePortKilobytes *
361 (unsigned long) RAM_QUOTA_RX) / 100)) + SK_MIN_RXQ_SIZE;
362
363 ActivePortKilobytes -= (pGePort->PRxQSize - SK_MIN_RXQ_SIZE);
364
365 /* synchronous transmit queue */
366 pGePort->PXSQSize = 0;
367
368 /* asynchronous transmit queue */
369 pGePort->PXAQSize = (int) ROUND_QUEUE_SIZE_KB(ActivePortKilobytes) +
370 SK_MIN_TXQ_SIZE;
371 }
372 #ifdef VCPU
373 VCPUprintf(0, "PRxQSize=%u, PXSQSize=%u, PXAQSize=%u\n",
374 pGePort->PRxQSize, pGePort->PXSQSize, pGePort->PXAQSize);
375 #endif /* VCPU */
376
377 return(0);
378 } /* SkGeInitAssignRamToQueues */
379
380 /******************************************************************************
381 *
382 * SkGeCheckQSize() - Checks the Adapters Queue Size Configuration
383 *
384 * Description:
385 * This function verifies the Queue Size Configuration specified
386 * in the variables PRxQSize, PXSQSize, and PXAQSize of all
387 * used ports.
388 * This requirements must be fullfilled to have a valid configuration:
389 * - The size of all queues must not exceed GIRamSize.
390 * - The queue sizes must be specified in units of 8 kB.
391 * - The size of Rx queues of available ports must not be
392 * smaller than 16 kB.
393 * - The size of at least one Tx queue (synch. or asynch.)
394 * of available ports must not be smaller than 16 kB
395 * when Jumbo Frames are used.
396 * - The RAM start and end addresses must not be changed
397 * for ports which are already initialized.
398 * Furthermore SkGeCheckQSize() defines the Start and End Addresses
399 * of all ports and stores them into the HWAC port structure.
400 *
401 * Returns:
402 * 0: Queue Size Configuration valid
403 * 1: Queue Size Configuration invalid
404 */
SkGeCheckQSize(SK_AC * pAC,int Port)405 static int SkGeCheckQSize(
406 SK_AC *pAC, /* adapter context */
407 int Port) /* port index */
408 {
409 SK_GEPORT *pPrt;
410 int i;
411 int Rtv;
412 int Rtv2;
413 SK_U32 StartAddr;
414 #ifndef SK_SLIM
415 int UsedMem; /* total memory used (max. found ports) */
416 #endif
417
418 Rtv = 0;
419
420 #ifndef SK_SLIM
421
422 UsedMem = 0;
423 for (i = 0; i < pAC->GIni.GIMacsFound; i++) {
424 pPrt = &pAC->GIni.GP[i];
425
426 if ((pPrt->PRxQSize & QZ_UNITS) != 0 ||
427 (pPrt->PXSQSize & QZ_UNITS) != 0 ||
428 (pPrt->PXAQSize & QZ_UNITS) != 0) {
429
430 SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E012, SKERR_HWI_E012MSG);
431 return(1);
432 }
433
434 if (i == Port && pPrt->PRxQSize < SK_MIN_RXQ_SIZE) {
435 SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E011, SKERR_HWI_E011MSG);
436 return(1);
437 }
438
439 /*
440 * the size of at least one Tx queue (synch. or asynch.) has to be > 0.
441 * if Jumbo Frames are used, this size has to be >= 16 kB.
442 */
443 if ((i == Port && pPrt->PXSQSize == 0 && pPrt->PXAQSize == 0) ||
444 (pAC->GIni.GIPortUsage == SK_JUMBO_LINK &&
445 ((pPrt->PXSQSize > 0 && pPrt->PXSQSize < SK_MIN_TXQ_SIZE) ||
446 (pPrt->PXAQSize > 0 && pPrt->PXAQSize < SK_MIN_TXQ_SIZE)))) {
447 SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E023, SKERR_HWI_E023MSG);
448 return(1);
449 }
450
451 UsedMem += pPrt->PRxQSize + pPrt->PXSQSize + pPrt->PXAQSize;
452 }
453
454 if (UsedMem > pAC->GIni.GIRamSize) {
455 SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E012, SKERR_HWI_E012MSG);
456 return(1);
457 }
458 #endif /* !SK_SLIM */
459
460 /* Now start address calculation */
461 StartAddr = pAC->GIni.GIRamOffs;
462 for (i = 0; i < pAC->GIni.GIMacsFound; i++) {
463 pPrt = &pAC->GIni.GP[i];
464
465 /* Calculate/Check values for the receive queue */
466 Rtv2 = DoCalcAddr(pAC, pPrt, pPrt->PRxQSize, &StartAddr,
467 &pPrt->PRxQRamStart, &pPrt->PRxQRamEnd);
468 Rtv |= Rtv2;
469
470 /* Calculate/Check values for the synchronous Tx queue */
471 Rtv2 = DoCalcAddr(pAC, pPrt, pPrt->PXSQSize, &StartAddr,
472 &pPrt->PXsQRamStart, &pPrt->PXsQRamEnd);
473 Rtv |= Rtv2;
474
475 /* Calculate/Check values for the asynchronous Tx queue */
476 Rtv2 = DoCalcAddr(pAC, pPrt, pPrt->PXAQSize, &StartAddr,
477 &pPrt->PXaQRamStart, &pPrt->PXaQRamEnd);
478 Rtv |= Rtv2;
479
480 if (Rtv) {
481 SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E013, SKERR_HWI_E013MSG);
482 return(1);
483 }
484 }
485
486 return(0);
487 } /* SkGeCheckQSize */
488
489
490 #ifdef GENESIS
491 /******************************************************************************
492 *
493 * SkGeInitMacArb() - Initialize the MAC Arbiter
494 *
495 * Description:
496 * This function initializes the MAC Arbiter.
497 * It must not be called if there is still an
498 * initialized or active port.
499 *
500 * Returns:
501 * nothing
502 */
SkGeInitMacArb(SK_AC * pAC,SK_IOC IoC)503 static void SkGeInitMacArb(
504 SK_AC *pAC, /* adapter context */
505 SK_IOC IoC) /* IO context */
506 {
507 /* release local reset */
508 SK_OUT16(IoC, B3_MA_TO_CTRL, MA_RST_CLR);
509
510 /* configure timeout values */
511 SK_OUT8(IoC, B3_MA_TOINI_RX1, SK_MAC_TO_53);
512 SK_OUT8(IoC, B3_MA_TOINI_RX2, SK_MAC_TO_53);
513 SK_OUT8(IoC, B3_MA_TOINI_TX1, SK_MAC_TO_53);
514 SK_OUT8(IoC, B3_MA_TOINI_TX2, SK_MAC_TO_53);
515
516 SK_OUT8(IoC, B3_MA_RCINI_RX1, 0);
517 SK_OUT8(IoC, B3_MA_RCINI_RX2, 0);
518 SK_OUT8(IoC, B3_MA_RCINI_TX1, 0);
519 SK_OUT8(IoC, B3_MA_RCINI_TX2, 0);
520
521 /* recovery values are needed for XMAC II Rev. B2 only */
522 /* Fast Output Enable Mode was intended to use with Rev. B2, but now? */
523
524 /*
525 * There is no start or enable button to push, therefore
526 * the MAC arbiter is configured and enabled now.
527 */
528 } /* SkGeInitMacArb */
529
530
531 /******************************************************************************
532 *
533 * SkGeInitPktArb() - Initialize the Packet Arbiter
534 *
535 * Description:
536 * This function initializes the Packet Arbiter.
537 * It must not be called if there is still an
538 * initialized or active port.
539 *
540 * Returns:
541 * nothing
542 */
SkGeInitPktArb(SK_AC * pAC,SK_IOC IoC)543 static void SkGeInitPktArb(
544 SK_AC *pAC, /* adapter context */
545 SK_IOC IoC) /* IO context */
546 {
547 /* release local reset */
548 SK_OUT16(IoC, B3_PA_CTRL, PA_RST_CLR);
549
550 /* configure timeout values */
551 SK_OUT16(IoC, B3_PA_TOINI_RX1, SK_PKT_TO_MAX);
552 SK_OUT16(IoC, B3_PA_TOINI_RX2, SK_PKT_TO_MAX);
553 SK_OUT16(IoC, B3_PA_TOINI_TX1, SK_PKT_TO_MAX);
554 SK_OUT16(IoC, B3_PA_TOINI_TX2, SK_PKT_TO_MAX);
555
556 /*
557 * enable timeout timers if jumbo frames not used
558 * NOTE: the packet arbiter timeout interrupt is needed for
559 * half duplex hangup workaround
560 */
561 if (pAC->GIni.GIPortUsage != SK_JUMBO_LINK) {
562 if (pAC->GIni.GIMacsFound == 1) {
563 SK_OUT16(IoC, B3_PA_CTRL, PA_ENA_TO_TX1);
564 }
565 else {
566 SK_OUT16(IoC, B3_PA_CTRL, PA_ENA_TO_TX1 | PA_ENA_TO_TX2);
567 }
568 }
569 } /* SkGeInitPktArb */
570 #endif /* GENESIS */
571
572
573 /******************************************************************************
574 *
575 * SkGeInitMacFifo() - Initialize the MAC FIFOs
576 *
577 * Description:
578 * Initialize all MAC FIFOs of the specified port
579 *
580 * Returns:
581 * nothing
582 */
SkGeInitMacFifo(SK_AC * pAC,SK_IOC IoC,int Port)583 static void SkGeInitMacFifo(
584 SK_AC *pAC, /* adapter context */
585 SK_IOC IoC, /* IO context */
586 int Port) /* Port Index (MAC_1 + n) */
587 {
588 SK_U16 Word;
589 #ifdef VCPU
590 SK_U32 DWord;
591 #endif /* VCPU */
592 /*
593 * For each FIFO:
594 * - release local reset
595 * - use default value for MAC FIFO size
596 * - setup defaults for the control register
597 * - enable the FIFO
598 */
599
600 #ifdef GENESIS
601 if (pAC->GIni.GIGenesis) {
602 /* Configure Rx MAC FIFO */
603 SK_OUT8(IoC, MR_ADDR(Port, RX_MFF_CTRL2), MFF_RST_CLR);
604 SK_OUT16(IoC, MR_ADDR(Port, RX_MFF_CTRL1), MFF_RX_CTRL_DEF);
605 SK_OUT8(IoC, MR_ADDR(Port, RX_MFF_CTRL2), MFF_ENA_OP_MD);
606
607 /* Configure Tx MAC FIFO */
608 SK_OUT8(IoC, MR_ADDR(Port, TX_MFF_CTRL2), MFF_RST_CLR);
609 SK_OUT16(IoC, MR_ADDR(Port, TX_MFF_CTRL1), MFF_TX_CTRL_DEF);
610 SK_OUT8(IoC, MR_ADDR(Port, TX_MFF_CTRL2), MFF_ENA_OP_MD);
611
612 /* Enable frame flushing if jumbo frames used */
613 if (pAC->GIni.GIPortUsage == SK_JUMBO_LINK) {
614 SK_OUT16(IoC, MR_ADDR(Port, RX_MFF_CTRL1), MFF_ENA_FLUSH);
615 }
616 }
617 #endif /* GENESIS */
618
619 #ifdef YUKON
620 if (pAC->GIni.GIYukon) {
621 /* set Rx GMAC FIFO Flush Mask */
622 SK_OUT16(IoC, MR_ADDR(Port, RX_GMF_FL_MSK), (SK_U16)RX_FF_FL_DEF_MSK);
623
624 Word = (SK_U16)GMF_RX_CTRL_DEF;
625
626 /* disable Rx GMAC FIFO Flush for YUKON-Lite Rev. A0 only */
627 if (pAC->GIni.GIYukonLite && pAC->GIni.GIChipId == CHIP_ID_YUKON) {
628
629 Word &= ~GMF_RX_F_FL_ON;
630 }
631
632 /* Configure Rx MAC FIFO */
633 SK_OUT8(IoC, MR_ADDR(Port, RX_GMF_CTRL_T), (SK_U8)GMF_RST_CLR);
634 SK_OUT16(IoC, MR_ADDR(Port, RX_GMF_CTRL_T), Word);
635
636 /* set Rx GMAC FIFO Flush Threshold (default: 0x0a -> 56 bytes) */
637 SK_OUT16(IoC, MR_ADDR(Port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF);
638
639 /* Configure Tx MAC FIFO */
640 SK_OUT8(IoC, MR_ADDR(Port, TX_GMF_CTRL_T), (SK_U8)GMF_RST_CLR);
641 SK_OUT16(IoC, MR_ADDR(Port, TX_GMF_CTRL_T), (SK_U16)GMF_TX_CTRL_DEF);
642
643 #ifdef VCPU
644 SK_IN32(IoC, MR_ADDR(Port, RX_GMF_AF_THR), &DWord);
645 SK_IN32(IoC, MR_ADDR(Port, TX_GMF_AE_THR), &DWord);
646 #endif /* VCPU */
647
648 /* set Tx GMAC FIFO Almost Empty Threshold */
649 /* SK_OUT32(IoC, MR_ADDR(Port, TX_GMF_AE_THR), 0); */
650 }
651 #endif /* YUKON */
652
653 } /* SkGeInitMacFifo */
654
655 #ifdef SK_LNK_SYNC_CNT
656 /******************************************************************************
657 *
658 * SkGeLoadLnkSyncCnt() - Load the Link Sync Counter and starts counting
659 *
660 * Description:
661 * This function starts the Link Sync Counter of the specified
662 * port and enables the generation of an Link Sync IRQ.
663 * The Link Sync Counter may be used to detect an active link,
664 * if autonegotiation is not used.
665 *
666 * Note:
667 * o To ensure receiving the Link Sync Event the LinkSyncCounter
668 * should be initialized BEFORE clearing the XMAC's reset!
669 * o Enable IS_LNK_SYNC_M1 and IS_LNK_SYNC_M2 after calling this
670 * function.
671 *
672 * Returns:
673 * nothing
674 */
SkGeLoadLnkSyncCnt(SK_AC * pAC,SK_IOC IoC,int Port,SK_U32 CntVal)675 void SkGeLoadLnkSyncCnt(
676 SK_AC *pAC, /* adapter context */
677 SK_IOC IoC, /* IO context */
678 int Port, /* Port Index (MAC_1 + n) */
679 SK_U32 CntVal) /* Counter value */
680 {
681 SK_U32 OrgIMsk;
682 SK_U32 NewIMsk;
683 SK_U32 ISrc;
684 SK_BOOL IrqPend;
685
686 /* stop counter */
687 SK_OUT8(IoC, MR_ADDR(Port, LNK_SYNC_CTRL), LED_STOP);
688
689 /*
690 * ASIC problem:
691 * Each time starting the Link Sync Counter an IRQ is generated
692 * by the adapter. See problem report entry from 21.07.98
693 *
694 * Workaround: Disable Link Sync IRQ and clear the unexpeced IRQ
695 * if no IRQ is already pending.
696 */
697 IrqPend = SK_FALSE;
698 SK_IN32(IoC, B0_ISRC, &ISrc);
699 SK_IN32(IoC, B0_IMSK, &OrgIMsk);
700 if (Port == MAC_1) {
701 NewIMsk = OrgIMsk & ~IS_LNK_SYNC_M1;
702 if ((ISrc & IS_LNK_SYNC_M1) != 0) {
703 IrqPend = SK_TRUE;
704 }
705 }
706 else {
707 NewIMsk = OrgIMsk & ~IS_LNK_SYNC_M2;
708 if ((ISrc & IS_LNK_SYNC_M2) != 0) {
709 IrqPend = SK_TRUE;
710 }
711 }
712 if (!IrqPend) {
713 SK_OUT32(IoC, B0_IMSK, NewIMsk);
714 }
715
716 /* load counter */
717 SK_OUT32(IoC, MR_ADDR(Port, LNK_SYNC_INI), CntVal);
718
719 /* start counter */
720 SK_OUT8(IoC, MR_ADDR(Port, LNK_SYNC_CTRL), LED_START);
721
722 if (!IrqPend) {
723 /* clear the unexpected IRQ, and restore the interrupt mask */
724 SK_OUT8(IoC, MR_ADDR(Port, LNK_SYNC_CTRL), LED_CLR_IRQ);
725 SK_OUT32(IoC, B0_IMSK, OrgIMsk);
726 }
727 } /* SkGeLoadLnkSyncCnt*/
728 #endif /* SK_LNK_SYNC_CNT */
729
730 #if defined(SK_DIAG) || defined(SK_CFG_SYNC)
731 /******************************************************************************
732 *
733 * SkGeCfgSync() - Configure synchronous bandwidth for this port.
734 *
735 * Description:
736 * This function may be used to configure synchronous bandwidth
737 * to the specified port. This may be done any time after
738 * initializing the port. The configuration values are NOT saved
739 * in the HWAC port structure and will be overwritten any
740 * time when stopping and starting the port.
741 * Any values for the synchronous configuration will be ignored
742 * if the size of the synchronous queue is zero!
743 *
744 * The default configuration for the synchronous service is
745 * TXA_ENA_FSYNC. This means if the size of
746 * the synchronous queue is unequal zero but no specific
747 * synchronous bandwidth is configured, the synchronous queue
748 * will always have the 'unlimited' transmit priority!
749 *
750 * This mode will be restored if the synchronous bandwidth is
751 * deallocated ('IntTime' = 0 and 'LimCount' = 0).
752 *
753 * Returns:
754 * 0: success
755 * 1: parameter configuration error
756 * 2: try to configure quality of service although no
757 * synchronous queue is configured
758 */
SkGeCfgSync(SK_AC * pAC,SK_IOC IoC,int Port,SK_U32 IntTime,SK_U32 LimCount,int SyncMode)759 int SkGeCfgSync(
760 SK_AC *pAC, /* adapter context */
761 SK_IOC IoC, /* IO context */
762 int Port, /* Port Index (MAC_1 + n) */
763 SK_U32 IntTime, /* Interval Timer Value in units of 8ns */
764 SK_U32 LimCount, /* Number of bytes to transfer during IntTime */
765 int SyncMode) /* Sync Mode: TXA_ENA_ALLOC | TXA_DIS_ALLOC | 0 */
766 {
767 int Rtv;
768
769 Rtv = 0;
770
771 /* check the parameters */
772 if (LimCount > IntTime ||
773 (LimCount == 0 && IntTime != 0) ||
774 (LimCount != 0 && IntTime == 0)) {
775
776 SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E010, SKERR_HWI_E010MSG);
777 return(1);
778 }
779
780 if (pAC->GIni.GP[Port].PXSQSize == 0) {
781 SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E009, SKERR_HWI_E009MSG);
782 return(2);
783 }
784
785 /* calculate register values */
786 IntTime = (IntTime / 2) * pAC->GIni.GIHstClkFact / 100;
787 LimCount = LimCount / 8;
788
789 if (IntTime > TXA_MAX_VAL || LimCount > TXA_MAX_VAL) {
790 SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E010, SKERR_HWI_E010MSG);
791 return(1);
792 }
793
794 /*
795 * - Enable 'Force Sync' to ensure the synchronous queue
796 * has the priority while configuring the new values.
797 * - Also 'disable alloc' to ensure the settings complies
798 * to the SyncMode parameter.
799 * - Disable 'Rate Control' to configure the new values.
800 * - write IntTime and LimCount
801 * - start 'Rate Control' and disable 'Force Sync'
802 * if Interval Timer or Limit Counter not zero.
803 */
804 SK_OUT8(IoC, MR_ADDR(Port, TXA_CTRL),
805 TXA_ENA_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
806
807 SK_OUT32(IoC, MR_ADDR(Port, TXA_ITI_INI), IntTime);
808 SK_OUT32(IoC, MR_ADDR(Port, TXA_LIM_INI), LimCount);
809
810 SK_OUT8(IoC, MR_ADDR(Port, TXA_CTRL),
811 (SK_U8)(SyncMode & (TXA_ENA_ALLOC | TXA_DIS_ALLOC)));
812
813 if (IntTime != 0 || LimCount != 0) {
814 SK_OUT8(IoC, MR_ADDR(Port, TXA_CTRL), TXA_DIS_FSYNC | TXA_START_RC);
815 }
816
817 return(0);
818 } /* SkGeCfgSync */
819 #endif /* SK_DIAG || SK_CFG_SYNC*/
820
821
822 /******************************************************************************
823 *
824 * DoInitRamQueue() - Initialize the RAM Buffer Address of a single Queue
825 *
826 * Desccription:
827 * If the queue is used, enable and initialize it.
828 * Make sure the queue is still reset, if it is not used.
829 *
830 * Returns:
831 * nothing
832 */
DoInitRamQueue(SK_AC * pAC,SK_IOC IoC,int QuIoOffs,SK_U32 QuStartAddr,SK_U32 QuEndAddr,int QuType)833 static void DoInitRamQueue(
834 SK_AC *pAC, /* adapter context */
835 SK_IOC IoC, /* IO context */
836 int QuIoOffs, /* Queue IO Address Offset */
837 SK_U32 QuStartAddr, /* Queue Start Address */
838 SK_U32 QuEndAddr, /* Queue End Address */
839 int QuType) /* Queue Type (SK_RX_SRAM_Q|SK_RX_BRAM_Q|SK_TX_RAM_Q) */
840 {
841 SK_U32 RxUpThresVal;
842 SK_U32 RxLoThresVal;
843
844 if (QuStartAddr != QuEndAddr) {
845 /* calculate thresholds, assume we have a big Rx queue */
846 RxUpThresVal = (QuEndAddr + 1 - QuStartAddr - SK_RB_ULPP) / 8;
847 RxLoThresVal = (QuEndAddr + 1 - QuStartAddr - SK_RB_LLPP_B)/8;
848
849 /* build HW address format */
850 QuStartAddr = QuStartAddr / 8;
851 QuEndAddr = QuEndAddr / 8;
852
853 /* release local reset */
854 SK_OUT8(IoC, RB_ADDR(QuIoOffs, RB_CTRL), RB_RST_CLR);
855
856 /* configure addresses */
857 SK_OUT32(IoC, RB_ADDR(QuIoOffs, RB_START), QuStartAddr);
858 SK_OUT32(IoC, RB_ADDR(QuIoOffs, RB_END), QuEndAddr);
859 SK_OUT32(IoC, RB_ADDR(QuIoOffs, RB_WP), QuStartAddr);
860 SK_OUT32(IoC, RB_ADDR(QuIoOffs, RB_RP), QuStartAddr);
861
862 switch (QuType) {
863 case SK_RX_SRAM_Q:
864 /* configure threshold for small Rx Queue */
865 RxLoThresVal += (SK_RB_LLPP_B - SK_RB_LLPP_S) / 8;
866
867 /* continue with SK_RX_BRAM_Q */
868 case SK_RX_BRAM_Q:
869 /* write threshold for Rx Queue */
870
871 SK_OUT32(IoC, RB_ADDR(QuIoOffs, RB_RX_UTPP), RxUpThresVal);
872 SK_OUT32(IoC, RB_ADDR(QuIoOffs, RB_RX_LTPP), RxLoThresVal);
873
874 /* the high priority threshold not used */
875 break;
876 case SK_TX_RAM_Q:
877 /*
878 * Do NOT use Store & Forward under normal operation due to
879 * performance optimization (GENESIS only).
880 * But if Jumbo Frames are configured (XMAC Tx FIFO is only 4 kB)
881 * or YUKON is used ((GMAC Tx FIFO is only 1 kB)
882 * we NEED Store & Forward of the RAM buffer.
883 */
884 if (pAC->GIni.GIPortUsage == SK_JUMBO_LINK ||
885 pAC->GIni.GIYukon) {
886 /* enable Store & Forward Mode for the Tx Side */
887 SK_OUT8(IoC, RB_ADDR(QuIoOffs, RB_CTRL), RB_ENA_STFWD);
888 }
889 break;
890 }
891
892 /* set queue operational */
893 SK_OUT8(IoC, RB_ADDR(QuIoOffs, RB_CTRL), RB_ENA_OP_MD);
894 }
895 else {
896 /* ensure the queue is still disabled */
897 SK_OUT8(IoC, RB_ADDR(QuIoOffs, RB_CTRL), RB_RST_SET);
898 }
899 } /* DoInitRamQueue */
900
901
902 /******************************************************************************
903 *
904 * SkGeInitRamBufs() - Initialize the RAM Buffer Queues
905 *
906 * Description:
907 * Initialize all RAM Buffer Queues of the specified port
908 *
909 * Returns:
910 * nothing
911 */
SkGeInitRamBufs(SK_AC * pAC,SK_IOC IoC,int Port)912 static void SkGeInitRamBufs(
913 SK_AC *pAC, /* adapter context */
914 SK_IOC IoC, /* IO context */
915 int Port) /* Port Index (MAC_1 + n) */
916 {
917 SK_GEPORT *pPrt;
918 int RxQType;
919
920 pPrt = &pAC->GIni.GP[Port];
921
922 if (pPrt->PRxQSize == SK_MIN_RXQ_SIZE) {
923 RxQType = SK_RX_SRAM_Q; /* small Rx Queue */
924 }
925 else {
926 RxQType = SK_RX_BRAM_Q; /* big Rx Queue */
927 }
928
929 DoInitRamQueue(pAC, IoC, pPrt->PRxQOff, pPrt->PRxQRamStart,
930 pPrt->PRxQRamEnd, RxQType);
931
932 DoInitRamQueue(pAC, IoC, pPrt->PXsQOff, pPrt->PXsQRamStart,
933 pPrt->PXsQRamEnd, SK_TX_RAM_Q);
934
935 DoInitRamQueue(pAC, IoC, pPrt->PXaQOff, pPrt->PXaQRamStart,
936 pPrt->PXaQRamEnd, SK_TX_RAM_Q);
937
938 } /* SkGeInitRamBufs */
939
940
941 /******************************************************************************
942 *
943 * SkGeInitRamIface() - Initialize the RAM Interface
944 *
945 * Description:
946 * This function initializes the Adapters RAM Interface.
947 *
948 * Note:
949 * This function is used in the diagnostics.
950 *
951 * Returns:
952 * nothing
953 */
SkGeInitRamIface(SK_AC * pAC,SK_IOC IoC)954 void SkGeInitRamIface(
955 SK_AC *pAC, /* adapter context */
956 SK_IOC IoC) /* IO context */
957 {
958 /* release local reset */
959 SK_OUT16(IoC, B3_RI_CTRL, RI_RST_CLR);
960
961 /* configure timeout values */
962 SK_OUT8(IoC, B3_RI_WTO_R1, SK_RI_TO_53);
963 SK_OUT8(IoC, B3_RI_WTO_XA1, SK_RI_TO_53);
964 SK_OUT8(IoC, B3_RI_WTO_XS1, SK_RI_TO_53);
965 SK_OUT8(IoC, B3_RI_RTO_R1, SK_RI_TO_53);
966 SK_OUT8(IoC, B3_RI_RTO_XA1, SK_RI_TO_53);
967 SK_OUT8(IoC, B3_RI_RTO_XS1, SK_RI_TO_53);
968 SK_OUT8(IoC, B3_RI_WTO_R2, SK_RI_TO_53);
969 SK_OUT8(IoC, B3_RI_WTO_XA2, SK_RI_TO_53);
970 SK_OUT8(IoC, B3_RI_WTO_XS2, SK_RI_TO_53);
971 SK_OUT8(IoC, B3_RI_RTO_R2, SK_RI_TO_53);
972 SK_OUT8(IoC, B3_RI_RTO_XA2, SK_RI_TO_53);
973 SK_OUT8(IoC, B3_RI_RTO_XS2, SK_RI_TO_53);
974
975 } /* SkGeInitRamIface */
976
977
978 /******************************************************************************
979 *
980 * SkGeInitBmu() - Initialize the BMU state machines
981 *
982 * Description:
983 * Initialize all BMU state machines of the specified port
984 *
985 * Returns:
986 * nothing
987 */
SkGeInitBmu(SK_AC * pAC,SK_IOC IoC,int Port)988 static void SkGeInitBmu(
989 SK_AC *pAC, /* adapter context */
990 SK_IOC IoC, /* IO context */
991 int Port) /* Port Index (MAC_1 + n) */
992 {
993 SK_GEPORT *pPrt;
994 SK_U32 RxWm;
995 SK_U32 TxWm;
996
997 pPrt = &pAC->GIni.GP[Port];
998
999 RxWm = SK_BMU_RX_WM;
1000 TxWm = SK_BMU_TX_WM;
1001
1002 if (!pAC->GIni.GIPciSlot64 && !pAC->GIni.GIPciClock66) {
1003 /* for better performance */
1004 RxWm /= 2;
1005 TxWm /= 2;
1006 }
1007
1008 /* Rx Queue: Release all local resets and set the watermark */
1009 SK_OUT32(IoC, Q_ADDR(pPrt->PRxQOff, Q_CSR), CSR_CLR_RESET);
1010 SK_OUT32(IoC, Q_ADDR(pPrt->PRxQOff, Q_F), RxWm);
1011
1012 /*
1013 * Tx Queue: Release all local resets if the queue is used !
1014 * set watermark
1015 */
1016 if (pPrt->PXSQSize != 0) {
1017 SK_OUT32(IoC, Q_ADDR(pPrt->PXsQOff, Q_CSR), CSR_CLR_RESET);
1018 SK_OUT32(IoC, Q_ADDR(pPrt->PXsQOff, Q_F), TxWm);
1019 }
1020
1021 if (pPrt->PXAQSize != 0) {
1022 SK_OUT32(IoC, Q_ADDR(pPrt->PXaQOff, Q_CSR), CSR_CLR_RESET);
1023 SK_OUT32(IoC, Q_ADDR(pPrt->PXaQOff, Q_F), TxWm);
1024 }
1025 /*
1026 * Do NOT enable the descriptor poll timers here, because
1027 * the descriptor addresses are not specified yet.
1028 */
1029 } /* SkGeInitBmu */
1030
1031
1032 /******************************************************************************
1033 *
1034 * TestStopBit() - Test the stop bit of the queue
1035 *
1036 * Description:
1037 * Stopping a queue is not as simple as it seems to be.
1038 * If descriptor polling is enabled, it may happen
1039 * that RX/TX stop is done and SV idle is NOT set.
1040 * In this case we have to issue another stop command.
1041 *
1042 * Returns:
1043 * The queues control status register
1044 */
TestStopBit(SK_AC * pAC,SK_IOC IoC,int QuIoOffs)1045 static SK_U32 TestStopBit(
1046 SK_AC *pAC, /* Adapter Context */
1047 SK_IOC IoC, /* IO Context */
1048 int QuIoOffs) /* Queue IO Address Offset */
1049 {
1050 SK_U32 QuCsr; /* CSR contents */
1051
1052 SK_IN32(IoC, Q_ADDR(QuIoOffs, Q_CSR), &QuCsr);
1053
1054 if ((QuCsr & (CSR_STOP | CSR_SV_IDLE)) == 0) {
1055 /* Stop Descriptor overridden by start command */
1056 SK_OUT32(IoC, Q_ADDR(QuIoOffs, Q_CSR), CSR_STOP);
1057
1058 SK_IN32(IoC, Q_ADDR(QuIoOffs, Q_CSR), &QuCsr);
1059 }
1060
1061 return(QuCsr);
1062 } /* TestStopBit */
1063
1064
1065 /******************************************************************************
1066 *
1067 * SkGeStopPort() - Stop the Rx/Tx activity of the port 'Port'.
1068 *
1069 * Description:
1070 * After calling this function the descriptor rings and Rx and Tx
1071 * queues of this port may be reconfigured.
1072 *
1073 * It is possible to stop the receive and transmit path separate or
1074 * both together.
1075 *
1076 * Dir = SK_STOP_TX Stops the transmit path only and resets the MAC.
1077 * The receive queue is still active and
1078 * the pending Rx frames may be still transferred
1079 * into the RxD.
1080 * SK_STOP_RX Stop the receive path. The tansmit path
1081 * has to be stopped once before.
1082 * SK_STOP_ALL SK_STOP_TX + SK_STOP_RX
1083 *
1084 * RstMode = SK_SOFT_RST Resets the MAC. The PHY is still alive.
1085 * SK_HARD_RST Resets the MAC and the PHY.
1086 *
1087 * Example:
1088 * 1) A Link Down event was signaled for a port. Therefore the activity
1089 * of this port should be stopped and a hardware reset should be issued
1090 * to enable the workaround of XMAC Errata #2. But the received frames
1091 * should not be discarded.
1092 * ...
1093 * SkGeStopPort(pAC, IoC, Port, SK_STOP_TX, SK_HARD_RST);
1094 * (transfer all pending Rx frames)
1095 * SkGeStopPort(pAC, IoC, Port, SK_STOP_RX, SK_HARD_RST);
1096 * ...
1097 *
1098 * 2) An event was issued which request the driver to switch
1099 * the 'virtual active' link to an other already active port
1100 * as soon as possible. The frames in the receive queue of this
1101 * port may be lost. But the PHY must not be reset during this
1102 * event.
1103 * ...
1104 * SkGeStopPort(pAC, IoC, Port, SK_STOP_ALL, SK_SOFT_RST);
1105 * ...
1106 *
1107 * Extended Description:
1108 * If SK_STOP_TX is set,
1109 * o disable the MAC's receive and transmitter to prevent
1110 * from sending incomplete frames
1111 * o stop the port's transmit queues before terminating the
1112 * BMUs to prevent from performing incomplete PCI cycles
1113 * on the PCI bus
1114 * - The network Rx and Tx activity and PCI Tx transfer is
1115 * disabled now.
1116 * o reset the MAC depending on the RstMode
1117 * o Stop Interval Timer and Limit Counter of Tx Arbiter,
1118 * also disable Force Sync bit and Enable Alloc bit.
1119 * o perform a local reset of the port's Tx path
1120 * - reset the PCI FIFO of the async Tx queue
1121 * - reset the PCI FIFO of the sync Tx queue
1122 * - reset the RAM Buffer async Tx queue
1123 * - reset the RAM Buffer sync Tx queue
1124 * - reset the MAC Tx FIFO
1125 * o switch Link and Tx LED off, stop the LED counters
1126 *
1127 * If SK_STOP_RX is set,
1128 * o stop the port's receive queue
1129 * - The path data transfer activity is fully stopped now.
1130 * o perform a local reset of the port's Rx path
1131 * - reset the PCI FIFO of the Rx queue
1132 * - reset the RAM Buffer receive queue
1133 * - reset the MAC Rx FIFO
1134 * o switch Rx LED off, stop the LED counter
1135 *
1136 * If all ports are stopped,
1137 * o reset the RAM Interface.
1138 *
1139 * Notes:
1140 * o This function may be called during the driver states RESET_PORT and
1141 * SWITCH_PORT.
1142 */
SkGeStopPort(SK_AC * pAC,SK_IOC IoC,int Port,int Dir,int RstMode)1143 void SkGeStopPort(
1144 SK_AC *pAC, /* adapter context */
1145 SK_IOC IoC, /* I/O context */
1146 int Port, /* port to stop (MAC_1 + n) */
1147 int Dir, /* Direction to Stop (SK_STOP_RX, SK_STOP_TX, SK_STOP_ALL) */
1148 int RstMode)/* Reset Mode (SK_SOFT_RST, SK_HARD_RST) */
1149 {
1150 #ifndef SK_DIAG
1151 SK_EVPARA Para;
1152 #endif /* !SK_DIAG */
1153 SK_GEPORT *pPrt;
1154 SK_U32 DWord;
1155 SK_U32 XsCsr;
1156 SK_U32 XaCsr;
1157 SK_U64 ToutStart;
1158 int i;
1159 int ToutCnt;
1160
1161 pPrt = &pAC->GIni.GP[Port];
1162
1163 if ((Dir & SK_STOP_TX) != 0) {
1164 /* disable receiver and transmitter */
1165 SkMacRxTxDisable(pAC, IoC, Port);
1166
1167 /* stop both transmit queues */
1168 /*
1169 * If the BMU is in the reset state CSR_STOP will terminate
1170 * immediately.
1171 */
1172 SK_OUT32(IoC, Q_ADDR(pPrt->PXsQOff, Q_CSR), CSR_STOP);
1173 SK_OUT32(IoC, Q_ADDR(pPrt->PXaQOff, Q_CSR), CSR_STOP);
1174
1175 ToutStart = SkOsGetTime(pAC);
1176 ToutCnt = 0;
1177 do {
1178 /*
1179 * Clear packet arbiter timeout to make sure
1180 * this loop will terminate.
1181 */
1182 SK_OUT16(IoC, B3_PA_CTRL, (SK_U16)((Port == MAC_1) ?
1183 PA_CLR_TO_TX1 : PA_CLR_TO_TX2));
1184
1185 /*
1186 * If the transfer stucks at the MAC the STOP command will not
1187 * terminate if we don't flush the XMAC's transmit FIFO !
1188 */
1189 SkMacFlushTxFifo(pAC, IoC, Port);
1190
1191 XsCsr = TestStopBit(pAC, IoC, pPrt->PXsQOff);
1192 XaCsr = TestStopBit(pAC, IoC, pPrt->PXaQOff);
1193
1194 if (SkOsGetTime(pAC) - ToutStart > (SK_TICKS_PER_SEC / 18)) {
1195 /*
1196 * Timeout of 1/18 second reached.
1197 * This needs to be checked at 1/18 sec only.
1198 */
1199 ToutCnt++;
1200 if (ToutCnt > 1) {
1201 /* Might be a problem when the driver event handler
1202 * calls StopPort again. XXX.
1203 */
1204
1205 /* Fatal Error, Loop aborted */
1206 SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_HWI_E018,
1207 SKERR_HWI_E018MSG);
1208 #ifndef SK_DIAG
1209 Para.Para64 = Port;
1210 SkEventQueue(pAC, SKGE_DRV, SK_DRV_PORT_FAIL, Para);
1211 #endif /* !SK_DIAG */
1212 return;
1213 }
1214 /*
1215 * Cache incoherency workaround: Assume a start command
1216 * has been lost while sending the frame.
1217 */
1218 ToutStart = SkOsGetTime(pAC);
1219
1220 if ((XsCsr & CSR_STOP) != 0) {
1221 SK_OUT32(IoC, Q_ADDR(pPrt->PXsQOff, Q_CSR), CSR_START);
1222 }
1223 if ((XaCsr & CSR_STOP) != 0) {
1224 SK_OUT32(IoC, Q_ADDR(pPrt->PXaQOff, Q_CSR), CSR_START);
1225 }
1226 }
1227
1228 /*
1229 * Because of the ASIC problem report entry from 21.08.1998 it is
1230 * required to wait until CSR_STOP is reset and CSR_SV_IDLE is set.
1231 */
1232 } while ((XsCsr & (CSR_STOP | CSR_SV_IDLE)) != CSR_SV_IDLE ||
1233 (XaCsr & (CSR_STOP | CSR_SV_IDLE)) != CSR_SV_IDLE);
1234
1235 /* Reset the MAC depending on the RstMode */
1236 if (RstMode == SK_SOFT_RST) {
1237 SkMacSoftRst(pAC, IoC, Port);
1238 }
1239 else {
1240 SkMacHardRst(pAC, IoC, Port);
1241 }
1242
1243 /* Disable Force Sync bit and Enable Alloc bit */
1244 SK_OUT8(IoC, MR_ADDR(Port, TXA_CTRL),
1245 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
1246
1247 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
1248 SK_OUT32(IoC, MR_ADDR(Port, TXA_ITI_INI), 0L);
1249 SK_OUT32(IoC, MR_ADDR(Port, TXA_LIM_INI), 0L);
1250
1251 /* Perform a local reset of the port's Tx path */
1252
1253 /* Reset the PCI FIFO of the async Tx queue */
1254 SK_OUT32(IoC, Q_ADDR(pPrt->PXaQOff, Q_CSR), CSR_SET_RESET);
1255 /* Reset the PCI FIFO of the sync Tx queue */
1256 SK_OUT32(IoC, Q_ADDR(pPrt->PXsQOff, Q_CSR), CSR_SET_RESET);
1257 /* Reset the RAM Buffer async Tx queue */
1258 SK_OUT8(IoC, RB_ADDR(pPrt->PXaQOff, RB_CTRL), RB_RST_SET);
1259 /* Reset the RAM Buffer sync Tx queue */
1260 SK_OUT8(IoC, RB_ADDR(pPrt->PXsQOff, RB_CTRL), RB_RST_SET);
1261
1262 /* Reset Tx MAC FIFO */
1263 #ifdef GENESIS
1264 if (pAC->GIni.GIGenesis) {
1265 /* Note: MFF_RST_SET does NOT reset the XMAC ! */
1266 SK_OUT8(IoC, MR_ADDR(Port, TX_MFF_CTRL2), MFF_RST_SET);
1267
1268 /* switch Link and Tx LED off, stop the LED counters */
1269 /* Link LED is switched off by the RLMT and the Diag itself */
1270 SkGeXmitLED(pAC, IoC, MR_ADDR(Port, TX_LED_INI), SK_LED_DIS);
1271 }
1272 #endif /* GENESIS */
1273
1274 #ifdef YUKON
1275 if (pAC->GIni.GIYukon) {
1276 /* Reset TX MAC FIFO */
1277 SK_OUT8(IoC, MR_ADDR(Port, TX_GMF_CTRL_T), (SK_U8)GMF_RST_SET);
1278 }
1279 #endif /* YUKON */
1280 }
1281
1282 if ((Dir & SK_STOP_RX) != 0) {
1283 /*
1284 * The RX Stop Command will not terminate if no buffers
1285 * are queued in the RxD ring. But it will always reach
1286 * the Idle state. Therefore we can use this feature to
1287 * stop the transfer of received packets.
1288 */
1289 /* stop the port's receive queue */
1290 SK_OUT32(IoC, Q_ADDR(pPrt->PRxQOff, Q_CSR), CSR_STOP);
1291
1292 i = 100;
1293 do {
1294 /*
1295 * Clear packet arbiter timeout to make sure
1296 * this loop will terminate
1297 */
1298 SK_OUT16(IoC, B3_PA_CTRL, (SK_U16)((Port == MAC_1) ?
1299 PA_CLR_TO_RX1 : PA_CLR_TO_RX2));
1300
1301 DWord = TestStopBit(pAC, IoC, pPrt->PRxQOff);
1302
1303 /* timeout if i==0 (bug fix for #10748) */
1304 if (--i == 0) {
1305 SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_HWI_E024,
1306 SKERR_HWI_E024MSG);
1307 break;
1308 }
1309 /*
1310 * because of the ASIC problem report entry from 21.08.98
1311 * it is required to wait until CSR_STOP is reset and
1312 * CSR_SV_IDLE is set.
1313 */
1314 } while ((DWord & (CSR_STOP | CSR_SV_IDLE)) != CSR_SV_IDLE);
1315
1316 /* The path data transfer activity is fully stopped now */
1317
1318 /* Perform a local reset of the port's Rx path */
1319
1320 /* Reset the PCI FIFO of the Rx queue */
1321 SK_OUT32(IoC, Q_ADDR(pPrt->PRxQOff, Q_CSR), CSR_SET_RESET);
1322 /* Reset the RAM Buffer receive queue */
1323 SK_OUT8(IoC, RB_ADDR(pPrt->PRxQOff, RB_CTRL), RB_RST_SET);
1324
1325 /* Reset Rx MAC FIFO */
1326 #ifdef GENESIS
1327 if (pAC->GIni.GIGenesis) {
1328
1329 SK_OUT8(IoC, MR_ADDR(Port, RX_MFF_CTRL2), MFF_RST_SET);
1330
1331 /* switch Rx LED off, stop the LED counter */
1332 SkGeXmitLED(pAC, IoC, MR_ADDR(Port, RX_LED_INI), SK_LED_DIS);
1333 }
1334 #endif /* GENESIS */
1335
1336 #ifdef YUKON
1337 if (pAC->GIni.GIYukon) {
1338 /* Reset Rx MAC FIFO */
1339 SK_OUT8(IoC, MR_ADDR(Port, RX_GMF_CTRL_T), (SK_U8)GMF_RST_SET);
1340 }
1341 #endif /* YUKON */
1342 }
1343 } /* SkGeStopPort */
1344
1345
1346 /******************************************************************************
1347 *
1348 * SkGeInit0() - Level 0 Initialization
1349 *
1350 * Description:
1351 * - Initialize the BMU address offsets
1352 *
1353 * Returns:
1354 * nothing
1355 */
SkGeInit0(SK_AC * pAC,SK_IOC IoC)1356 static void SkGeInit0(
1357 SK_AC *pAC, /* adapter context */
1358 SK_IOC IoC) /* IO context */
1359 {
1360 int i;
1361 SK_GEPORT *pPrt;
1362
1363 for (i = 0; i < SK_MAX_MACS; i++) {
1364 pPrt = &pAC->GIni.GP[i];
1365
1366 pPrt->PState = SK_PRT_RESET;
1367 pPrt->PRxQOff = QOffTab[i].RxQOff;
1368 pPrt->PXsQOff = QOffTab[i].XsQOff;
1369 pPrt->PXaQOff = QOffTab[i].XaQOff;
1370 pPrt->PCheckPar = SK_FALSE;
1371 pPrt->PIsave = 0;
1372 pPrt->PPrevShorts = 0;
1373 pPrt->PLinkResCt = 0;
1374 pPrt->PAutoNegTOCt = 0;
1375 pPrt->PPrevRx = 0;
1376 pPrt->PPrevFcs = 0;
1377 pPrt->PRxLim = SK_DEF_RX_WA_LIM;
1378 pPrt->PLinkMode = (SK_U8)SK_LMODE_AUTOFULL;
1379 pPrt->PLinkSpeedCap = (SK_U8)SK_LSPEED_CAP_1000MBPS;
1380 pPrt->PLinkSpeed = (SK_U8)SK_LSPEED_1000MBPS;
1381 pPrt->PLinkSpeedUsed = (SK_U8)SK_LSPEED_STAT_UNKNOWN;
1382 pPrt->PLinkModeConf = (SK_U8)SK_LMODE_AUTOSENSE;
1383 pPrt->PFlowCtrlMode = (SK_U8)SK_FLOW_MODE_SYM_OR_REM;
1384 pPrt->PLinkCap = (SK_U8)(SK_LMODE_CAP_HALF | SK_LMODE_CAP_FULL |
1385 SK_LMODE_CAP_AUTOHALF | SK_LMODE_CAP_AUTOFULL);
1386 pPrt->PLinkModeStatus = (SK_U8)SK_LMODE_STAT_UNKNOWN;
1387 pPrt->PFlowCtrlCap = (SK_U8)SK_FLOW_MODE_SYM_OR_REM;
1388 pPrt->PFlowCtrlStatus = (SK_U8)SK_FLOW_STAT_NONE;
1389 pPrt->PMSCap = 0;
1390 pPrt->PMSMode = (SK_U8)SK_MS_MODE_AUTO;
1391 pPrt->PMSStatus = (SK_U8)SK_MS_STAT_UNSET;
1392 pPrt->PLipaAutoNeg = (SK_U8)SK_LIPA_UNKNOWN;
1393 pPrt->PAutoNegFail = SK_FALSE;
1394 pPrt->PHWLinkUp = SK_FALSE;
1395 pPrt->PLinkBroken = SK_TRUE; /* See WA code */
1396 pPrt->PPhyPowerState = PHY_PM_OPERATIONAL_MODE;
1397 pPrt->PMacColThres = TX_COL_DEF;
1398 pPrt->PMacJamLen = TX_JAM_LEN_DEF;
1399 pPrt->PMacJamIpgVal = TX_JAM_IPG_DEF;
1400 pPrt->PMacJamIpgData = TX_IPG_JAM_DEF;
1401 pPrt->PMacIpgData = IPG_DATA_DEF;
1402 pPrt->PMacLimit4 = SK_FALSE;
1403 }
1404
1405 pAC->GIni.GIPortUsage = SK_RED_LINK;
1406 pAC->GIni.GILedBlinkCtrl = (SK_U16)OemConfig.Value;
1407 pAC->GIni.GIValIrqMask = IS_ALL_MSK;
1408
1409 } /* SkGeInit0*/
1410
1411 #ifdef SK_PCI_RESET
1412
1413 /******************************************************************************
1414 *
1415 * SkGePciReset() - Reset PCI interface
1416 *
1417 * Description:
1418 * o Read PCI configuration.
1419 * o Change power state to 3.
1420 * o Change power state to 0.
1421 * o Restore PCI configuration.
1422 *
1423 * Returns:
1424 * 0: Success.
1425 * 1: Power state could not be changed to 3.
1426 */
SkGePciReset(SK_AC * pAC,SK_IOC IoC)1427 static int SkGePciReset(
1428 SK_AC *pAC, /* adapter context */
1429 SK_IOC IoC) /* IO context */
1430 {
1431 int i;
1432 SK_U16 PmCtlSts;
1433 SK_U32 Bp1;
1434 SK_U32 Bp2;
1435 SK_U16 PciCmd;
1436 SK_U8 Cls;
1437 SK_U8 Lat;
1438 SK_U8 ConfigSpace[PCI_CFG_SIZE];
1439
1440 /*
1441 * Note: Switching to D3 state is like a software reset.
1442 * Switching from D3 to D0 is a hardware reset.
1443 * We have to save and restore the configuration space.
1444 */
1445 for (i = 0; i < PCI_CFG_SIZE; i++) {
1446 SkPciReadCfgDWord(pAC, i*4, &ConfigSpace[i]);
1447 }
1448
1449 /* We know the RAM Interface Arbiter is enabled. */
1450 SkPciWriteCfgWord(pAC, PCI_PM_CTL_STS, PCI_PM_STATE_D3);
1451 SkPciReadCfgWord(pAC, PCI_PM_CTL_STS, &PmCtlSts);
1452
1453 if ((PmCtlSts & PCI_PM_STATE_MSK) != PCI_PM_STATE_D3) {
1454 return(1);
1455 }
1456
1457 /* Return to D0 state. */
1458 SkPciWriteCfgWord(pAC, PCI_PM_CTL_STS, PCI_PM_STATE_D0);
1459
1460 /* Check for D0 state. */
1461 SkPciReadCfgWord(pAC, PCI_PM_CTL_STS, &PmCtlSts);
1462
1463 if ((PmCtlSts & PCI_PM_STATE_MSK) != PCI_PM_STATE_D0) {
1464 return(1);
1465 }
1466
1467 /* Check PCI Config Registers. */
1468 SkPciReadCfgWord(pAC, PCI_COMMAND, &PciCmd);
1469 SkPciReadCfgByte(pAC, PCI_CACHE_LSZ, &Cls);
1470 SkPciReadCfgDWord(pAC, PCI_BASE_1ST, &Bp1);
1471 SkPciReadCfgDWord(pAC, PCI_BASE_2ND, &Bp2);
1472 SkPciReadCfgByte(pAC, PCI_LAT_TIM, &Lat);
1473
1474 if (PciCmd != 0 || Cls != (SK_U8)0 || Lat != (SK_U8)0 ||
1475 (Bp1 & 0xfffffff0L) != 0 || Bp2 != 1) {
1476 return(1);
1477 }
1478
1479 /* Restore PCI Config Space. */
1480 for (i = 0; i < PCI_CFG_SIZE; i++) {
1481 SkPciWriteCfgDWord(pAC, i*4, ConfigSpace[i]);
1482 }
1483
1484 return(0);
1485 } /* SkGePciReset */
1486
1487 #endif /* SK_PCI_RESET */
1488
1489 /******************************************************************************
1490 *
1491 * SkGeInit1() - Level 1 Initialization
1492 *
1493 * Description:
1494 * o Do a software reset.
1495 * o Clear all reset bits.
1496 * o Verify that the detected hardware is present.
1497 * Return an error if not.
1498 * o Get the hardware configuration
1499 * + Read the number of MACs/Ports.
1500 * + Read the RAM size.
1501 * + Read the PCI Revision Id.
1502 * + Find out the adapters host clock speed
1503 * + Read and check the PHY type
1504 *
1505 * Returns:
1506 * 0: success
1507 * 5: Unexpected PHY type detected
1508 * 6: HW self test failed
1509 */
SkGeInit1(SK_AC * pAC,SK_IOC IoC)1510 static int SkGeInit1(
1511 SK_AC *pAC, /* adapter context */
1512 SK_IOC IoC) /* IO context */
1513 {
1514 SK_U8 Byte;
1515 SK_U16 Word;
1516 SK_U16 CtrlStat;
1517 SK_U32 DWord;
1518 int RetVal;
1519 int i;
1520
1521 RetVal = 0;
1522
1523 /* save CLK_RUN bits (YUKON-Lite) */
1524 SK_IN16(IoC, B0_CTST, &CtrlStat);
1525
1526 #ifdef SK_PCI_RESET
1527 (void)SkGePciReset(pAC, IoC);
1528 #endif /* SK_PCI_RESET */
1529
1530 /* do the SW-reset */
1531 SK_OUT8(IoC, B0_CTST, CS_RST_SET);
1532
1533 /* release the SW-reset */
1534 SK_OUT8(IoC, B0_CTST, CS_RST_CLR);
1535
1536 /* reset all error bits in the PCI STATUS register */
1537 /*
1538 * Note: PCI Cfg cycles cannot be used, because they are not
1539 * available on some platforms after 'boot time'.
1540 */
1541 SK_IN16(IoC, PCI_C(PCI_STATUS), &Word);
1542
1543 SK_OUT8(IoC, B2_TST_CTRL1, TST_CFG_WRITE_ON);
1544 SK_OUT16(IoC, PCI_C(PCI_STATUS), (SK_U16)(Word | PCI_ERRBITS));
1545 SK_OUT8(IoC, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
1546
1547 /* release Master Reset */
1548 SK_OUT8(IoC, B0_CTST, CS_MRST_CLR);
1549
1550 #ifdef CLK_RUN
1551 CtrlStat |= CS_CLK_RUN_ENA;
1552 #endif /* CLK_RUN */
1553
1554 /* restore CLK_RUN bits */
1555 SK_OUT16(IoC, B0_CTST, (SK_U16)(CtrlStat &
1556 (CS_CLK_RUN_HOT | CS_CLK_RUN_RST | CS_CLK_RUN_ENA)));
1557
1558 /* read Chip Identification Number */
1559 SK_IN8(IoC, B2_CHIP_ID, &Byte);
1560 pAC->GIni.GIChipId = Byte;
1561
1562 /* read number of MACs */
1563 SK_IN8(IoC, B2_MAC_CFG, &Byte);
1564 pAC->GIni.GIMacsFound = (Byte & CFG_SNG_MAC) ? 1 : 2;
1565
1566 /* get Chip Revision Number */
1567 pAC->GIni.GIChipRev = (SK_U8)((Byte & CFG_CHIP_R_MSK) >> 4);
1568
1569 /* get diff. PCI parameters */
1570 SK_IN16(IoC, B0_CTST, &CtrlStat);
1571
1572 /* read the adapters RAM size */
1573 SK_IN8(IoC, B2_E_0, &Byte);
1574
1575 pAC->GIni.GIGenesis = SK_FALSE;
1576 pAC->GIni.GIYukon = SK_FALSE;
1577 pAC->GIni.GIYukonLite = SK_FALSE;
1578
1579 #ifdef GENESIS
1580 if (pAC->GIni.GIChipId == CHIP_ID_GENESIS) {
1581
1582 pAC->GIni.GIGenesis = SK_TRUE;
1583
1584 if (Byte == (SK_U8)3) {
1585 /* special case: 4 x 64k x 36, offset = 0x80000 */
1586 pAC->GIni.GIRamSize = 1024;
1587 pAC->GIni.GIRamOffs = (SK_U32)512 * 1024;
1588 }
1589 else {
1590 pAC->GIni.GIRamSize = (int)Byte * 512;
1591 pAC->GIni.GIRamOffs = 0;
1592 }
1593 /* all GE adapters work with 53.125 MHz host clock */
1594 pAC->GIni.GIHstClkFact = SK_FACT_53;
1595
1596 /* set Descr. Poll Timer Init Value to 250 ms */
1597 pAC->GIni.GIPollTimerVal =
1598 SK_DPOLL_DEF * (SK_U32)pAC->GIni.GIHstClkFact / 100;
1599 }
1600 #endif /* GENESIS */
1601
1602 #ifdef YUKON
1603 if (pAC->GIni.GIChipId != CHIP_ID_GENESIS) {
1604
1605 pAC->GIni.GIYukon = SK_TRUE;
1606
1607 pAC->GIni.GIRamSize = (Byte == (SK_U8)0) ? 128 : (int)Byte * 4;
1608
1609 pAC->GIni.GIRamOffs = 0;
1610
1611 /* WA for chip Rev. A */
1612 pAC->GIni.GIWolOffs = (pAC->GIni.GIChipId == CHIP_ID_YUKON &&
1613 pAC->GIni.GIChipRev == 0) ? WOL_REG_OFFS : 0;
1614
1615 /* get PM Capabilities of PCI config space */
1616 SK_IN16(IoC, PCI_C(PCI_PM_CAP_REG), &Word);
1617
1618 /* check if VAUX is available */
1619 if (((CtrlStat & CS_VAUX_AVAIL) != 0) &&
1620 /* check also if PME from D3cold is set */
1621 ((Word & PCI_PME_D3C_SUP) != 0)) {
1622 /* set entry in GE init struct */
1623 pAC->GIni.GIVauxAvail = SK_TRUE;
1624 }
1625
1626 if (pAC->GIni.GIChipId == CHIP_ID_YUKON_LITE) {
1627 /* this is Rev. A1 */
1628 pAC->GIni.GIYukonLite = SK_TRUE;
1629 }
1630 else {
1631 /* save Flash-Address Register */
1632 SK_IN32(IoC, B2_FAR, &DWord);
1633
1634 /* test Flash-Address Register */
1635 SK_OUT8(IoC, B2_FAR + 3, 0xff);
1636 SK_IN8(IoC, B2_FAR + 3, &Byte);
1637
1638 if (Byte != 0) {
1639 /* this is Rev. A0 */
1640 pAC->GIni.GIYukonLite = SK_TRUE;
1641
1642 /* restore Flash-Address Register */
1643 SK_OUT32(IoC, B2_FAR, DWord);
1644 }
1645 }
1646
1647 /* switch power to VCC (WA for VAUX problem) */
1648 SK_OUT8(IoC, B0_POWER_CTRL, (SK_U8)(PC_VAUX_ENA | PC_VCC_ENA |
1649 PC_VAUX_OFF | PC_VCC_ON));
1650
1651 /* read the Interrupt source */
1652 SK_IN32(IoC, B0_ISRC, &DWord);
1653
1654 if ((DWord & IS_HW_ERR) != 0) {
1655 /* read the HW Error Interrupt source */
1656 SK_IN32(IoC, B0_HWE_ISRC, &DWord);
1657
1658 if ((DWord & IS_IRQ_SENSOR) != 0) {
1659 /* disable HW Error IRQ */
1660 pAC->GIni.GIValIrqMask &= ~IS_HW_ERR;
1661 }
1662 }
1663
1664 for (i = 0; i < pAC->GIni.GIMacsFound; i++) {
1665 /* set GMAC Link Control reset */
1666 SK_OUT16(IoC, MR_ADDR(i, GMAC_LINK_CTRL), GMLC_RST_SET);
1667
1668 /* clear GMAC Link Control reset */
1669 SK_OUT16(IoC, MR_ADDR(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
1670 }
1671 /* all YU chips work with 78.125 MHz host clock */
1672 pAC->GIni.GIHstClkFact = SK_FACT_78;
1673
1674 pAC->GIni.GIPollTimerVal = SK_DPOLL_MAX; /* 215 ms */
1675 }
1676 #endif /* YUKON */
1677
1678 /* check if 64-bit PCI Slot is present */
1679 pAC->GIni.GIPciSlot64 = (SK_BOOL)((CtrlStat & CS_BUS_SLOT_SZ) != 0);
1680
1681 /* check if 66 MHz PCI Clock is active */
1682 pAC->GIni.GIPciClock66 = (SK_BOOL)((CtrlStat & CS_BUS_CLOCK) != 0);
1683
1684 /* read PCI HW Revision Id. */
1685 SK_IN8(IoC, PCI_C(PCI_REV_ID), &Byte);
1686 pAC->GIni.GIPciHwRev = Byte;
1687
1688 /* read the PMD type */
1689 SK_IN8(IoC, B2_PMD_TYP, &Byte);
1690 pAC->GIni.GICopperType = (SK_U8)(Byte == 'T');
1691
1692 /* read the PHY type */
1693 SK_IN8(IoC, B2_E_1, &Byte);
1694
1695 Byte &= 0x0f; /* the PHY type is stored in the lower nibble */
1696 for (i = 0; i < pAC->GIni.GIMacsFound; i++) {
1697
1698 #ifdef GENESIS
1699 if (pAC->GIni.GIGenesis) {
1700 switch (Byte) {
1701 case SK_PHY_XMAC:
1702 pAC->GIni.GP[i].PhyAddr = PHY_ADDR_XMAC;
1703 break;
1704 case SK_PHY_BCOM:
1705 pAC->GIni.GP[i].PhyAddr = PHY_ADDR_BCOM;
1706 pAC->GIni.GP[i].PMSCap = (SK_U8)(SK_MS_CAP_AUTO |
1707 SK_MS_CAP_MASTER | SK_MS_CAP_SLAVE);
1708 break;
1709 #ifdef OTHER_PHY
1710 case SK_PHY_LONE:
1711 pAC->GIni.GP[i].PhyAddr = PHY_ADDR_LONE;
1712 break;
1713 case SK_PHY_NAT:
1714 pAC->GIni.GP[i].PhyAddr = PHY_ADDR_NAT;
1715 break;
1716 #endif /* OTHER_PHY */
1717 default:
1718 /* ERROR: unexpected PHY type detected */
1719 RetVal = 5;
1720 break;
1721 }
1722 }
1723 #endif /* GENESIS */
1724
1725 #ifdef YUKON
1726 if (pAC->GIni.GIYukon) {
1727
1728 if (Byte < (SK_U8)SK_PHY_MARV_COPPER) {
1729 /* if this field is not initialized */
1730 Byte = (SK_U8)SK_PHY_MARV_COPPER;
1731
1732 pAC->GIni.GICopperType = SK_TRUE;
1733 }
1734
1735 pAC->GIni.GP[i].PhyAddr = PHY_ADDR_MARV;
1736
1737 if (pAC->GIni.GICopperType) {
1738
1739 pAC->GIni.GP[i].PLinkSpeedCap = (SK_U8)(SK_LSPEED_CAP_AUTO |
1740 SK_LSPEED_CAP_10MBPS | SK_LSPEED_CAP_100MBPS |
1741 SK_LSPEED_CAP_1000MBPS);
1742
1743 pAC->GIni.GP[i].PLinkSpeed = (SK_U8)SK_LSPEED_AUTO;
1744
1745 pAC->GIni.GP[i].PMSCap = (SK_U8)(SK_MS_CAP_AUTO |
1746 SK_MS_CAP_MASTER | SK_MS_CAP_SLAVE);
1747 }
1748 else {
1749 Byte = (SK_U8)SK_PHY_MARV_FIBER;
1750 }
1751 }
1752 #endif /* YUKON */
1753
1754 pAC->GIni.GP[i].PhyType = (int)Byte;
1755
1756 SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_INIT,
1757 ("PHY type: %d PHY addr: %04x\n", Byte,
1758 pAC->GIni.GP[i].PhyAddr));
1759 }
1760
1761 /* get MAC Type & set function pointers dependent on */
1762 #ifdef GENESIS
1763 if (pAC->GIni.GIGenesis) {
1764
1765 pAC->GIni.GIMacType = SK_MAC_XMAC;
1766
1767 pAC->GIni.GIFunc.pFnMacUpdateStats = SkXmUpdateStats;
1768 pAC->GIni.GIFunc.pFnMacStatistic = SkXmMacStatistic;
1769 pAC->GIni.GIFunc.pFnMacResetCounter = SkXmResetCounter;
1770 pAC->GIni.GIFunc.pFnMacOverflow = SkXmOverflowStatus;
1771 }
1772 #endif /* GENESIS */
1773
1774 #ifdef YUKON
1775 if (pAC->GIni.GIYukon) {
1776
1777 pAC->GIni.GIMacType = SK_MAC_GMAC;
1778
1779 pAC->GIni.GIFunc.pFnMacUpdateStats = SkGmUpdateStats;
1780 pAC->GIni.GIFunc.pFnMacStatistic = SkGmMacStatistic;
1781 pAC->GIni.GIFunc.pFnMacResetCounter = SkGmResetCounter;
1782 pAC->GIni.GIFunc.pFnMacOverflow = SkGmOverflowStatus;
1783
1784 #ifdef SPECIAL_HANDLING
1785 if (pAC->GIni.GIChipId == CHIP_ID_YUKON) {
1786 /* check HW self test result */
1787 SK_IN8(IoC, B2_E_3, &Byte);
1788 if (Byte & B2_E3_RES_MASK) {
1789 RetVal = 6;
1790 }
1791 }
1792 #endif
1793 }
1794 #endif /* YUKON */
1795
1796 return(RetVal);
1797 } /* SkGeInit1 */
1798
1799
1800 /******************************************************************************
1801 *
1802 * SkGeInit2() - Level 2 Initialization
1803 *
1804 * Description:
1805 * - start the Blink Source Counter
1806 * - start the Descriptor Poll Timer
1807 * - configure the MAC-Arbiter
1808 * - configure the Packet-Arbiter
1809 * - enable the Tx Arbiters
1810 * - enable the RAM Interface Arbiter
1811 *
1812 * Returns:
1813 * nothing
1814 */
SkGeInit2(SK_AC * pAC,SK_IOC IoC)1815 static void SkGeInit2(
1816 SK_AC *pAC, /* adapter context */
1817 SK_IOC IoC) /* IO context */
1818 {
1819 #ifdef GENESIS
1820 SK_U32 DWord;
1821 #endif /* GENESIS */
1822 int i;
1823
1824 /* start the Descriptor Poll Timer */
1825 if (pAC->GIni.GIPollTimerVal != 0) {
1826 if (pAC->GIni.GIPollTimerVal > SK_DPOLL_MAX) {
1827 pAC->GIni.GIPollTimerVal = SK_DPOLL_MAX;
1828
1829 SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E017, SKERR_HWI_E017MSG);
1830 }
1831 SK_OUT32(IoC, B28_DPT_INI, pAC->GIni.GIPollTimerVal);
1832 SK_OUT8(IoC, B28_DPT_CTRL, DPT_START);
1833 }
1834
1835 #ifdef GENESIS
1836 if (pAC->GIni.GIGenesis) {
1837 /* start the Blink Source Counter */
1838 DWord = SK_BLK_DUR * (SK_U32)pAC->GIni.GIHstClkFact / 100;
1839
1840 SK_OUT32(IoC, B2_BSC_INI, DWord);
1841 SK_OUT8(IoC, B2_BSC_CTRL, BSC_START);
1842
1843 /*
1844 * Configure the MAC Arbiter and the Packet Arbiter.
1845 * They will be started once and never be stopped.
1846 */
1847 SkGeInitMacArb(pAC, IoC);
1848
1849 SkGeInitPktArb(pAC, IoC);
1850 }
1851 #endif /* GENESIS */
1852
1853 #ifdef YUKON
1854 if (pAC->GIni.GIYukon) {
1855 /* start Time Stamp Timer */
1856 SK_OUT8(IoC, GMAC_TI_ST_CTRL, (SK_U8)GMT_ST_START);
1857 }
1858 #endif /* YUKON */
1859
1860 /* enable the Tx Arbiters */
1861 for (i = 0; i < pAC->GIni.GIMacsFound; i++) {
1862 SK_OUT8(IoC, MR_ADDR(i, TXA_CTRL), TXA_ENA_ARB);
1863 }
1864
1865 /* enable the RAM Interface Arbiter */
1866 SkGeInitRamIface(pAC, IoC);
1867
1868 } /* SkGeInit2 */
1869
1870 /******************************************************************************
1871 *
1872 * SkGeInit() - Initialize the GE Adapter with the specified level.
1873 *
1874 * Description:
1875 * Level 0: Initialize the Module structures.
1876 * Level 1: Generic Hardware Initialization. The IOP/MemBase pointer has
1877 * to be set before calling this level.
1878 *
1879 * o Do a software reset.
1880 * o Clear all reset bits.
1881 * o Verify that the detected hardware is present.
1882 * Return an error if not.
1883 * o Get the hardware configuration
1884 * + Set GIMacsFound with the number of MACs.
1885 * + Store the RAM size in GIRamSize.
1886 * + Save the PCI Revision ID in GIPciHwRev.
1887 * o return an error
1888 * if Number of MACs > SK_MAX_MACS
1889 *
1890 * After returning from Level 0 the adapter
1891 * may be accessed with IO operations.
1892 *
1893 * Level 2: start the Blink Source Counter
1894 *
1895 * Returns:
1896 * 0: success
1897 * 1: Number of MACs exceeds SK_MAX_MACS (after level 1)
1898 * 2: Adapter not present or not accessible
1899 * 3: Illegal initialization level
1900 * 4: Initialization Level 1 Call missing
1901 * 5: Unexpected PHY type detected
1902 * 6: HW self test failed
1903 */
SkGeInit(SK_AC * pAC,SK_IOC IoC,int Level)1904 int SkGeInit(
1905 SK_AC *pAC, /* adapter context */
1906 SK_IOC IoC, /* IO context */
1907 int Level) /* initialization level */
1908 {
1909 int RetVal; /* return value */
1910 SK_U32 DWord;
1911
1912 RetVal = 0;
1913 SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_INIT,
1914 ("SkGeInit(Level %d)\n", Level));
1915
1916 switch (Level) {
1917 case SK_INIT_DATA:
1918 /* Initialization Level 0 */
1919 SkGeInit0(pAC, IoC);
1920 pAC->GIni.GILevel = SK_INIT_DATA;
1921 break;
1922
1923 case SK_INIT_IO:
1924 /* Initialization Level 1 */
1925 RetVal = SkGeInit1(pAC, IoC);
1926 if (RetVal != 0) {
1927 break;
1928 }
1929
1930 /* check if the adapter seems to be accessible */
1931 SK_OUT32(IoC, B2_IRQM_INI, SK_TEST_VAL);
1932 SK_IN32(IoC, B2_IRQM_INI, &DWord);
1933 SK_OUT32(IoC, B2_IRQM_INI, 0L);
1934
1935 if (DWord != SK_TEST_VAL) {
1936 RetVal = 2;
1937 break;
1938 }
1939
1940 /* check if the number of GIMacsFound matches SK_MAX_MACS */
1941 if (pAC->GIni.GIMacsFound > SK_MAX_MACS) {
1942 RetVal = 1;
1943 break;
1944 }
1945
1946 /* Level 1 successfully passed */
1947 pAC->GIni.GILevel = SK_INIT_IO;
1948 break;
1949
1950 case SK_INIT_RUN:
1951 /* Initialization Level 2 */
1952 if (pAC->GIni.GILevel != SK_INIT_IO) {
1953 #ifndef SK_DIAG
1954 SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E002, SKERR_HWI_E002MSG);
1955 #endif /* !SK_DIAG */
1956 RetVal = 4;
1957 break;
1958 }
1959 SkGeInit2(pAC, IoC);
1960
1961 /* Level 2 successfully passed */
1962 pAC->GIni.GILevel = SK_INIT_RUN;
1963 break;
1964
1965 default:
1966 SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E003, SKERR_HWI_E003MSG);
1967 RetVal = 3;
1968 break;
1969 }
1970
1971 return(RetVal);
1972 } /* SkGeInit */
1973
1974
1975 /******************************************************************************
1976 *
1977 * SkGeDeInit() - Deinitialize the adapter
1978 *
1979 * Description:
1980 * All ports of the adapter will be stopped if not already done.
1981 * Do a software reset and switch off all LEDs.
1982 *
1983 * Returns:
1984 * nothing
1985 */
SkGeDeInit(SK_AC * pAC,SK_IOC IoC)1986 void SkGeDeInit(
1987 SK_AC *pAC, /* adapter context */
1988 SK_IOC IoC) /* IO context */
1989 {
1990 int i;
1991 SK_U16 Word;
1992
1993 #ifdef SK_PHY_LP_MODE
1994 SK_U8 Byte;
1995 SK_U16 PmCtlSts;
1996 #endif /* SK_PHY_LP_MODE */
1997
1998 #if (!defined(SK_SLIM) && !defined(VCPU))
1999 /* ensure I2C is ready */
2000 SkI2cWaitIrq(pAC, IoC);
2001 #endif
2002
2003 /* stop all current transfer activity */
2004 for (i = 0; i < pAC->GIni.GIMacsFound; i++) {
2005 if (pAC->GIni.GP[i].PState != SK_PRT_STOP &&
2006 pAC->GIni.GP[i].PState != SK_PRT_RESET) {
2007
2008 SkGeStopPort(pAC, IoC, i, SK_STOP_ALL, SK_HARD_RST);
2009 }
2010 }
2011
2012 #ifdef SK_PHY_LP_MODE
2013 /*
2014 * for power saving purposes within mobile environments
2015 * we set the PHY to coma mode and switch to D3 power state.
2016 */
2017 if (pAC->GIni.GIYukonLite &&
2018 pAC->GIni.GIChipRev == CHIP_REV_YU_LITE_A3) {
2019
2020 /* for all ports switch PHY to coma mode */
2021 for (i = 0; i < pAC->GIni.GIMacsFound; i++) {
2022
2023 SkGmEnterLowPowerMode(pAC, IoC, i, PHY_PM_DEEP_SLEEP);
2024 }
2025
2026 if (pAC->GIni.GIVauxAvail) {
2027 /* switch power to VAUX */
2028 Byte = PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_ON | PC_VCC_OFF;
2029
2030 SK_OUT8(IoC, B0_POWER_CTRL, Byte);
2031 }
2032
2033 /* switch to D3 state */
2034 SK_IN16(IoC, PCI_C(PCI_PM_CTL_STS), &PmCtlSts);
2035
2036 PmCtlSts |= PCI_PM_STATE_D3;
2037
2038 SK_OUT8(IoC, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2039
2040 SK_OUT16(IoC, PCI_C(PCI_PM_CTL_STS), PmCtlSts);
2041 }
2042 #endif /* SK_PHY_LP_MODE */
2043
2044 /* Reset all bits in the PCI STATUS register */
2045 /*
2046 * Note: PCI Cfg cycles cannot be used, because they are not
2047 * available on some platforms after 'boot time'.
2048 */
2049 SK_IN16(IoC, PCI_C(PCI_STATUS), &Word);
2050
2051 SK_OUT8(IoC, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2052 SK_OUT16(IoC, PCI_C(PCI_STATUS), (SK_U16)(Word | PCI_ERRBITS));
2053 SK_OUT8(IoC, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2054
2055 /* do the reset, all LEDs are switched off now */
2056 SK_OUT8(IoC, B0_CTST, CS_RST_SET);
2057
2058 pAC->GIni.GILevel = SK_INIT_DATA;
2059 } /* SkGeDeInit */
2060
2061
2062 /******************************************************************************
2063 *
2064 * SkGeInitPort() Initialize the specified port.
2065 *
2066 * Description:
2067 * PRxQSize, PXSQSize, and PXAQSize has to be
2068 * configured for the specified port before calling this function.
2069 * The descriptor rings has to be initialized too.
2070 *
2071 * o (Re)configure queues of the specified port.
2072 * o configure the MAC of the specified port.
2073 * o put ASIC and MAC(s) in operational mode.
2074 * o initialize Rx/Tx and Sync LED
2075 * o initialize RAM Buffers and MAC FIFOs
2076 *
2077 * The port is ready to connect when returning.
2078 *
2079 * Note:
2080 * The MAC's Rx and Tx state machine is still disabled when returning.
2081 *
2082 * Returns:
2083 * 0: success
2084 * 1: Queue size initialization error. The configured values
2085 * for PRxQSize, PXSQSize, or PXAQSize are invalid for one
2086 * or more queues. The specified port was NOT initialized.
2087 * An error log entry was generated.
2088 * 2: The port has to be stopped before it can be initialized again.
2089 */
SkGeInitPort(SK_AC * pAC,SK_IOC IoC,int Port)2090 int SkGeInitPort(
2091 SK_AC *pAC, /* adapter context */
2092 SK_IOC IoC, /* IO context */
2093 int Port) /* Port to configure */
2094 {
2095 SK_GEPORT *pPrt;
2096
2097 pPrt = &pAC->GIni.GP[Port];
2098
2099 if (SkGeCheckQSize(pAC, Port) != 0) {
2100 SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E004, SKERR_HWI_E004MSG);
2101 return(1);
2102 }
2103
2104 if (pPrt->PState == SK_PRT_INIT || pPrt->PState == SK_PRT_RUN) {
2105 SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E005, SKERR_HWI_E005MSG);
2106 return(2);
2107 }
2108
2109 /* configuration ok, initialize the Port now */
2110
2111 #ifdef GENESIS
2112 if (pAC->GIni.GIGenesis) {
2113 /* initialize Rx, Tx and Link LED */
2114 /*
2115 * If 1000BT Phy needs LED initialization than swap
2116 * LED and XMAC initialization order
2117 */
2118 SkGeXmitLED(pAC, IoC, MR_ADDR(Port, TX_LED_INI), SK_LED_ENA);
2119 SkGeXmitLED(pAC, IoC, MR_ADDR(Port, RX_LED_INI), SK_LED_ENA);
2120 /* The Link LED is initialized by RLMT or Diagnostics itself */
2121
2122 SkXmInitMac(pAC, IoC, Port);
2123 }
2124 #endif /* GENESIS */
2125
2126 #ifdef YUKON
2127 if (pAC->GIni.GIYukon) {
2128
2129 SkGmInitMac(pAC, IoC, Port);
2130 }
2131 #endif /* YUKON */
2132
2133 /* do NOT initialize the Link Sync Counter */
2134
2135 SkGeInitMacFifo(pAC, IoC, Port);
2136
2137 SkGeInitRamBufs(pAC, IoC, Port);
2138
2139 if (pPrt->PXSQSize != 0) {
2140 /* enable Force Sync bit if synchronous queue available */
2141 SK_OUT8(IoC, MR_ADDR(Port, TXA_CTRL), TXA_ENA_FSYNC);
2142 }
2143
2144 SkGeInitBmu(pAC, IoC, Port);
2145
2146 /* mark port as initialized */
2147 pPrt->PState = SK_PRT_INIT;
2148
2149 return(0);
2150 } /* SkGeInitPort */
2151