1 /*
2  * 06/02/02 -Armin
3  *    added new mal functions and defines from ibm_ocp_enet.h
4  */
5 
6 #ifndef _IBM_OCP_MAL_H
7 #define _IBM_OCP_MAL_H
8 
9 #include <linux/list.h>
10 
11 #define MAL_DT_ALIGN	(4096)	/* Alignment for each channel's descriptor table */
12 
13 #define MAL_CHAN_MASK(chan)	(0x80000000 >> (chan))
14 
15 /* MAL Buffer Descriptor structure */
16 struct mal_descriptor {
17 	volatile unsigned short ctrl;	/* MAL / Commac status control bits */
18 	volatile short data_len;	/* Max length is 4K-1 (12 bits)     */
19 	unsigned char *data_ptr;	/* pointer to actual data buffer    */
20 } __attribute__((packed));
21 
22 /* the following defines are for the MadMAL status and control registers. */
23 /* MADMAL transmit and receive status/control bits  */
24 #define MAL_RX_CTRL_EMPTY		0x8000
25 #define MAL_RX_CTRL_WRAP		0x4000
26 #define MAL_RX_CTRL_CM			0x2000
27 #define MAL_RX_CTRL_LAST		0x1000
28 #define MAL_RX_CTRL_FIRST		0x0800
29 #define MAL_RX_CTRL_INTR		0x0400
30 
31 #define MAL_TX_CTRL_READY		0x8000
32 #define MAL_TX_CTRL_WRAP		0x4000
33 #define MAL_TX_CTRL_CM			0x2000
34 #define MAL_TX_CTRL_LAST		0x1000
35 #define MAL_TX_CTRL_INTR		0x0400
36 
37 struct mal_commac_ops {
38 	void (*txeob)(void *dev, u32 chanmask);
39 	void (*txde)(void *dev, u32 chanmask);
40 	void (*rxeob)(void *dev, u32 chanmask);
41 	void (*rxde)(void *dev, u32 chanmask);
42 };
43 
44 struct mal_commac {
45 	struct mal_commac_ops *ops;
46 	void *dev;
47 	u32 tx_chan_mask, rx_chan_mask;
48 	struct list_head list;
49 };
50 
51 /* FIXME: Work this out better */
52 #define MAL_MAX_TX_CHANNELS	(EMAC_NUMS*2)
53 #define MAL_MAX_RX_CHANNELS	(EMAC_NUMS)
54 
55 struct ibm_ocp_mal {
56 	int dcrbase;
57 	int serr_irq, txeob_irq, txde_irq, rxeob_irq, rxde_irq;
58 
59 	struct list_head commac;
60 	u32 tx_chan_mask, rx_chan_mask;
61 
62 	int num_tx_channels;
63 	dma_addr_t tx_phys_addr;
64 	struct mal_descriptor *tx_virt_addr;
65 
66 	int num_rx_channels;
67 	dma_addr_t rx_phys_addr;
68 	struct mal_descriptor *rx_virt_addr;
69 };
70 
71 #ifdef DCRN_MAL1_BASE
72 #define NUM_MALS	2
73 #else
74 #define	NUM_MALS	1
75 #endif
76 
77 extern struct ibm_ocp_mal mal_table[NUM_MALS];
78 
79 #define GET_MAL_STANZA(base,dcrn) \
80 	case base: \
81 		x = mfdcr(dcrn(base)); \
82 		break;
83 
84 #define SET_MAL_STANZA(base,dcrn, val) \
85 	case base: \
86 		mtdcr(dcrn(base), (val)); \
87 		break;
88 
89 #define GET_MAL0_STANZA(dcrn) GET_MAL_STANZA(DCRN_MAL_BASE,dcrn)
90 #define SET_MAL0_STANZA(dcrn,val) SET_MAL_STANZA(DCRN_MAL_BASE,dcrn,val)
91 
92 #ifdef DCRN_MAL1_BASE
93 #define GET_MAL1_STANZA(dcrn) GET_MAL_STANZA(DCRN_MAL1_BASE,dcrn)
94 #define SET_MAL1_STANZA(dcrn,val) SET_MAL_STANZA(DCRN_MAL1_BASE,dcrn,val)
95 #else /* ! DCRN_MAL1_BASE */
96 #define GET_MAL1_STANZA(dcrn)
97 #define SET_MAL1_STANZA(dcrn,val)
98 #endif
99 
100 
101 #define get_mal_dcrn(mal, dcrn) ({ \
102 	u32 x; \
103 	switch ((mal)->dcrbase) { \
104 		GET_MAL0_STANZA(dcrn) \
105 		GET_MAL1_STANZA(dcrn) \
106 	default: \
107 		BUG(); \
108 	} \
109 x; })
110 
111 #define set_mal_dcrn(mal, dcrn, val) do { \
112 	switch ((mal)->dcrbase) { \
113 		SET_MAL0_STANZA(dcrn,val) \
114 		SET_MAL1_STANZA(dcrn,val) \
115 	default: \
116 		BUG(); \
117 	} } while (0)
118 
119 
mal_enable_tx_channels(struct ibm_ocp_mal * mal,u32 chanmask)120 static inline void mal_enable_tx_channels(struct ibm_ocp_mal *mal, u32 chanmask)
121 {
122 	set_mal_dcrn(mal, DCRN_MALTXCASR,
123 		     get_mal_dcrn(mal, DCRN_MALTXCASR) | chanmask);
124 }
125 
mal_disable_tx_channels(struct ibm_ocp_mal * mal,u32 chanmask)126 static inline void mal_disable_tx_channels(struct ibm_ocp_mal *mal, u32 chanmask)
127 {
128 	set_mal_dcrn(mal, DCRN_MALTXCARR, chanmask);
129 }
130 
mal_enable_rx_channels(struct ibm_ocp_mal * mal,u32 chanmask)131 static inline void mal_enable_rx_channels(struct ibm_ocp_mal *mal, u32 chanmask)
132 {
133 	set_mal_dcrn(mal, DCRN_MALRXCASR,
134 		     get_mal_dcrn(mal, DCRN_MALRXCASR) | chanmask);
135 }
136 
mal_disable_rx_channels(struct ibm_ocp_mal * mal,u32 chanmask)137 static inline void mal_disable_rx_channels(struct ibm_ocp_mal *mal, u32 chanmask)
138 {
139 	set_mal_dcrn(mal, DCRN_MALRXCARR, chanmask);
140 }
141 
142 extern int mal_register_commac(struct ibm_ocp_mal *mal, struct mal_commac *commac);
143 extern int mal_unregister_commac(struct ibm_ocp_mal *mal, struct mal_commac *commac);
144 
145 extern int mal_set_rcbs(struct ibm_ocp_mal *mal, int channel, unsigned long size);
146 
147 #endif /* _IBM_OCP_MAL_H */
148