1 /*******************************************************************************
2
3
4 Copyright(c) 1999 - 2004 Intel Corporation. All rights reserved.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms of the GNU General Public License as published by the Free
8 Software Foundation; either version 2 of the License, or (at your option)
9 any later version.
10
11 This program is distributed in the hope that it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 more details.
15
16 You should have received a copy of the GNU General Public License along with
17 this program; if not, write to the Free Software Foundation, Inc., 59
18 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19
20 The full GNU General Public License is included in this distribution in the
21 file called LICENSE.
22
23 Contact Information:
24 Linux NICS <linux.nics@intel.com>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26 *******************************************************************************/
27
28 #include "e100_phy.h"
29
30 void e100_handle_zlock(struct e100_private *bdp);
31
32 /*
33 * Procedure: e100_mdi_write
34 *
35 * Description: This routine will write a value to the specified MII register
36 * of an external MDI compliant device (e.g. PHY 100). The
37 * command will execute in polled mode.
38 *
39 * Arguments:
40 * bdp - Ptr to this card's e100_bdconfig structure
41 * reg_addr - The MII register that we are writing to
42 * phy_addr - The MDI address of the Phy component.
43 * data - The value that we are writing to the MII register.
44 *
45 * Returns:
46 * NOTHING
47 */
48 int
e100_mdi_write(struct e100_private * bdp,u32 reg_addr,u32 phy_addr,u16 data)49 e100_mdi_write(struct e100_private *bdp, u32 reg_addr, u32 phy_addr, u16 data)
50 {
51 int e100_retry;
52 u32 temp_val;
53 unsigned int mdi_cntrl;
54
55 spin_lock_bh(&bdp->mdi_access_lock);
56 temp_val = (((u32) data) | (reg_addr << 16) |
57 (phy_addr << 21) | (MDI_WRITE << 26));
58 writel(temp_val, &bdp->scb->scb_mdi_cntrl);
59 readw(&bdp->scb->scb_status);
60
61 /* wait 20usec before checking status */
62 udelay(20);
63
64 /* poll for the mdi write to complete */
65 e100_retry = E100_CMD_WAIT;
66 while ((!((mdi_cntrl = readl(&bdp->scb->scb_mdi_cntrl)) & MDI_PHY_READY)) && (e100_retry)) {
67
68 udelay(20);
69 e100_retry--;
70 }
71 spin_unlock_bh(&bdp->mdi_access_lock);
72 if (mdi_cntrl & MDI_PHY_READY)
73 return 0;
74 else {
75 printk(KERN_ERR "e100: MDI write timeout\n");
76 return 1;
77 }
78 }
79
80 /*
81 * Procedure: e100_mdi_read
82 *
83 * Description: This routine will read a value from the specified MII register
84 * of an external MDI compliant device (e.g. PHY 100), and return
85 * it to the calling routine. The command will execute in polled
86 * mode.
87 *
88 * Arguments:
89 * bdp - Ptr to this card's e100_bdconfig structure
90 * reg_addr - The MII register that we are reading from
91 * phy_addr - The MDI address of the Phy component.
92 *
93 * Results:
94 * data - The value that we read from the MII register.
95 *
96 * Returns:
97 * NOTHING
98 */
99 int
e100_mdi_read(struct e100_private * bdp,u32 reg_addr,u32 phy_addr,u16 * data)100 e100_mdi_read(struct e100_private *bdp, u32 reg_addr, u32 phy_addr, u16 *data)
101 {
102 int e100_retry;
103 u32 temp_val;
104 unsigned int mdi_cntrl;
105
106 spin_lock_bh(&bdp->mdi_access_lock);
107 /* Issue the read command to the MDI control register. */
108 temp_val = ((reg_addr << 16) | (phy_addr << 21) | (MDI_READ << 26));
109 writel(temp_val, &bdp->scb->scb_mdi_cntrl);
110 readw(&bdp->scb->scb_status);
111
112 /* wait 20usec before checking status */
113 udelay(20);
114
115 /* poll for the mdi read to complete */
116 e100_retry = E100_CMD_WAIT;
117 while ((!((mdi_cntrl = readl(&bdp->scb->scb_mdi_cntrl)) & MDI_PHY_READY)) && (e100_retry)) {
118
119 udelay(20);
120 e100_retry--;
121 }
122
123 spin_unlock_bh(&bdp->mdi_access_lock);
124 if (mdi_cntrl & MDI_PHY_READY) {
125 /* return the lower word */
126 *data = (u16) mdi_cntrl;
127 return 0;
128 }
129 else {
130 printk(KERN_ERR "e100: MDI read timeout\n");
131 return 1;
132 }
133 }
134
135 static unsigned char
e100_phy_valid(struct e100_private * bdp,unsigned int phy_address)136 e100_phy_valid(struct e100_private *bdp, unsigned int phy_address)
137 {
138 u16 ctrl_reg, stat_reg;
139
140 /* Read the MDI control register */
141 e100_mdi_read(bdp, MII_BMCR, phy_address, &ctrl_reg);
142
143 /* Read the status register twice, bacause of sticky bits */
144 e100_mdi_read(bdp, MII_BMSR, phy_address, &stat_reg);
145 e100_mdi_read(bdp, MII_BMSR, phy_address, &stat_reg);
146
147 if ((ctrl_reg == 0xffff) || ((stat_reg == 0) && (ctrl_reg == 0)))
148 return false;
149
150 return true;
151 }
152
153 static void
e100_phy_address_detect(struct e100_private * bdp)154 e100_phy_address_detect(struct e100_private *bdp)
155 {
156 unsigned int addr;
157 unsigned char valid_phy_found = false;
158
159 if (IS_NC3133(bdp)) {
160 bdp->phy_addr = 0;
161 return;
162 }
163
164 if (e100_phy_valid(bdp, PHY_DEFAULT_ADDRESS)) {
165 bdp->phy_addr = PHY_DEFAULT_ADDRESS;
166 valid_phy_found = true;
167
168 } else {
169 for (addr = MIN_PHY_ADDR; addr <= MAX_PHY_ADDR; addr++) {
170 if (e100_phy_valid(bdp, addr)) {
171 bdp->phy_addr = addr;
172 valid_phy_found = true;
173 break;
174 }
175 }
176 }
177
178 if (!valid_phy_found) {
179 bdp->phy_addr = PHY_ADDRESS_503;
180 }
181 }
182
183 static void
e100_phy_id_detect(struct e100_private * bdp)184 e100_phy_id_detect(struct e100_private *bdp)
185 {
186 u16 low_id_reg, high_id_reg;
187
188 if (bdp->phy_addr == PHY_ADDRESS_503) {
189 bdp->PhyId = PHY_503;
190 return;
191 }
192 if (!(bdp->flags & IS_ICH)) {
193 if (bdp->rev_id >= D102_REV_ID) {
194 bdp->PhyId = PHY_82562ET;
195 return;
196 }
197 }
198
199 /* Read phy id from the MII register */
200 e100_mdi_read(bdp, MII_PHYSID1, bdp->phy_addr, &low_id_reg);
201 e100_mdi_read(bdp, MII_PHYSID2, bdp->phy_addr, &high_id_reg);
202
203 bdp->PhyId = ((unsigned int) low_id_reg |
204 ((unsigned int) high_id_reg << 16));
205 }
206
207 static void
e100_phy_isolate(struct e100_private * bdp)208 e100_phy_isolate(struct e100_private *bdp)
209 {
210 unsigned int phy_address;
211 u16 ctrl_reg;
212
213 /* Go over all phy addresses. Deisolate the selected one, and isolate
214 * all the rest */
215 for (phy_address = 0; phy_address <= MAX_PHY_ADDR; phy_address++) {
216 if (phy_address != bdp->phy_addr) {
217 e100_mdi_write(bdp, MII_BMCR, phy_address,
218 BMCR_ISOLATE);
219
220 } else {
221 e100_mdi_read(bdp, MII_BMCR, bdp->phy_addr, &ctrl_reg);
222 ctrl_reg &= ~BMCR_ISOLATE;
223 e100_mdi_write(bdp, MII_BMCR, bdp->phy_addr, ctrl_reg);
224 }
225
226 udelay(100);
227 }
228 }
229
230 static unsigned char
e100_phy_specific_setup(struct e100_private * bdp)231 e100_phy_specific_setup(struct e100_private *bdp)
232 {
233 u16 misc_reg;
234
235 if (bdp->phy_addr == PHY_ADDRESS_503) {
236 switch (bdp->params.e100_speed_duplex) {
237 case E100_AUTONEG:
238 /* The adapter can't autoneg. so set to 10/HALF */
239 printk(KERN_INFO
240 "e100: 503 serial component detected which "
241 "cannot autonegotiate\n");
242 printk(KERN_INFO
243 "e100: speed/duplex forced to "
244 "10Mbps / Half duplex\n");
245 bdp->params.e100_speed_duplex = E100_SPEED_10_HALF;
246 break;
247
248 case E100_SPEED_100_HALF:
249 case E100_SPEED_100_FULL:
250 printk(KERN_ERR
251 "e100: 503 serial component detected "
252 "which does not support 100Mbps\n");
253 printk(KERN_ERR
254 "e100: Change the forced speed/duplex "
255 "to a supported setting\n");
256 return false;
257 }
258
259 return true;
260 }
261
262 if (IS_NC3133(bdp)) {
263 u16 int_reg;
264
265 /* enable 100BASE fiber interface */
266 e100_mdi_write(bdp, MDI_NC3133_CONFIG_REG, bdp->phy_addr,
267 MDI_NC3133_100FX_ENABLE);
268
269 if ((bdp->params.e100_speed_duplex != E100_AUTONEG) &&
270 (bdp->params.e100_speed_duplex != E100_SPEED_100_FULL)) {
271 /* just inform user about 100 full */
272 printk(KERN_ERR "e100: NC3133 NIC can only run "
273 "at 100Mbps full duplex\n");
274 }
275
276 bdp->params.e100_speed_duplex = E100_SPEED_100_FULL;
277
278 /* enable interrupts */
279 e100_mdi_read(bdp, MDI_NC3133_INT_ENABLE_REG,
280 bdp->phy_addr, &int_reg);
281 int_reg |= MDI_NC3133_INT_ENABLE;
282 e100_mdi_write(bdp, MDI_NC3133_INT_ENABLE_REG,
283 bdp->phy_addr, int_reg);
284 }
285
286 /* Handle the National TX */
287 if ((bdp->PhyId & PHY_MODEL_REV_ID_MASK) == PHY_NSC_TX) {
288 e100_mdi_read(bdp, NSC_CONG_CONTROL_REG,
289 bdp->phy_addr, &misc_reg);
290
291 misc_reg |= NSC_TX_CONG_TXREADY;
292
293 /* disable the congestion control bit in the National Phy */
294 misc_reg &= ~NSC_TX_CONG_ENABLE;
295
296 e100_mdi_write(bdp, NSC_CONG_CONTROL_REG,
297 bdp->phy_addr, misc_reg);
298 }
299
300 return true;
301 }
302
303 /*
304 * Procedure: e100_phy_fix_squelch
305 *
306 * Description:
307 * Help find link on certain rare scenarios.
308 * NOTE: This routine must be called once per watchdog,
309 * and *after* setting the current link state.
310 *
311 * Arguments:
312 * bdp - Ptr to this card's e100_bdconfig structure
313 *
314 * Returns:
315 * NOTHING
316 */
317 static void
e100_phy_fix_squelch(struct e100_private * bdp)318 e100_phy_fix_squelch(struct e100_private *bdp)
319 {
320 if ((bdp->PhyId != PHY_82555_TX) || (bdp->flags & DF_SPEED_FORCED))
321 return;
322
323 if (netif_carrier_ok(bdp->device)) {
324 switch (bdp->PhyState) {
325 case 0:
326 break;
327 case 1:
328 e100_mdi_write(bdp, PHY_82555_SPECIAL_CONTROL,
329 bdp->phy_addr, 0x0000);
330 break;
331 case 2:
332 e100_mdi_write(bdp, PHY_82555_MDI_EQUALIZER_CSR,
333 bdp->phy_addr, 0x3000);
334 break;
335 }
336 bdp->PhyState = 0;
337 bdp->PhyDelay = 0;
338
339 } else if (!bdp->PhyDelay--) {
340 switch (bdp->PhyState) {
341 case 0:
342 e100_mdi_write(bdp, PHY_82555_SPECIAL_CONTROL,
343 bdp->phy_addr, EXTENDED_SQUELCH_BIT);
344 bdp->PhyState = 1;
345 break;
346 case 1:
347 e100_mdi_write(bdp, PHY_82555_SPECIAL_CONTROL,
348 bdp->phy_addr, 0x0000);
349 e100_mdi_write(bdp, PHY_82555_MDI_EQUALIZER_CSR,
350 bdp->phy_addr, 0x2010);
351 bdp->PhyState = 2;
352 break;
353 case 2:
354 e100_mdi_write(bdp, PHY_82555_MDI_EQUALIZER_CSR,
355 bdp->phy_addr, 0x3000);
356 bdp->PhyState = 0;
357 break;
358 }
359
360 e100_mdi_write(bdp, MII_BMCR, bdp->phy_addr,
361 BMCR_ANENABLE | BMCR_ANRESTART);
362 bdp->PhyDelay = 3;
363 }
364 }
365
366 /*
367 * Procedure: e100_fix_polarity
368 *
369 * Description:
370 * Fix for 82555 auto-polarity toggle problem. With a short cable
371 * connecting an 82555 with an 840A link partner, if the medium is noisy,
372 * the 82555 sometime thinks that the polarity might be wrong and so
373 * toggles polarity. This happens repeatedly and results in a high bit
374 * error rate.
375 * NOTE: This happens only at 10 Mbps
376 *
377 * Arguments:
378 * bdp - Ptr to this card's e100_bdconfig structure
379 *
380 * Returns:
381 * NOTHING
382 */
383 static void
e100_fix_polarity(struct e100_private * bdp)384 e100_fix_polarity(struct e100_private *bdp)
385 {
386 u16 status;
387 u16 errors;
388 u16 misc_reg;
389 int speed;
390
391 if ((bdp->PhyId != PHY_82555_TX) && (bdp->PhyId != PHY_82562ET) &&
392 (bdp->PhyId != PHY_82562EM))
393 return;
394
395 /* If the user wants auto-polarity disabled, do only that and nothing *
396 * else. * e100_autopolarity == 0 means disable --- we do just the
397 * disabling * e100_autopolarity == 1 means enable --- we do nothing at
398 * all * e100_autopolarity >= 2 means we do the workaround code. */
399 /* Change for 82558 enhancement */
400 switch (E100_AUTOPOLARITY) {
401 case 0:
402 e100_mdi_read(bdp, PHY_82555_SPECIAL_CONTROL,
403 bdp->phy_addr, &misc_reg);
404 e100_mdi_write(bdp, PHY_82555_SPECIAL_CONTROL, bdp->phy_addr,
405 (u16) (misc_reg | DISABLE_AUTO_POLARITY));
406 break;
407
408 case 1:
409 e100_mdi_read(bdp, PHY_82555_SPECIAL_CONTROL,
410 bdp->phy_addr, &misc_reg);
411 e100_mdi_write(bdp, PHY_82555_SPECIAL_CONTROL, bdp->phy_addr,
412 (u16) (misc_reg & ~DISABLE_AUTO_POLARITY));
413 break;
414
415 case 2:
416 /* we do this only if link is up */
417 if (!netif_carrier_ok(bdp->device)) {
418 break;
419 }
420
421 e100_mdi_read(bdp, PHY_82555_CSR, bdp->phy_addr, &status);
422 speed = (status & PHY_82555_SPEED_BIT) ? 100 : 10;
423
424 /* we need to do this only if speed is 10 */
425 if (speed != 10) {
426 break;
427 }
428
429 /* see if we have any end of frame errors */
430 e100_mdi_read(bdp, PHY_82555_EOF_COUNTER,
431 bdp->phy_addr, &errors);
432
433 /* if non-zero, wait for 100 ms before reading again */
434 if (errors) {
435 udelay(200);
436 e100_mdi_read(bdp, PHY_82555_EOF_COUNTER,
437 bdp->phy_addr, &errors);
438
439 /* if non-zero again, we disable polarity */
440 if (errors) {
441 e100_mdi_read(bdp, PHY_82555_SPECIAL_CONTROL,
442 bdp->phy_addr, &misc_reg);
443 e100_mdi_write(bdp, PHY_82555_SPECIAL_CONTROL,
444 bdp->phy_addr,
445 (u16) (misc_reg |
446 DISABLE_AUTO_POLARITY));
447 }
448 }
449
450 if (!errors) {
451 /* it is safe to read the polarity now */
452 e100_mdi_read(bdp, PHY_82555_CSR,
453 bdp->phy_addr, &status);
454
455 /* if polarity is normal, disable polarity */
456 if (!(status & PHY_82555_POLARITY_BIT)) {
457 e100_mdi_read(bdp, PHY_82555_SPECIAL_CONTROL,
458 bdp->phy_addr, &misc_reg);
459 e100_mdi_write(bdp, PHY_82555_SPECIAL_CONTROL,
460 bdp->phy_addr,
461 (u16) (misc_reg |
462 DISABLE_AUTO_POLARITY));
463 }
464 }
465 break;
466
467 default:
468 break;
469 }
470 }
471
472 /*
473 * Procedure: e100_find_speed_duplex
474 *
475 * Description: This routine will figure out what line speed and duplex mode
476 * the PHY is currently using.
477 *
478 * Arguments:
479 * bdp - Ptr to this card's e100_bdconfig structure
480 *
481 * Returns:
482 * NOTHING
483 */
484 static void
e100_find_speed_duplex(struct e100_private * bdp)485 e100_find_speed_duplex(struct e100_private *bdp)
486 {
487 unsigned int PhyId;
488 u16 stat_reg, misc_reg;
489 u16 ad_reg, lp_ad_reg;
490
491 PhyId = bdp->PhyId & PHY_MODEL_REV_ID_MASK;
492
493 /* First we should check to see if we have link */
494 /* If we don't have a link no reason to print a speed and duplex */
495 if (!e100_update_link_state(bdp)) {
496 bdp->cur_line_speed = 0;
497 bdp->cur_dplx_mode = 0;
498 return;
499 }
500
501 /* On the 82559 and later controllers, speed/duplex is part of the *
502 * SCB. So, we save an mdi_read and get these from the SCB. * */
503 if (bdp->rev_id >= D101MA_REV_ID) {
504 /* Read speed */
505 if (readb(&bdp->scb->scb_ext.d101m_scb.scb_gen_stat) & BIT_1)
506 bdp->cur_line_speed = 100;
507 else
508 bdp->cur_line_speed = 10;
509
510 /* Read duplex */
511 if (readb(&bdp->scb->scb_ext.d101m_scb.scb_gen_stat) & BIT_2)
512 bdp->cur_dplx_mode = FULL_DUPLEX;
513 else
514 bdp->cur_dplx_mode = HALF_DUPLEX;
515
516 return;
517 }
518
519 /* If this is a Phy 100, then read bits 1 and 0 of extended register 0,
520 * to get the current speed and duplex settings. */
521 if ((PhyId == PHY_100_A) || (PhyId == PHY_100_C) ||
522 (PhyId == PHY_82555_TX)) {
523
524 /* Read Phy 100 extended register 0 */
525 e100_mdi_read(bdp, EXTENDED_REG_0, bdp->phy_addr, &misc_reg);
526
527 /* Get current speed setting */
528 if (misc_reg & PHY_100_ER0_SPEED_INDIC)
529 bdp->cur_line_speed = 100;
530 else
531 bdp->cur_line_speed = 10;
532
533 /* Get current duplex setting -- FDX enabled if bit is set */
534 if (misc_reg & PHY_100_ER0_FDX_INDIC)
535 bdp->cur_dplx_mode = FULL_DUPLEX;
536 else
537 bdp->cur_dplx_mode = HALF_DUPLEX;
538
539 return;
540 }
541
542 /* See if link partner is capable of Auto-Negotiation (bit 0, reg 6) */
543 e100_mdi_read(bdp, MII_EXPANSION, bdp->phy_addr, &misc_reg);
544
545 /* See if Auto-Negotiation was complete (bit 5, reg 1) */
546 e100_mdi_read(bdp, MII_BMSR, bdp->phy_addr, &stat_reg);
547
548 /* If a True NWAY connection was made, then we can detect speed/dplx
549 * by ANDing our adapter's advertised abilities with our link partner's
550 * advertised ablilities, and then assuming that the highest common
551 * denominator was chosed by NWAY. */
552 if ((misc_reg & EXPANSION_NWAY) && (stat_reg & BMSR_ANEGCOMPLETE)) {
553
554 /* Read our advertisement register */
555 e100_mdi_read(bdp, MII_ADVERTISE, bdp->phy_addr, &ad_reg);
556
557 /* Read our link partner's advertisement register */
558 e100_mdi_read(bdp, MII_LPA, bdp->phy_addr, &lp_ad_reg);
559
560 /* AND the two advertisement registers together, and get rid
561 * of any extraneous bits. */
562 ad_reg &= (lp_ad_reg & NWAY_LP_ABILITY);
563
564 /* Get speed setting */
565 if (ad_reg &
566 (ADVERTISE_100HALF | ADVERTISE_100FULL |
567 ADVERTISE_100BASE4))
568
569 bdp->cur_line_speed = 100;
570 else
571 bdp->cur_line_speed = 10;
572
573 /* Get duplex setting -- use priority resolution algorithm */
574 if (ad_reg & ADVERTISE_100BASE4) {
575 bdp->cur_dplx_mode = HALF_DUPLEX;
576 } else if (ad_reg & ADVERTISE_100FULL) {
577 bdp->cur_dplx_mode = FULL_DUPLEX;
578 } else if (ad_reg & ADVERTISE_100HALF) {
579 bdp->cur_dplx_mode = HALF_DUPLEX;
580 } else if (ad_reg & ADVERTISE_10FULL) {
581 bdp->cur_dplx_mode = FULL_DUPLEX;
582 } else {
583 bdp->cur_dplx_mode = HALF_DUPLEX;
584 }
585
586 return;
587 }
588
589 /* If we are connected to a dumb (non-NWAY) repeater or hub, and the
590 * line speed was determined automatically by parallel detection, then
591 * we have no way of knowing exactly what speed the PHY is set to
592 * unless that PHY has a propietary register which indicates speed in
593 * this situation. The NSC TX PHY does have such a register. Also,
594 * since NWAY didn't establish the connection, the duplex setting
595 * should HALF duplex. */
596 bdp->cur_dplx_mode = HALF_DUPLEX;
597
598 if (PhyId == PHY_NSC_TX) {
599 /* Read register 25 to get the SPEED_10 bit */
600 e100_mdi_read(bdp, NSC_SPEED_IND_REG, bdp->phy_addr, &misc_reg);
601
602 /* If bit 6 was set then we're at 10Mbps */
603 if (misc_reg & NSC_TX_SPD_INDC_SPEED)
604 bdp->cur_line_speed = 10;
605 else
606 bdp->cur_line_speed = 100;
607
608 } else {
609 /* If we don't know the line speed, default to 10Mbps */
610 bdp->cur_line_speed = 10;
611 }
612 }
613
614 /*
615 * Procedure: e100_force_speed_duplex
616 *
617 * Description: This routine forces line speed and duplex mode of the
618 * adapter based on the values the user has set in e100.c.
619 *
620 * Arguments: bdp - Pointer to the e100_private structure for the board
621 *
622 * Returns: void
623 *
624 */
625 void
e100_force_speed_duplex(struct e100_private * bdp)626 e100_force_speed_duplex(struct e100_private *bdp)
627 {
628 u16 control;
629 unsigned long expires;
630
631 bdp->flags |= DF_SPEED_FORCED;
632
633 e100_mdi_read(bdp, MII_BMCR, bdp->phy_addr, &control);
634 control &= ~BMCR_ANENABLE;
635 control &= ~BMCR_LOOPBACK;
636
637 switch (bdp->params.e100_speed_duplex) {
638 case E100_SPEED_10_HALF:
639 control &= ~BMCR_SPEED100;
640 control &= ~BMCR_FULLDPLX;
641 bdp->cur_line_speed = 10;
642 bdp->cur_dplx_mode = HALF_DUPLEX;
643 break;
644
645 case E100_SPEED_10_FULL:
646 control &= ~BMCR_SPEED100;
647 control |= BMCR_FULLDPLX;
648 bdp->cur_line_speed = 10;
649 bdp->cur_dplx_mode = FULL_DUPLEX;
650 break;
651
652 case E100_SPEED_100_HALF:
653 control |= BMCR_SPEED100;
654 control &= ~BMCR_FULLDPLX;
655 bdp->cur_line_speed = 100;
656 bdp->cur_dplx_mode = HALF_DUPLEX;
657 break;
658
659 case E100_SPEED_100_FULL:
660 control |= BMCR_SPEED100;
661 control |= BMCR_FULLDPLX;
662 bdp->cur_line_speed = 100;
663 bdp->cur_dplx_mode = FULL_DUPLEX;
664 break;
665 }
666
667 e100_mdi_write(bdp, MII_BMCR, bdp->phy_addr, control);
668
669 /* loop must run at least once */
670 expires = jiffies + 2 * HZ;
671 do {
672 if (e100_update_link_state(bdp) ||
673 time_after(jiffies, expires)) {
674 break;
675 } else {
676 yield();
677 }
678
679 } while (true);
680 }
681
682 void
e100_force_speed_duplex_to_phy(struct e100_private * bdp)683 e100_force_speed_duplex_to_phy(struct e100_private *bdp)
684 {
685 u16 control;
686
687 e100_mdi_read(bdp, MII_BMCR, bdp->phy_addr, &control);
688 control &= ~BMCR_ANENABLE;
689 control &= ~BMCR_LOOPBACK;
690
691 switch (bdp->params.e100_speed_duplex) {
692 case E100_SPEED_10_HALF:
693 control &= ~BMCR_SPEED100;
694 control &= ~BMCR_FULLDPLX;
695 break;
696
697 case E100_SPEED_10_FULL:
698 control &= ~BMCR_SPEED100;
699 control |= BMCR_FULLDPLX;
700 break;
701
702 case E100_SPEED_100_HALF:
703 control |= BMCR_SPEED100;
704 control &= ~BMCR_FULLDPLX;
705 break;
706
707 case E100_SPEED_100_FULL:
708 control |= BMCR_SPEED100;
709 control |= BMCR_FULLDPLX;
710 break;
711 }
712
713 /* Send speed/duplex command to PHY layer. */
714 e100_mdi_write(bdp, MII_BMCR, bdp->phy_addr, control);
715 }
716
717 /*
718 * Procedure: e100_set_fc
719 *
720 * Description: Checks the link's capability for flow control.
721 *
722 * Arguments: bdp - Pointer to the e100_private structure for the board
723 *
724 * Returns: void
725 *
726 */
727 static void
e100_set_fc(struct e100_private * bdp)728 e100_set_fc(struct e100_private *bdp)
729 {
730 u16 ad_reg;
731 u16 lp_ad_reg;
732 u16 exp_reg;
733
734 /* no flow control for 82557, forced links or half duplex */
735 if (!netif_carrier_ok(bdp->device) || (bdp->flags & DF_SPEED_FORCED) ||
736 (bdp->cur_dplx_mode == HALF_DUPLEX) ||
737 !(bdp->flags & IS_BACHELOR)) {
738
739 bdp->flags &= ~DF_LINK_FC_CAP;
740 return;
741 }
742
743 /* See if link partner is capable of Auto-Negotiation (bit 0, reg 6) */
744 e100_mdi_read(bdp, MII_EXPANSION, bdp->phy_addr, &exp_reg);
745
746 if (exp_reg & EXPANSION_NWAY) {
747 /* Read our advertisement register */
748 e100_mdi_read(bdp, MII_ADVERTISE, bdp->phy_addr, &ad_reg);
749
750 /* Read our link partner's advertisement register */
751 e100_mdi_read(bdp, MII_LPA, bdp->phy_addr, &lp_ad_reg);
752
753 ad_reg &= lp_ad_reg; /* AND the 2 ad registers */
754
755 if (ad_reg & NWAY_AD_FC_SUPPORTED)
756 bdp->flags |= DF_LINK_FC_CAP;
757 else
758 /* If link partner is capable of autoneg, but */
759 /* not capable of flow control, Received PAUSE */
760 /* frames are still honored, i.e., */
761 /* transmitted frames would be paused */
762 /* by incoming PAUSE frames */
763 bdp->flags |= DF_LINK_FC_TX_ONLY;
764
765 } else {
766 bdp->flags &= ~DF_LINK_FC_CAP;
767 }
768 }
769
770 /*
771 * Procedure: e100_phy_check
772 *
773 * Arguments: bdp - Pointer to the e100_private structure for the board
774 *
775 * Returns: true if link state was changed
776 * false otherwise
777 *
778 */
779 unsigned char
e100_phy_check(struct e100_private * bdp)780 e100_phy_check(struct e100_private *bdp)
781 {
782 unsigned char old_link;
783 unsigned char changed = false;
784
785 old_link = netif_carrier_ok(bdp->device) ? 1 : 0;
786 e100_find_speed_duplex(bdp);
787
788 if (!old_link && netif_carrier_ok(bdp->device)) {
789 e100_set_fc(bdp);
790 changed = true;
791 }
792
793 if (old_link && !netif_carrier_ok(bdp->device)) {
794 /* reset the zero lock state */
795 bdp->zlock_state = ZLOCK_INITIAL;
796
797 // set auto lock for phy auto-negotiation on link up
798 if ((bdp->PhyId & PHY_MODEL_REV_ID_MASK) == PHY_82555_TX)
799 e100_mdi_write(bdp, PHY_82555_MDI_EQUALIZER_CSR,
800 bdp->phy_addr, 0);
801 changed = true;
802 }
803
804 e100_phy_fix_squelch(bdp);
805 e100_handle_zlock(bdp);
806
807 return changed;
808 }
809
810 /*
811 * Procedure: e100_auto_neg
812 *
813 * Description: This routine will start autonegotiation and wait
814 * for it to complete
815 *
816 * Arguments:
817 * bdp - pointer to this card's e100_bdconfig structure
818 * force_restart - defines if autoneg should be restarted even if it
819 * has been completed before
820 * Returns:
821 * NOTHING
822 */
823 static void
e100_auto_neg(struct e100_private * bdp,unsigned char force_restart)824 e100_auto_neg(struct e100_private *bdp, unsigned char force_restart)
825 {
826 u16 stat_reg;
827 unsigned long expires;
828
829 bdp->flags &= ~DF_SPEED_FORCED;
830
831 e100_mdi_read(bdp, MII_BMSR, bdp->phy_addr, &stat_reg);
832 e100_mdi_read(bdp, MII_BMSR, bdp->phy_addr, &stat_reg);
833
834 /* if we are capable of performing autoneg then we restart if needed */
835 if ((stat_reg != 0xFFFF) && (stat_reg & BMSR_ANEGCAPABLE)) {
836
837 if ((!force_restart) &&
838 (stat_reg & BMSR_ANEGCOMPLETE)) {
839 goto exit;
840 }
841
842 e100_mdi_write(bdp, MII_BMCR, bdp->phy_addr,
843 BMCR_ANENABLE | BMCR_ANRESTART);
844
845 /* wait for autoneg to complete (up to 3 seconds) */
846 expires = jiffies + HZ * 3;
847 do {
848 /* now re-read the value. Sticky so read twice */
849 e100_mdi_read(bdp, MII_BMSR, bdp->phy_addr, &stat_reg);
850 e100_mdi_read(bdp, MII_BMSR, bdp->phy_addr, &stat_reg);
851
852 if ((stat_reg & BMSR_ANEGCOMPLETE) ||
853 time_after(jiffies, expires) ) {
854 goto exit;
855 } else {
856 yield();
857 }
858 } while (true);
859 }
860
861 exit:
862 e100_find_speed_duplex(bdp);
863 }
864
865 void
e100_phy_set_speed_duplex(struct e100_private * bdp,unsigned char force_restart)866 e100_phy_set_speed_duplex(struct e100_private *bdp, unsigned char force_restart)
867 {
868 if (bdp->params.e100_speed_duplex == E100_AUTONEG) {
869 if (bdp->rev_id >= D102_REV_ID)
870 /* Enable MDI/MDI-X auto switching */
871 e100_mdi_write(bdp, MII_NCONFIG, bdp->phy_addr,
872 MDI_MDIX_AUTO_SWITCH_ENABLE);
873 e100_auto_neg(bdp, force_restart);
874
875 } else {
876 if (bdp->rev_id >= D102_REV_ID)
877 /* Disable MDI/MDI-X auto switching */
878 e100_mdi_write(bdp, MII_NCONFIG, bdp->phy_addr,
879 MDI_MDIX_RESET_ALL_MASK);
880 e100_force_speed_duplex(bdp);
881 }
882
883 e100_set_fc(bdp);
884 }
885
886 void
e100_phy_autoneg(struct e100_private * bdp)887 e100_phy_autoneg(struct e100_private *bdp)
888 {
889 u16 ctrl_reg;
890
891 ctrl_reg = BMCR_ANENABLE | BMCR_ANRESTART | BMCR_RESET;
892
893 e100_mdi_write(bdp, MII_BMCR, bdp->phy_addr, ctrl_reg);
894
895 udelay(100);
896 }
897
898 void
e100_phy_set_loopback(struct e100_private * bdp)899 e100_phy_set_loopback(struct e100_private *bdp)
900 {
901 u16 ctrl_reg;
902 ctrl_reg = BMCR_LOOPBACK;
903 e100_mdi_write(bdp, MII_BMCR, bdp->phy_addr, ctrl_reg);
904 udelay(100);
905 }
906
907 void
e100_phy_reset(struct e100_private * bdp)908 e100_phy_reset(struct e100_private *bdp)
909 {
910 u16 ctrl_reg;
911 ctrl_reg = BMCR_RESET;
912 e100_mdi_write(bdp, MII_BMCR, bdp->phy_addr, ctrl_reg);
913 /* ieee 802.3 : The reset process shall be completed */
914 /* within 0.5 seconds from the settting of PHY reset bit. */
915 set_current_state(TASK_UNINTERRUPTIBLE);
916 schedule_timeout(HZ / 2);
917 }
918
919 unsigned char
e100_phy_init(struct e100_private * bdp)920 e100_phy_init(struct e100_private *bdp)
921 {
922 e100_phy_reset(bdp);
923 e100_phy_address_detect(bdp);
924 e100_phy_isolate(bdp);
925 e100_phy_id_detect(bdp);
926
927 if (!e100_phy_specific_setup(bdp))
928 return false;
929
930 bdp->PhyState = 0;
931 bdp->PhyDelay = 0;
932 bdp->zlock_state = ZLOCK_INITIAL;
933
934 e100_phy_set_speed_duplex(bdp, false);
935 e100_fix_polarity(bdp);
936
937 return true;
938 }
939
940 /*
941 * Procedure: e100_get_link_state
942 *
943 * Description: This routine checks the link status of the adapter
944 *
945 * Arguments: bdp - Pointer to the e100_private structure for the board
946 *
947 *
948 * Returns: true - If a link is found
949 * false - If there is no link
950 *
951 */
952 unsigned char
e100_get_link_state(struct e100_private * bdp)953 e100_get_link_state(struct e100_private *bdp)
954 {
955 unsigned char link = false;
956 u16 status;
957
958 /* Check link status */
959 /* If the controller is a 82559 or later one, link status is available
960 * from the CSR. This avoids the mdi_read. */
961 if (bdp->rev_id >= D101MA_REV_ID) {
962 if (readb(&bdp->scb->scb_ext.d101m_scb.scb_gen_stat) & BIT_0) {
963 link = true;
964 } else {
965 link = false;
966 }
967
968 } else {
969 /* Read the status register twice because of sticky bits */
970 e100_mdi_read(bdp, MII_BMSR, bdp->phy_addr, &status);
971 e100_mdi_read(bdp, MII_BMSR, bdp->phy_addr, &status);
972
973 if (status & BMSR_LSTATUS) {
974 link = true;
975 } else {
976 link = false;
977 }
978 }
979
980 return link;
981 }
982
983 /*
984 * Procedure: e100_update_link_state
985 *
986 * Description: This routine updates the link status of the adapter,
987 * also considering netif_running
988 *
989 * Arguments: bdp - Pointer to the e100_private structure for the board
990 *
991 *
992 * Returns: true - If a link is found
993 * false - If there is no link
994 *
995 */
996 unsigned char
e100_update_link_state(struct e100_private * bdp)997 e100_update_link_state(struct e100_private *bdp)
998 {
999 unsigned char link;
1000
1001 /* Logical AND PHY link & netif_running */
1002 link = e100_get_link_state(bdp) && netif_running(bdp->device);
1003
1004 if (link) {
1005 if (!netif_carrier_ok(bdp->device))
1006 netif_carrier_on(bdp->device);
1007 } else {
1008 if (netif_carrier_ok(bdp->device))
1009 netif_carrier_off(bdp->device);
1010 }
1011
1012 return link;
1013 }
1014
1015 /**************************************************************************\
1016 **
1017 ** PROC NAME: e100_handle_zlock
1018 ** This function manages a state machine that controls
1019 ** the driver's zero locking algorithm.
1020 ** This function is called by e100_watchdog() every ~2 second.
1021 ** States:
1022 ** The current link handling state is stored in
1023 ** bdp->zlock_state, and is one of:
1024 ** ZLOCK_INITIAL, ZLOCK_READING, ZLOCK_SLEEPING
1025 ** Detailed description of the states and the transitions
1026 ** between states is found below.
1027 ** Note that any time the link is down / there is a reset
1028 ** state will be changed outside this function to ZLOCK_INITIAL
1029 ** Algorithm:
1030 ** 1. If link is up & 100 Mbps continue else stay in #1:
1031 ** 2. Set 'auto lock'
1032 ** 3. Read & Store 100 times 'Zero' locked in 1 sec interval
1033 ** 4. If max zero read >= 0xB continue else goto 1
1034 ** 5. Set most popular 'Zero' read in #3
1035 ** 6. Sleep 5 minutes
1036 ** 7. Read number of errors, if it is > 300 goto 2 else goto 6
1037 ** Data Structures (in DRIVER_DATA):
1038 ** zlock_state - current state of the algorithm
1039 ** zlock_read_cnt - counts number of reads (up to 100)
1040 ** zlock_read_data[i] - counts number of times 'Zero' read was i, 0 <= i <= 15
1041 ** zlock_sleep_cnt - keeps track of "sleep" time (up to 300 secs = 5 minutes)
1042 **
1043 ** Parameters: DRIVER_DATA *bdp
1044 **
1045 ** bdp - Pointer to HSM's adapter data space
1046 **
1047 ** Return Value: NONE
1048 **
1049 ** See Also: e100_watchdog()
1050 **
1051 \**************************************************************************/
1052 void
e100_handle_zlock(struct e100_private * bdp)1053 e100_handle_zlock(struct e100_private *bdp)
1054 {
1055 u16 pos;
1056 u16 eq_reg;
1057 u16 err_cnt;
1058 u8 mpz; /* Most Popular Zero */
1059
1060 switch (bdp->zlock_state) {
1061 case ZLOCK_INITIAL:
1062
1063 if (((u8) bdp->rev_id <= D102_REV_ID) ||
1064 !(bdp->cur_line_speed == 100) ||
1065 !netif_carrier_ok(bdp->device)) {
1066 break;
1067 }
1068
1069 /* initialize hw and sw and start reading */
1070 e100_mdi_write(bdp, PHY_82555_MDI_EQUALIZER_CSR,
1071 bdp->phy_addr, 0);
1072 /* reset read counters: */
1073 bdp->zlock_read_cnt = 0;
1074 for (pos = 0; pos < 16; pos++)
1075 bdp->zlock_read_data[pos] = 0;
1076 /* start reading in the next call back: */
1077 bdp->zlock_state = ZLOCK_READING;
1078
1079 /* FALL THROUGH !! */
1080
1081 case ZLOCK_READING:
1082 /* state: reading (100 times) zero locked in 1 sec interval
1083 * prev states: ZLOCK_INITIAL
1084 * next states: ZLOCK_INITIAL, ZLOCK_SLEEPING */
1085
1086 e100_mdi_read(bdp, PHY_82555_MDI_EQUALIZER_CSR,
1087 bdp->phy_addr, &eq_reg);
1088 pos = (eq_reg & ZLOCK_ZERO_MASK) >> 4;
1089 bdp->zlock_read_data[pos]++;
1090 bdp->zlock_read_cnt++;
1091
1092 if (bdp->zlock_read_cnt == ZLOCK_MAX_READS) {
1093 /* check if we read a 'Zero' value of 0xB or greater */
1094 if ((bdp->zlock_read_data[0xB]) ||
1095 (bdp->zlock_read_data[0xC]) ||
1096 (bdp->zlock_read_data[0xD]) ||
1097 (bdp->zlock_read_data[0xE]) ||
1098 (bdp->zlock_read_data[0xF])) {
1099
1100 /* we've read 'Zero' value of 0xB or greater,
1101 * find most popular 'Zero' value and lock it */
1102 mpz = 0;
1103 /* this loop finds the most popular 'Zero': */
1104 for (pos = 1; pos < 16; pos++) {
1105 if (bdp->zlock_read_data[pos] >
1106 bdp->zlock_read_data[mpz])
1107
1108 mpz = pos;
1109 }
1110 /* now lock the most popular 'Zero': */
1111 eq_reg = (ZLOCK_SET_ZERO | mpz);
1112 e100_mdi_write(bdp,
1113 PHY_82555_MDI_EQUALIZER_CSR,
1114 bdp->phy_addr, eq_reg);
1115
1116 /* sleep for 5 minutes: */
1117 bdp->zlock_sleep_cnt = jiffies;
1118 bdp->zlock_state = ZLOCK_SLEEPING;
1119 /* we will be reading the # of errors after 5
1120 * minutes, so we need to reset the error
1121 * counters - these registers are self clearing
1122 * on read, so read them */
1123 e100_mdi_read(bdp, PHY_82555_SYMBOL_ERR,
1124 bdp->phy_addr, &err_cnt);
1125
1126 } else {
1127 /* we did not read a 'Zero' value of 0xB or
1128 * above. go back to the start */
1129 bdp->zlock_state = ZLOCK_INITIAL;
1130 }
1131
1132 }
1133 break;
1134
1135 case ZLOCK_SLEEPING:
1136 /* state: sleeping for 5 minutes
1137 * prev states: ZLOCK_READING
1138 * next states: ZLOCK_READING, ZLOCK_SLEEPING */
1139
1140 /* if 5 minutes have passed: */
1141 if ((jiffies - bdp->zlock_sleep_cnt) >= ZLOCK_MAX_SLEEP) {
1142 /* read and sum up the number of errors: */
1143 e100_mdi_read(bdp, PHY_82555_SYMBOL_ERR,
1144 bdp->phy_addr, &err_cnt);
1145 /* if we've more than 300 errors (this number was
1146 * calculated according to the spec max allowed errors
1147 * (80 errors per 1 million frames) for 5 minutes in
1148 * 100 Mbps (or the user specified max BER number) */
1149 if (err_cnt > bdp->params.ber) {
1150 /* start again in the next callback: */
1151 bdp->zlock_state = ZLOCK_INITIAL;
1152 } else {
1153 /* we don't have more errors than allowed,
1154 * sleep for 5 minutes */
1155 bdp->zlock_sleep_cnt = jiffies;
1156 }
1157 }
1158 break;
1159
1160 default:
1161 break;
1162 }
1163 }
1164