1 /* de4x5.c: A DIGITAL DC21x4x DECchip and DE425/DE434/DE435/DE450/DE500
2 ethernet driver for Linux.
3
4 Copyright 1994, 1995 Digital Equipment Corporation.
5
6 Testing resources for this driver have been made available
7 in part by NASA Ames Research Center (mjacob@nas.nasa.gov).
8
9 The author may be reached at davies@maniac.ultranet.com.
10
11 This program is free software; you can redistribute it and/or modify it
12 under the terms of the GNU General Public License as published by the
13 Free Software Foundation; either version 2 of the License, or (at your
14 option) any later version.
15
16 THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
17 WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
18 MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
19 NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20 INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
21 NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
22 USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
23 ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24 (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
25 THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26
27 You should have received a copy of the GNU General Public License along
28 with this program; if not, write to the Free Software Foundation, Inc.,
29 675 Mass Ave, Cambridge, MA 02139, USA.
30
31 Originally, this driver was written for the Digital Equipment
32 Corporation series of EtherWORKS ethernet cards:
33
34 DE425 TP/COAX EISA
35 DE434 TP PCI
36 DE435 TP/COAX/AUI PCI
37 DE450 TP/COAX/AUI PCI
38 DE500 10/100 PCI Fasternet
39
40 but it will now attempt to support all cards which conform to the
41 Digital Semiconductor SROM Specification. The driver currently
42 recognises the following chips:
43
44 DC21040 (no SROM)
45 DC21041[A]
46 DC21140[A]
47 DC21142
48 DC21143
49
50 So far the driver is known to work with the following cards:
51
52 KINGSTON
53 Linksys
54 ZNYX342
55 SMC8432
56 SMC9332 (w/new SROM)
57 ZNYX31[45]
58 ZNYX346 10/100 4 port (can act as a 10/100 bridge!)
59
60 The driver has been tested on a relatively busy network using the DE425,
61 DE434, DE435 and DE500 cards and benchmarked with 'ttcp': it transferred
62 16M of data to a DECstation 5000/200 as follows:
63
64 TCP UDP
65 TX RX TX RX
66 DE425 1030k 997k 1170k 1128k
67 DE434 1063k 995k 1170k 1125k
68 DE435 1063k 995k 1170k 1125k
69 DE500 1063k 998k 1170k 1125k in 10Mb/s mode
70
71 All values are typical (in kBytes/sec) from a sample of 4 for each
72 measurement. Their error is +/-20k on a quiet (private) network and also
73 depend on what load the CPU has.
74
75 =========================================================================
76 This driver has been written substantially from scratch, although its
77 inheritance of style and stack interface from 'ewrk3.c' and in turn from
78 Donald Becker's 'lance.c' should be obvious. With the module autoload of
79 every usable DECchip board, I pinched Donald's 'next_module' field to
80 link my modules together.
81
82 Upto 15 EISA cards can be supported under this driver, limited primarily
83 by the available IRQ lines. I have checked different configurations of
84 multiple depca, EtherWORKS 3 cards and de4x5 cards and have not found a
85 problem yet (provided you have at least depca.c v0.38) ...
86
87 PCI support has been added to allow the driver to work with the DE434,
88 DE435, DE450 and DE500 cards. The I/O accesses are a bit of a kludge due
89 to the differences in the EISA and PCI CSR address offsets from the base
90 address.
91
92 The ability to load this driver as a loadable module has been included
93 and used extensively during the driver development (to save those long
94 reboot sequences). Loadable module support under PCI and EISA has been
95 achieved by letting the driver autoprobe as if it were compiled into the
96 kernel. Do make sure you're not sharing interrupts with anything that
97 cannot accommodate interrupt sharing!
98
99 To utilise this ability, you have to do 8 things:
100
101 0) have a copy of the loadable modules code installed on your system.
102 1) copy de4x5.c from the /linux/drivers/net directory to your favourite
103 temporary directory.
104 2) for fixed autoprobes (not recommended), edit the source code near
105 line 5594 to reflect the I/O address you're using, or assign these when
106 loading by:
107
108 insmod de4x5 io=0xghh where g = bus number
109 hh = device number
110
111 NB: autoprobing for modules is now supported by default. You may just
112 use:
113
114 insmod de4x5
115
116 to load all available boards. For a specific board, still use
117 the 'io=?' above.
118 3) compile de4x5.c, but include -DMODULE in the command line to ensure
119 that the correct bits are compiled (see end of source code).
120 4) if you are wanting to add a new card, goto 5. Otherwise, recompile a
121 kernel with the de4x5 configuration turned off and reboot.
122 5) insmod de4x5 [io=0xghh]
123 6) run the net startup bits for your new eth?? interface(s) manually
124 (usually /etc/rc.inet[12] at boot time).
125 7) enjoy!
126
127 To unload a module, turn off the associated interface(s)
128 'ifconfig eth?? down' then 'rmmod de4x5'.
129
130 Automedia detection is included so that in principal you can disconnect
131 from, e.g. TP, reconnect to BNC and things will still work (after a
132 pause whilst the driver figures out where its media went). My tests
133 using ping showed that it appears to work....
134
135 By default, the driver will now autodetect any DECchip based card.
136 Should you have a need to restrict the driver to DIGITAL only cards, you
137 can compile with a DEC_ONLY define, or if loading as a module, use the
138 'dec_only=1' parameter.
139
140 I've changed the timing routines to use the kernel timer and scheduling
141 functions so that the hangs and other assorted problems that occurred
142 while autosensing the media should be gone. A bonus for the DC21040
143 auto media sense algorithm is that it can now use one that is more in
144 line with the rest (the DC21040 chip doesn't have a hardware timer).
145 The downside is the 1 'jiffies' (10ms) resolution.
146
147 IEEE 802.3u MII interface code has been added in anticipation that some
148 products may use it in the future.
149
150 The SMC9332 card has a non-compliant SROM which needs fixing - I have
151 patched this driver to detect it because the SROM format used complies
152 to a previous DEC-STD format.
153
154 I have removed the buffer copies needed for receive on Intels. I cannot
155 remove them for Alphas since the Tulip hardware only does longword
156 aligned DMA transfers and the Alphas get alignment traps with non
157 longword aligned data copies (which makes them really slow). No comment.
158
159 I have added SROM decoding routines to make this driver work with any
160 card that supports the Digital Semiconductor SROM spec. This will help
161 all cards running the dc2114x series chips in particular. Cards using
162 the dc2104x chips should run correctly with the basic driver. I'm in
163 debt to <mjacob@feral.com> for the testing and feedback that helped get
164 this feature working. So far we have tested KINGSTON, SMC8432, SMC9332
165 (with the latest SROM complying with the SROM spec V3: their first was
166 broken), ZNYX342 and LinkSys. ZYNX314 (dual 21041 MAC) and ZNYX 315
167 (quad 21041 MAC) cards also appear to work despite their incorrectly
168 wired IRQs.
169
170 I have added a temporary fix for interrupt problems when some SCSI cards
171 share the same interrupt as the DECchip based cards. The problem occurs
172 because the SCSI card wants to grab the interrupt as a fast interrupt
173 (runs the service routine with interrupts turned off) vs. this card
174 which really needs to run the service routine with interrupts turned on.
175 This driver will now add the interrupt service routine as a fast
176 interrupt if it is bounced from the slow interrupt. THIS IS NOT A
177 RECOMMENDED WAY TO RUN THE DRIVER and has been done for a limited time
178 until people sort out their compatibility issues and the kernel
179 interrupt service code is fixed. YOU SHOULD SEPARATE OUT THE FAST
180 INTERRUPT CARDS FROM THE SLOW INTERRUPT CARDS to ensure that they do not
181 run on the same interrupt. PCMCIA/CardBus is another can of worms...
182
183 Finally, I think I have really fixed the module loading problem with
184 more than one DECchip based card. As a side effect, I don't mess with
185 the device structure any more which means that if more than 1 card in
186 2.0.x is installed (4 in 2.1.x), the user will have to edit
187 linux/drivers/net/Space.c to make room for them. Hence, module loading
188 is the preferred way to use this driver, since it doesn't have this
189 limitation.
190
191 Where SROM media detection is used and full duplex is specified in the
192 SROM, the feature is ignored unless lp->params.fdx is set at compile
193 time OR during a module load (insmod de4x5 args='eth??:fdx' [see
194 below]). This is because there is no way to automatically detect full
195 duplex links except through autonegotiation. When I include the
196 autonegotiation feature in the SROM autoconf code, this detection will
197 occur automatically for that case.
198
199 Command line arguments are now allowed, similar to passing arguments
200 through LILO. This will allow a per adapter board set up of full duplex
201 and media. The only lexical constraints are: the board name (dev->name)
202 appears in the list before its parameters. The list of parameters ends
203 either at the end of the parameter list or with another board name. The
204 following parameters are allowed:
205
206 fdx for full duplex
207 autosense to set the media/speed; with the following
208 sub-parameters:
209 TP, TP_NW, BNC, AUI, BNC_AUI, 100Mb, 10Mb, AUTO
210
211 Case sensitivity is important for the sub-parameters. They *must* be
212 upper case. Examples:
213
214 insmod de4x5 args='eth1:fdx autosense=BNC eth0:autosense=100Mb'.
215
216 For a compiled in driver, at or above line 548, place e.g.
217 #define DE4X5_PARM "eth0:fdx autosense=AUI eth2:autosense=TP"
218
219 Yes, I know full duplex isn't permissible on BNC or AUI; they're just
220 examples. By default, full duplex is turned off and AUTO is the default
221 autosense setting. In reality, I expect only the full duplex option to
222 be used. Note the use of single quotes in the two examples above and the
223 lack of commas to separate items. ALSO, you must get the requested media
224 correct in relation to what the adapter SROM says it has. There's no way
225 to determine this in advance other than by trial and error and common
226 sense, e.g. call a BNC connectored port 'BNC', not '10Mb'.
227
228 Changed the bus probing. EISA used to be done first, followed by PCI.
229 Most people probably don't even know what a de425 is today and the EISA
230 probe has messed up some SCSI cards in the past, so now PCI is always
231 probed first followed by EISA if a) the architecture allows EISA and
232 either b) there have been no PCI cards detected or c) an EISA probe is
233 forced by the user. To force a probe include "force_eisa" in your
234 insmod "args" line; for built-in kernels either change the driver to do
235 this automatically or include #define DE4X5_FORCE_EISA on or before
236 line 1040 in the driver.
237
238 TO DO:
239 ------
240
241 Revision History
242 ----------------
243
244 Version Date Description
245
246 0.1 17-Nov-94 Initial writing. ALPHA code release.
247 0.2 13-Jan-95 Added PCI support for DE435's.
248 0.21 19-Jan-95 Added auto media detection.
249 0.22 10-Feb-95 Fix interrupt handler call <chris@cosy.sbg.ac.at>.
250 Fix recognition bug reported by <bkm@star.rl.ac.uk>.
251 Add request/release_region code.
252 Add loadable modules support for PCI.
253 Clean up loadable modules support.
254 0.23 28-Feb-95 Added DC21041 and DC21140 support.
255 Fix missed frame counter value and initialisation.
256 Fixed EISA probe.
257 0.24 11-Apr-95 Change delay routine to use <linux/udelay>.
258 Change TX_BUFFS_AVAIL macro.
259 Change media autodetection to allow manual setting.
260 Completed DE500 (DC21140) support.
261 0.241 18-Apr-95 Interim release without DE500 Autosense Algorithm.
262 0.242 10-May-95 Minor changes.
263 0.30 12-Jun-95 Timer fix for DC21140.
264 Portability changes.
265 Add ALPHA changes from <jestabro@ant.tay1.dec.com>.
266 Add DE500 semi automatic autosense.
267 Add Link Fail interrupt TP failure detection.
268 Add timer based link change detection.
269 Plugged a memory leak in de4x5_queue_pkt().
270 0.31 13-Jun-95 Fixed PCI stuff for 1.3.1.
271 0.32 26-Jun-95 Added verify_area() calls in de4x5_ioctl() from a
272 suggestion by <heiko@colossus.escape.de>.
273 0.33 8-Aug-95 Add shared interrupt support (not released yet).
274 0.331 21-Aug-95 Fix de4x5_open() with fast CPUs.
275 Fix de4x5_interrupt().
276 Fix dc21140_autoconf() mess.
277 No shared interrupt support.
278 0.332 11-Sep-95 Added MII management interface routines.
279 0.40 5-Mar-96 Fix setup frame timeout <maartenb@hpkuipc.cern.ch>.
280 Add kernel timer code (h/w is too flaky).
281 Add MII based PHY autosense.
282 Add new multicasting code.
283 Add new autosense algorithms for media/mode
284 selection using kernel scheduling/timing.
285 Re-formatted.
286 Made changes suggested by <jeff@router.patch.net>:
287 Change driver to detect all DECchip based cards
288 with DEC_ONLY restriction a special case.
289 Changed driver to autoprobe as a module. No irq
290 checking is done now - assume BIOS is good!
291 Added SMC9332 detection <manabe@Roy.dsl.tutics.ac.jp>
292 0.41 21-Mar-96 Don't check for get_hw_addr checksum unless DEC card
293 only <niles@axp745gsfc.nasa.gov>
294 Fix for multiple PCI cards reported by <jos@xos.nl>
295 Duh, put the SA_SHIRQ flag into request_interrupt().
296 Fix SMC ethernet address in enet_det[].
297 Print chip name instead of "UNKNOWN" during boot.
298 0.42 26-Apr-96 Fix MII write TA bit error.
299 Fix bug in dc21040 and dc21041 autosense code.
300 Remove buffer copies on receive for Intels.
301 Change sk_buff handling during media disconnects to
302 eliminate DUP packets.
303 Add dynamic TX thresholding.
304 Change all chips to use perfect multicast filtering.
305 Fix alloc_device() bug <jari@markkus2.fimr.fi>
306 0.43 21-Jun-96 Fix unconnected media TX retry bug.
307 Add Accton to the list of broken cards.
308 Fix TX under-run bug for non DC21140 chips.
309 Fix boot command probe bug in alloc_device() as
310 reported by <koen.gadeyne@barco.com> and
311 <orava@nether.tky.hut.fi>.
312 Add cache locks to prevent a race condition as
313 reported by <csd@microplex.com> and
314 <baba@beckman.uiuc.edu>.
315 Upgraded alloc_device() code.
316 0.431 28-Jun-96 Fix potential bug in queue_pkt() from discussion
317 with <csd@microplex.com>
318 0.44 13-Aug-96 Fix RX overflow bug in 2114[023] chips.
319 Fix EISA probe bugs reported by <os2@kpi.kharkov.ua>
320 and <michael@compurex.com>.
321 0.441 9-Sep-96 Change dc21041_autoconf() to probe quiet BNC media
322 with a loopback packet.
323 0.442 9-Sep-96 Include AUI in dc21041 media printout. Bug reported
324 by <bhat@mundook.cs.mu.OZ.AU>
325 0.45 8-Dec-96 Include endian functions for PPC use, from work
326 by <cort@cs.nmt.edu> and <g.thomas@opengroup.org>.
327 0.451 28-Dec-96 Added fix to allow autoprobe for modules after
328 suggestion from <mjacob@feral.com>.
329 0.5 30-Jan-97 Added SROM decoding functions.
330 Updated debug flags.
331 Fix sleep/wakeup calls for PCI cards, bug reported
332 by <cross@gweep.lkg.dec.com>.
333 Added multi-MAC, one SROM feature from discussion
334 with <mjacob@feral.com>.
335 Added full module autoprobe capability.
336 Added attempt to use an SMC9332 with broken SROM.
337 Added fix for ZYNX multi-mac cards that didn't
338 get their IRQs wired correctly.
339 0.51 13-Feb-97 Added endian fixes for the SROM accesses from
340 <paubert@iram.es>
341 Fix init_connection() to remove extra device reset.
342 Fix MAC/PHY reset ordering in dc21140m_autoconf().
343 Fix initialisation problem with lp->timeout in
344 typeX_infoblock() from <paubert@iram.es>.
345 Fix MII PHY reset problem from work done by
346 <paubert@iram.es>.
347 0.52 26-Apr-97 Some changes may not credit the right people -
348 a disk crash meant I lost some mail.
349 Change RX interrupt routine to drop rather than
350 defer packets to avoid hang reported by
351 <g.thomas@opengroup.org>.
352 Fix srom_exec() to return for COMPACT and type 1
353 infoblocks.
354 Added DC21142 and DC21143 functions.
355 Added byte counters from <phil@tazenda.demon.co.uk>
356 Added SA_INTERRUPT temporary fix from
357 <mjacob@feral.com>.
358 0.53 12-Nov-97 Fix the *_probe() to include 'eth??' name during
359 module load: bug reported by
360 <Piete.Brooks@cl.cam.ac.uk>
361 Fix multi-MAC, one SROM, to work with 2114x chips:
362 bug reported by <cmetz@inner.net>.
363 Make above search independent of BIOS device scan
364 direction.
365 Completed DC2114[23] autosense functions.
366 0.531 21-Dec-97 Fix DE500-XA 100Mb/s bug reported by
367 <robin@intercore.com
368 Fix type1_infoblock() bug introduced in 0.53, from
369 problem reports by
370 <parmee@postecss.ncrfran.france.ncr.com> and
371 <jo@ice.dillingen.baynet.de>.
372 Added argument list to set up each board from either
373 a module's command line or a compiled in #define.
374 Added generic MII PHY functionality to deal with
375 newer PHY chips.
376 Fix the mess in 2.1.67.
377 0.532 5-Jan-98 Fix bug in mii_get_phy() reported by
378 <redhat@cococo.net>.
379 Fix bug in pci_probe() for 64 bit systems reported
380 by <belliott@accessone.com>.
381 0.533 9-Jan-98 Fix more 64 bit bugs reported by <jal@cs.brown.edu>.
382 0.534 24-Jan-98 Fix last (?) endian bug from <geert@linux-m68k.org>
383 0.535 21-Feb-98 Fix Ethernet Address PROM reset bug for DC21040.
384 0.536 21-Mar-98 Change pci_probe() to use the pci_dev structure.
385 **Incompatible with 2.0.x from here.**
386 0.540 5-Jul-98 Atomicize assertion of dev->interrupt for SMP
387 from <lma@varesearch.com>
388 Add TP, AUI and BNC cases to 21140m_autoconf() for
389 case where a 21140 under SROM control uses, e.g. AUI
390 from problem report by <delchini@lpnp09.in2p3.fr>
391 Add MII parallel detection to 2114x_autoconf() for
392 case where no autonegotiation partner exists from
393 problem report by <mlapsley@ndirect.co.uk>.
394 Add ability to force connection type directly even
395 when using SROM control from problem report by
396 <earl@exis.net>.
397 Updated the PCI interface to conform with the latest
398 version. I hope nothing is broken...
399 Add TX done interrupt modification from suggestion
400 by <Austin.Donnelly@cl.cam.ac.uk>.
401 Fix is_anc_capable() bug reported by
402 <Austin.Donnelly@cl.cam.ac.uk>.
403 Fix type[13]_infoblock() bug: during MII search, PHY
404 lp->rst not run because lp->ibn not initialised -
405 from report & fix by <paubert@iram.es>.
406 Fix probe bug with EISA & PCI cards present from
407 report by <eirik@netcom.com>.
408 0.541 24-Aug-98 Fix compiler problems associated with i386-string
409 ops from multiple bug reports and temporary fix
410 from <paubert@iram.es>.
411 Fix pci_probe() to correctly emulate the old
412 pcibios_find_class() function.
413 Add an_exception() for old ZYNX346 and fix compile
414 warning on PPC & SPARC, from <ecd@skynet.be>.
415 Fix lastPCI to correctly work with compiled in
416 kernels and modules from bug report by
417 <Zlatko.Calusic@CARNet.hr> et al.
418 0.542 15-Sep-98 Fix dc2114x_autoconf() to stop multiple messages
419 when media is unconnected.
420 Change dev->interrupt to lp->interrupt to ensure
421 alignment for Alpha's and avoid their unaligned
422 access traps. This flag is merely for log messages:
423 should do something more definitive though...
424 0.543 30-Dec-98 Add SMP spin locking.
425 0.544 8-May-99 Fix for buggy SROM in Motorola embedded boards using
426 a 21143 by <mmporter@home.com>.
427 Change PCI/EISA bus probing order.
428 0.545 28-Nov-99 Further Moto SROM bug fix from
429 <mporter@eng.mcd.mot.com>
430 Remove double checking for DEBUG_RX in de4x5_dbg_rx()
431 from report by <geert@linux-m68k.org>
432 0.546 22-Feb-01 Fixes Alpha XP1000 oops. The srom_search function
433 was causing a page fault when initializing the
434 variable 'pb', on a non de4x5 PCI device, in this
435 case a PCI bridge (DEC chip 21152). The value of
436 'pb' is now only initialized if a de4x5 chip is
437 present.
438 <france@handhelds.org>
439 0.547 08-Nov-01 Use library crc32 functions by <Matt_Domsch@dell.com>
440 =========================================================================
441 */
442
443 static const char *version = "de4x5.c:V0.546 2001/02/22 davies@maniac.ultranet.com\n";
444
445 #include <linux/config.h>
446 #include <linux/module.h>
447
448 #include <linux/kernel.h>
449 #include <linux/sched.h>
450 #include <linux/string.h>
451 #include <linux/interrupt.h>
452 #include <linux/ptrace.h>
453 #include <linux/errno.h>
454 #include <linux/ioport.h>
455 #include <linux/slab.h>
456 #include <linux/pci.h>
457 #include <linux/delay.h>
458 #include <linux/init.h>
459 #include <linux/version.h>
460 #include <linux/spinlock.h>
461 #include <linux/crc32.h>
462
463 #include <asm/bitops.h>
464 #include <asm/io.h>
465 #include <asm/dma.h>
466 #include <asm/byteorder.h>
467 #include <asm/unaligned.h>
468 #include <asm/uaccess.h>
469 #ifdef CONFIG_PPC
470 #include <asm/machdep.h>
471 #endif /* CONFIG_PPC */
472
473 #include <linux/netdevice.h>
474 #include <linux/etherdevice.h>
475 #include <linux/skbuff.h>
476
477 #include <linux/time.h>
478 #include <linux/types.h>
479 #include <linux/unistd.h>
480 #include <linux/ctype.h>
481
482 #include "de4x5.h"
483
484 #define c_char const char
485 #define TWIDDLE(a) (u_short)le16_to_cpu(get_unaligned((u_short *)(a)))
486
487 /*
488 ** MII Information
489 */
490 struct phy_table {
491 int reset; /* Hard reset required? */
492 int id; /* IEEE OUI */
493 int ta; /* One cycle TA time - 802.3u is confusing here */
494 struct { /* Non autonegotiation (parallel) speed det. */
495 int reg;
496 int mask;
497 int value;
498 } spd;
499 };
500
501 struct mii_phy {
502 int reset; /* Hard reset required? */
503 int id; /* IEEE OUI */
504 int ta; /* One cycle TA time */
505 struct { /* Non autonegotiation (parallel) speed det. */
506 int reg;
507 int mask;
508 int value;
509 } spd;
510 int addr; /* MII address for the PHY */
511 u_char *gep; /* Start of GEP sequence block in SROM */
512 u_char *rst; /* Start of reset sequence in SROM */
513 u_int mc; /* Media Capabilities */
514 u_int ana; /* NWay Advertisement */
515 u_int fdx; /* Full DupleX capabilites for each media */
516 u_int ttm; /* Transmit Threshold Mode for each media */
517 u_int mci; /* 21142 MII Connector Interrupt info */
518 };
519
520 #define DE4X5_MAX_PHY 8 /* Allow upto 8 attached PHY devices per board */
521
522 struct sia_phy {
523 u_char mc; /* Media Code */
524 u_char ext; /* csr13-15 valid when set */
525 int csr13; /* SIA Connectivity Register */
526 int csr14; /* SIA TX/RX Register */
527 int csr15; /* SIA General Register */
528 int gepc; /* SIA GEP Control Information */
529 int gep; /* SIA GEP Data */
530 };
531
532 /*
533 ** Define the know universe of PHY devices that can be
534 ** recognised by this driver.
535 */
536 static struct phy_table phy_info[] = {
537 {0, NATIONAL_TX, 1, {0x19, 0x40, 0x00}}, /* National TX */
538 {1, BROADCOM_T4, 1, {0x10, 0x02, 0x02}}, /* Broadcom T4 */
539 {0, SEEQ_T4 , 1, {0x12, 0x10, 0x10}}, /* SEEQ T4 */
540 {0, CYPRESS_T4 , 1, {0x05, 0x20, 0x20}}, /* Cypress T4 */
541 {0, 0x7810 , 1, {0x14, 0x0800, 0x0800}} /* Level One LTX970 */
542 };
543
544 /*
545 ** These GENERIC values assumes that the PHY devices follow 802.3u and
546 ** allow parallel detection to set the link partner ability register.
547 ** Detection of 100Base-TX [H/F Duplex] and 100Base-T4 is supported.
548 */
549 #define GENERIC_REG 0x05 /* Autoneg. Link Partner Advertisement Reg. */
550 #define GENERIC_MASK MII_ANLPA_100M /* All 100Mb/s Technologies */
551 #define GENERIC_VALUE MII_ANLPA_100M /* 100B-TX, 100B-TX FDX, 100B-T4 */
552
553 /*
554 ** Define special SROM detection cases
555 */
556 static c_char enet_det[][ETH_ALEN] = {
557 {0x00, 0x00, 0xc0, 0x00, 0x00, 0x00},
558 {0x00, 0x00, 0xe8, 0x00, 0x00, 0x00}
559 };
560
561 #define SMC 1
562 #define ACCTON 2
563
564 /*
565 ** SROM Repair definitions. If a broken SROM is detected a card may
566 ** use this information to help figure out what to do. This is a
567 ** "stab in the dark" and so far for SMC9332's only.
568 */
569 static c_char srom_repair_info[][100] = {
570 {0x00,0x1e,0x00,0x00,0x00,0x08, /* SMC9332 */
571 0x1f,0x01,0x8f,0x01,0x00,0x01,0x00,0x02,
572 0x01,0x00,0x00,0x78,0xe0,0x01,0x00,0x50,
573 0x00,0x18,}
574 };
575
576
577 #ifdef DE4X5_DEBUG
578 static int de4x5_debug = DE4X5_DEBUG;
579 #else
580 /*static int de4x5_debug = (DEBUG_MII | DEBUG_SROM | DEBUG_PCICFG | DEBUG_MEDIA | DEBUG_VERSION);*/
581 static int de4x5_debug = (DEBUG_MEDIA | DEBUG_VERSION);
582 #endif
583
584 /*
585 ** Allow per adapter set up. For modules this is simply a command line
586 ** parameter, e.g.:
587 ** insmod de4x5 args='eth1:fdx autosense=BNC eth0:autosense=100Mb'.
588 **
589 ** For a compiled in driver, place e.g.
590 ** #define DE4X5_PARM "eth0:fdx autosense=AUI eth2:autosense=TP"
591 ** here
592 */
593 #ifdef DE4X5_PARM
594 static char *args = DE4X5_PARM;
595 #else
596 static char *args;
597 #endif
598
599 struct parameters {
600 int fdx;
601 int autosense;
602 };
603
604 #define DE4X5_AUTOSENSE_MS 250 /* msec autosense tick (DE500) */
605
606 #define DE4X5_NDA 0xffe0 /* No Device (I/O) Address */
607
608 /*
609 ** Ethernet PROM defines
610 */
611 #define PROBE_LENGTH 32
612 #define ETH_PROM_SIG 0xAA5500FFUL
613
614 /*
615 ** Ethernet Info
616 */
617 #define PKT_BUF_SZ 1536 /* Buffer size for each Tx/Rx buffer */
618 #define IEEE802_3_SZ 1518 /* Packet + CRC */
619 #define MAX_PKT_SZ 1514 /* Maximum ethernet packet length */
620 #define MAX_DAT_SZ 1500 /* Maximum ethernet data length */
621 #define MIN_DAT_SZ 1 /* Minimum ethernet data length */
622 #define PKT_HDR_LEN 14 /* Addresses and data length info */
623 #define FAKE_FRAME_LEN (MAX_PKT_SZ + 1)
624 #define QUEUE_PKT_TIMEOUT (3*HZ) /* 3 second timeout */
625
626
627 /*
628 ** EISA bus defines
629 */
630 #define DE4X5_EISA_IO_PORTS 0x0c00 /* I/O port base address, slot 0 */
631 #define DE4X5_EISA_TOTAL_SIZE 0x100 /* I/O address extent */
632
633 #define MAX_EISA_SLOTS 16
634 #define EISA_SLOT_INC 0x1000
635 #define EISA_ALLOWED_IRQ_LIST {5, 9, 10, 11}
636
637 #define DE4X5_SIGNATURE {"DE425","DE434","DE435","DE450","DE500"}
638 #define DE4X5_NAME_LENGTH 8
639
640 /*
641 ** Ethernet PROM defines for DC21040
642 */
643 #define PROBE_LENGTH 32
644 #define ETH_PROM_SIG 0xAA5500FFUL
645
646 /*
647 ** PCI Bus defines
648 */
649 #define PCI_MAX_BUS_NUM 8
650 #define DE4X5_PCI_TOTAL_SIZE 0x80 /* I/O address extent */
651 #define DE4X5_CLASS_CODE 0x00020000 /* Network controller, Ethernet */
652 #define NO_MORE_PCI -2 /* PCI bus search all done */
653
654 /*
655 ** Memory Alignment. Each descriptor is 4 longwords long. To force a
656 ** particular alignment on the TX descriptor, adjust DESC_SKIP_LEN and
657 ** DESC_ALIGN. ALIGN aligns the start address of the private memory area
658 ** and hence the RX descriptor ring's first entry.
659 */
660 #define DE4X5_ALIGN4 ((u_long)4 - 1) /* 1 longword align */
661 #define DE4X5_ALIGN8 ((u_long)8 - 1) /* 2 longword align */
662 #define DE4X5_ALIGN16 ((u_long)16 - 1) /* 4 longword align */
663 #define DE4X5_ALIGN32 ((u_long)32 - 1) /* 8 longword align */
664 #define DE4X5_ALIGN64 ((u_long)64 - 1) /* 16 longword align */
665 #define DE4X5_ALIGN128 ((u_long)128 - 1) /* 32 longword align */
666
667 #define DE4X5_ALIGN DE4X5_ALIGN32 /* Keep the DC21040 happy... */
668 #define DE4X5_CACHE_ALIGN CAL_16LONG
669 #define DESC_SKIP_LEN DSL_0 /* Must agree with DESC_ALIGN */
670 /*#define DESC_ALIGN u32 dummy[4]; / * Must agree with DESC_SKIP_LEN */
671 #define DESC_ALIGN
672
673 #ifndef DEC_ONLY /* See README.de4x5 for using this */
674 static int dec_only;
675 #else
676 static int dec_only = 1;
677 #endif
678
679 /*
680 ** DE4X5 IRQ ENABLE/DISABLE
681 */
682 #define ENABLE_IRQs { \
683 imr |= lp->irq_en;\
684 outl(imr, DE4X5_IMR); /* Enable the IRQs */\
685 }
686
687 #define DISABLE_IRQs {\
688 imr = inl(DE4X5_IMR);\
689 imr &= ~lp->irq_en;\
690 outl(imr, DE4X5_IMR); /* Disable the IRQs */\
691 }
692
693 #define UNMASK_IRQs {\
694 imr |= lp->irq_mask;\
695 outl(imr, DE4X5_IMR); /* Unmask the IRQs */\
696 }
697
698 #define MASK_IRQs {\
699 imr = inl(DE4X5_IMR);\
700 imr &= ~lp->irq_mask;\
701 outl(imr, DE4X5_IMR); /* Mask the IRQs */\
702 }
703
704 /*
705 ** DE4X5 START/STOP
706 */
707 #define START_DE4X5 {\
708 omr = inl(DE4X5_OMR);\
709 omr |= OMR_ST | OMR_SR;\
710 outl(omr, DE4X5_OMR); /* Enable the TX and/or RX */\
711 }
712
713 #define STOP_DE4X5 {\
714 omr = inl(DE4X5_OMR);\
715 omr &= ~(OMR_ST|OMR_SR);\
716 outl(omr, DE4X5_OMR); /* Disable the TX and/or RX */ \
717 }
718
719 /*
720 ** DE4X5 SIA RESET
721 */
722 #define RESET_SIA outl(0, DE4X5_SICR); /* Reset SIA connectivity regs */
723
724 /*
725 ** DE500 AUTOSENSE TIMER INTERVAL (MILLISECS)
726 */
727 #define DE4X5_AUTOSENSE_MS 250
728
729 /*
730 ** SROM Structure
731 */
732 struct de4x5_srom {
733 char sub_vendor_id[2];
734 char sub_system_id[2];
735 char reserved[12];
736 char id_block_crc;
737 char reserved2;
738 char version;
739 char num_controllers;
740 char ieee_addr[6];
741 char info[100];
742 short chksum;
743 };
744 #define SUB_VENDOR_ID 0x500a
745
746 /*
747 ** DE4X5 Descriptors. Make sure that all the RX buffers are contiguous
748 ** and have sizes of both a power of 2 and a multiple of 4.
749 ** A size of 256 bytes for each buffer could be chosen because over 90% of
750 ** all packets in our network are <256 bytes long and 64 longword alignment
751 ** is possible. 1536 showed better 'ttcp' performance. Take your pick. 32 TX
752 ** descriptors are needed for machines with an ALPHA CPU.
753 */
754 #define NUM_RX_DESC 8 /* Number of RX descriptors */
755 #define NUM_TX_DESC 32 /* Number of TX descriptors */
756 #define RX_BUFF_SZ 1536 /* Power of 2 for kmalloc and */
757 /* Multiple of 4 for DC21040 */
758 /* Allows 512 byte alignment */
759 struct de4x5_desc {
760 volatile s32 status;
761 u32 des1;
762 u32 buf;
763 u32 next;
764 DESC_ALIGN
765 };
766
767 /*
768 ** The DE4X5 private structure
769 */
770 #define DE4X5_PKT_STAT_SZ 16
771 #define DE4X5_PKT_BIN_SZ 128 /* Should be >=100 unless you
772 increase DE4X5_PKT_STAT_SZ */
773
774 struct pkt_stats {
775 u_int bins[DE4X5_PKT_STAT_SZ]; /* Private stats counters */
776 u_int unicast;
777 u_int multicast;
778 u_int broadcast;
779 u_int excessive_collisions;
780 u_int tx_underruns;
781 u_int excessive_underruns;
782 u_int rx_runt_frames;
783 u_int rx_collision;
784 u_int rx_dribble;
785 u_int rx_overflow;
786 };
787
788 struct de4x5_private {
789 char adapter_name[80]; /* Adapter name */
790 u_long interrupt; /* Aligned ISR flag */
791 struct de4x5_desc *rx_ring; /* RX descriptor ring */
792 struct de4x5_desc *tx_ring; /* TX descriptor ring */
793 struct sk_buff *tx_skb[NUM_TX_DESC]; /* TX skb for freeing when sent */
794 struct sk_buff *rx_skb[NUM_RX_DESC]; /* RX skb's */
795 int rx_new, rx_old; /* RX descriptor ring pointers */
796 int tx_new, tx_old; /* TX descriptor ring pointers */
797 char setup_frame[SETUP_FRAME_LEN]; /* Holds MCA and PA info. */
798 char frame[64]; /* Min sized packet for loopback*/
799 spinlock_t lock; /* Adapter specific spinlock */
800 struct net_device_stats stats; /* Public stats */
801 struct pkt_stats pktStats; /* Private stats counters */
802 char rxRingSize;
803 char txRingSize;
804 int bus; /* EISA or PCI */
805 int bus_num; /* PCI Bus number */
806 int device; /* Device number on PCI bus */
807 int state; /* Adapter OPENED or CLOSED */
808 int chipset; /* DC21040, DC21041 or DC21140 */
809 s32 irq_mask; /* Interrupt Mask (Enable) bits */
810 s32 irq_en; /* Summary interrupt bits */
811 int media; /* Media (eg TP), mode (eg 100B)*/
812 int c_media; /* Remember the last media conn */
813 int fdx; /* media full duplex flag */
814 int linkOK; /* Link is OK */
815 int autosense; /* Allow/disallow autosensing */
816 int tx_enable; /* Enable descriptor polling */
817 int setup_f; /* Setup frame filtering type */
818 int local_state; /* State within a 'media' state */
819 struct mii_phy phy[DE4X5_MAX_PHY]; /* List of attached PHY devices */
820 struct sia_phy sia; /* SIA PHY Information */
821 int active; /* Index to active PHY device */
822 int mii_cnt; /* Number of attached PHY's */
823 int timeout; /* Scheduling counter */
824 struct timer_list timer; /* Timer info for kernel */
825 int tmp; /* Temporary global per card */
826 struct {
827 void *priv; /* Original kmalloc'd mem addr */
828 u_long lock; /* Lock the cache accesses */
829 s32 csr0; /* Saved Bus Mode Register */
830 s32 csr6; /* Saved Operating Mode Reg. */
831 s32 csr7; /* Saved IRQ Mask Register */
832 s32 gep; /* Saved General Purpose Reg. */
833 s32 gepc; /* Control info for GEP */
834 s32 csr13; /* Saved SIA Connectivity Reg. */
835 s32 csr14; /* Saved SIA TX/RX Register */
836 s32 csr15; /* Saved SIA General Register */
837 int save_cnt; /* Flag if state already saved */
838 struct sk_buff *skb; /* Save the (re-ordered) skb's */
839 } cache;
840 struct de4x5_srom srom; /* A copy of the SROM */
841 struct net_device *next_module; /* Link to the next module */
842 int rx_ovf; /* Check for 'RX overflow' tag */
843 int useSROM; /* For non-DEC card use SROM */
844 int useMII; /* Infoblock using the MII */
845 int asBitValid; /* Autosense bits in GEP? */
846 int asPolarity; /* 0 => asserted high */
847 int asBit; /* Autosense bit number in GEP */
848 int defMedium; /* SROM default medium */
849 int tcount; /* Last infoblock number */
850 int infoblock_init; /* Initialised this infoblock? */
851 int infoleaf_offset; /* SROM infoleaf for controller */
852 s32 infoblock_csr6; /* csr6 value in SROM infoblock */
853 int infoblock_media; /* infoblock media */
854 int (*infoleaf_fn)(struct net_device *); /* Pointer to infoleaf function */
855 u_char *rst; /* Pointer to Type 5 reset info */
856 u_char ibn; /* Infoblock number */
857 struct parameters params; /* Command line/ #defined params */
858 struct pci_dev *pdev; /* Device cookie for DMA alloc */
859 dma_addr_t dma_rings; /* DMA handle for rings */
860 int dma_size; /* Size of the DMA area */
861 char *rx_bufs; /* rx bufs on alpha, sparc, ... */
862 };
863
864 /*
865 ** Kludge to get around the fact that the CSR addresses have different
866 ** offsets in the PCI and EISA boards. Also note that the ethernet address
867 ** PROM is accessed differently.
868 */
869 static struct de4x5_bus_type {
870 int bus;
871 int bus_num;
872 int device;
873 int chipset;
874 struct de4x5_srom srom;
875 int autosense;
876 int useSROM;
877 } bus;
878
879 /*
880 ** To get around certain poxy cards that don't provide an SROM
881 ** for the second and more DECchip, I have to key off the first
882 ** chip's address. I'll assume there's not a bad SROM iff:
883 **
884 ** o the chipset is the same
885 ** o the bus number is the same and > 0
886 ** o the sum of all the returned hw address bytes is 0 or 0x5fa
887 **
888 ** Also have to save the irq for those cards whose hardware designers
889 ** can't follow the PCI to PCI Bridge Architecture spec.
890 */
891 static struct {
892 int chipset;
893 int bus;
894 int irq;
895 u_char addr[ETH_ALEN];
896 } last = {0,};
897
898 /*
899 ** The transmit ring full condition is described by the tx_old and tx_new
900 ** pointers by:
901 ** tx_old = tx_new Empty ring
902 ** tx_old = tx_new+1 Full ring
903 ** tx_old+txRingSize = tx_new+1 Full ring (wrapped condition)
904 */
905 #define TX_BUFFS_AVAIL ((lp->tx_old<=lp->tx_new)?\
906 lp->tx_old+lp->txRingSize-lp->tx_new-1:\
907 lp->tx_old -lp->tx_new-1)
908
909 #define TX_PKT_PENDING (lp->tx_old != lp->tx_new)
910
911 /*
912 ** Public Functions
913 */
914 static int de4x5_open(struct net_device *dev);
915 static int de4x5_queue_pkt(struct sk_buff *skb, struct net_device *dev);
916 static void de4x5_interrupt(int irq, void *dev_id, struct pt_regs *regs);
917 static int de4x5_close(struct net_device *dev);
918 static struct net_device_stats *de4x5_get_stats(struct net_device *dev);
919 static void de4x5_local_stats(struct net_device *dev, char *buf, int pkt_len);
920 static void set_multicast_list(struct net_device *dev);
921 static int de4x5_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
922
923 /*
924 ** Private functions
925 */
926 static int de4x5_hw_init(struct net_device *dev, u_long iobase, struct pci_dev *pdev);
927 static int de4x5_init(struct net_device *dev);
928 static int de4x5_sw_reset(struct net_device *dev);
929 static int de4x5_rx(struct net_device *dev);
930 static int de4x5_tx(struct net_device *dev);
931 static int de4x5_ast(struct net_device *dev);
932 static int de4x5_txur(struct net_device *dev);
933 static int de4x5_rx_ovfc(struct net_device *dev);
934
935 static int autoconf_media(struct net_device *dev);
936 static void create_packet(struct net_device *dev, char *frame, int len);
937 static void load_packet(struct net_device *dev, char *buf, u32 flags, struct sk_buff *skb);
938 static int dc21040_autoconf(struct net_device *dev);
939 static int dc21041_autoconf(struct net_device *dev);
940 static int dc21140m_autoconf(struct net_device *dev);
941 static int dc2114x_autoconf(struct net_device *dev);
942 static int srom_autoconf(struct net_device *dev);
943 static int de4x5_suspect_state(struct net_device *dev, int timeout, int prev_state, int (*fn)(struct net_device *, int), int (*asfn)(struct net_device *));
944 static int dc21040_state(struct net_device *dev, int csr13, int csr14, int csr15, int timeout, int next_state, int suspect_state, int (*fn)(struct net_device *, int));
945 static int test_media(struct net_device *dev, s32 irqs, s32 irq_mask, s32 csr13, s32 csr14, s32 csr15, s32 msec);
946 static int test_for_100Mb(struct net_device *dev, int msec);
947 static int wait_for_link(struct net_device *dev);
948 static int test_mii_reg(struct net_device *dev, int reg, int mask, int pol, long msec);
949 static int is_spd_100(struct net_device *dev);
950 static int is_100_up(struct net_device *dev);
951 static int is_10_up(struct net_device *dev);
952 static int is_anc_capable(struct net_device *dev);
953 static int ping_media(struct net_device *dev, int msec);
954 static struct sk_buff *de4x5_alloc_rx_buff(struct net_device *dev, int index, int len);
955 static void de4x5_free_rx_buffs(struct net_device *dev);
956 static void de4x5_free_tx_buffs(struct net_device *dev);
957 static void de4x5_save_skbs(struct net_device *dev);
958 static void de4x5_rst_desc_ring(struct net_device *dev);
959 static void de4x5_cache_state(struct net_device *dev, int flag);
960 static void de4x5_put_cache(struct net_device *dev, struct sk_buff *skb);
961 static void de4x5_putb_cache(struct net_device *dev, struct sk_buff *skb);
962 static struct sk_buff *de4x5_get_cache(struct net_device *dev);
963 static void de4x5_setup_intr(struct net_device *dev);
964 static void de4x5_init_connection(struct net_device *dev);
965 static int de4x5_reset_phy(struct net_device *dev);
966 static void reset_init_sia(struct net_device *dev, s32 sicr, s32 strr, s32 sigr);
967 static int test_ans(struct net_device *dev, s32 irqs, s32 irq_mask, s32 msec);
968 static int test_tp(struct net_device *dev, s32 msec);
969 static int EISA_signature(char *name, s32 eisa_id);
970 static int PCI_signature(char *name, struct de4x5_bus_type *lp);
971 static void DevicePresent(u_long iobase);
972 static void enet_addr_rst(u_long aprom_addr);
973 static int de4x5_bad_srom(struct de4x5_bus_type *lp);
974 static short srom_rd(u_long address, u_char offset);
975 static void srom_latch(u_int command, u_long address);
976 static void srom_command(u_int command, u_long address);
977 static void srom_address(u_int command, u_long address, u_char offset);
978 static short srom_data(u_int command, u_long address);
979 /*static void srom_busy(u_int command, u_long address);*/
980 static void sendto_srom(u_int command, u_long addr);
981 static int getfrom_srom(u_long addr);
982 static int srom_map_media(struct net_device *dev);
983 static int srom_infoleaf_info(struct net_device *dev);
984 static void srom_init(struct net_device *dev);
985 static void srom_exec(struct net_device *dev, u_char *p);
986 static int mii_rd(u_char phyreg, u_char phyaddr, u_long ioaddr);
987 static void mii_wr(int data, u_char phyreg, u_char phyaddr, u_long ioaddr);
988 static int mii_rdata(u_long ioaddr);
989 static void mii_wdata(int data, int len, u_long ioaddr);
990 static void mii_ta(u_long rw, u_long ioaddr);
991 static int mii_swap(int data, int len);
992 static void mii_address(u_char addr, u_long ioaddr);
993 static void sendto_mii(u32 command, int data, u_long ioaddr);
994 static int getfrom_mii(u32 command, u_long ioaddr);
995 static int mii_get_oui(u_char phyaddr, u_long ioaddr);
996 static int mii_get_phy(struct net_device *dev);
997 static void SetMulticastFilter(struct net_device *dev);
998 static int get_hw_addr(struct net_device *dev);
999 static void srom_repair(struct net_device *dev, int card);
1000 static int test_bad_enet(struct net_device *dev, int status);
1001 static int an_exception(struct de4x5_bus_type *lp);
1002 #ifdef CONFIG_EISA
1003 static void eisa_probe(struct net_device *dev, u_long iobase);
1004 #endif
1005 static void pci_probe(struct net_device *dev, u_long iobase);
1006 static void srom_search(struct pci_dev *pdev);
1007 static char *build_setup_frame(struct net_device *dev, int mode);
1008 static void disable_ast(struct net_device *dev);
1009 static void enable_ast(struct net_device *dev, u32 time_out);
1010 static long de4x5_switch_mac_port(struct net_device *dev);
1011 static int gep_rd(struct net_device *dev);
1012 static void gep_wr(s32 data, struct net_device *dev);
1013 static void timeout(struct net_device *dev, void (*fn)(u_long data), u_long data, u_long msec);
1014 static void yawn(struct net_device *dev, int state);
1015 static void link_modules(struct net_device *dev, struct net_device *tmp);
1016 static void de4x5_parse_params(struct net_device *dev);
1017 static void de4x5_dbg_open(struct net_device *dev);
1018 static void de4x5_dbg_mii(struct net_device *dev, int k);
1019 static void de4x5_dbg_media(struct net_device *dev);
1020 static void de4x5_dbg_srom(struct de4x5_srom *p);
1021 static void de4x5_dbg_rx(struct sk_buff *skb, int len);
1022 static int de4x5_strncmp(char *a, char *b, int n);
1023 static int dc21041_infoleaf(struct net_device *dev);
1024 static int dc21140_infoleaf(struct net_device *dev);
1025 static int dc21142_infoleaf(struct net_device *dev);
1026 static int dc21143_infoleaf(struct net_device *dev);
1027 static int type0_infoblock(struct net_device *dev, u_char count, u_char *p);
1028 static int type1_infoblock(struct net_device *dev, u_char count, u_char *p);
1029 static int type2_infoblock(struct net_device *dev, u_char count, u_char *p);
1030 static int type3_infoblock(struct net_device *dev, u_char count, u_char *p);
1031 static int type4_infoblock(struct net_device *dev, u_char count, u_char *p);
1032 static int type5_infoblock(struct net_device *dev, u_char count, u_char *p);
1033 static int compact_infoblock(struct net_device *dev, u_char count, u_char *p);
1034
1035 #ifdef MODULE
1036 int init_module(void);
1037 void cleanup_module(void);
1038 static struct net_device *unlink_modules(struct net_device *p);
1039 static struct net_device *insert_device(struct net_device *dev, u_long iobase,
1040 int (*init)(struct net_device *));
1041 static int count_adapters(void);
1042 static int loading_module = 1;
1043 MODULE_PARM(de4x5_debug, "i");
1044 MODULE_PARM(dec_only, "i");
1045 MODULE_PARM(args, "s");
1046 MODULE_PARM_DESC(de4x5_debug, "de4x5 debug mask");
1047 MODULE_PARM_DESC(dec_only, "de4x5 probe only for Digital boards (0-1)");
1048 MODULE_PARM_DESC(args, "de4x5 full duplex and media type settings; see de4x5.c for details");
1049 MODULE_LICENSE("GPL");
1050
1051 # else
1052 static int loading_module;
1053 #endif /* MODULE */
1054
1055 static char name[DE4X5_NAME_LENGTH + 1];
1056 #ifdef CONFIG_EISA
1057 static u_char de4x5_irq[] = EISA_ALLOWED_IRQ_LIST;
1058 static int lastEISA;
1059 # ifdef DE4X5_FORCE_EISA /* Force an EISA bus probe or not */
1060 static int forceEISA = 1;
1061 # else
1062 static int forceEISA;
1063 # endif
1064 #endif
1065 static int num_de4x5s;
1066 static int cfrv, useSROM;
1067 static int lastPCI = -1;
1068 static struct net_device *lastModule;
1069 static struct pci_dev *pdev;
1070
1071 /*
1072 ** List the SROM infoleaf functions and chipsets
1073 */
1074 struct InfoLeaf {
1075 int chipset;
1076 int (*fn)(struct net_device *);
1077 };
1078 static struct InfoLeaf infoleaf_array[] = {
1079 {DC21041, dc21041_infoleaf},
1080 {DC21140, dc21140_infoleaf},
1081 {DC21142, dc21142_infoleaf},
1082 {DC21143, dc21143_infoleaf}
1083 };
1084 #define INFOLEAF_SIZE (sizeof(infoleaf_array)/(sizeof(int)+sizeof(int *)))
1085
1086 /*
1087 ** List the SROM info block functions
1088 */
1089 static int (*dc_infoblock[])(struct net_device *dev, u_char, u_char *) = {
1090 type0_infoblock,
1091 type1_infoblock,
1092 type2_infoblock,
1093 type3_infoblock,
1094 type4_infoblock,
1095 type5_infoblock,
1096 compact_infoblock
1097 };
1098
1099 #define COMPACT (sizeof(dc_infoblock)/sizeof(int *) - 1)
1100
1101 /*
1102 ** Miscellaneous defines...
1103 */
1104 #define RESET_DE4X5 {\
1105 int i;\
1106 i=inl(DE4X5_BMR);\
1107 mdelay(1);\
1108 outl(i | BMR_SWR, DE4X5_BMR);\
1109 mdelay(1);\
1110 outl(i, DE4X5_BMR);\
1111 mdelay(1);\
1112 for (i=0;i<5;i++) {inl(DE4X5_BMR); mdelay(1);}\
1113 mdelay(1);\
1114 }
1115
1116 #define PHY_HARD_RESET {\
1117 outl(GEP_HRST, DE4X5_GEP); /* Hard RESET the PHY dev. */\
1118 mdelay(1); /* Assert for 1ms */\
1119 outl(0x00, DE4X5_GEP);\
1120 mdelay(2); /* Wait for 2ms */\
1121 }
1122
1123
1124 /*
1125 ** Autoprobing in modules is allowed here. See the top of the file for
1126 ** more info.
1127 */
1128 int __init
de4x5_probe(struct net_device * dev)1129 de4x5_probe(struct net_device *dev)
1130 {
1131 u_long iobase = dev->base_addr;
1132
1133 pci_probe(dev, iobase);
1134 #ifdef CONFIG_EISA
1135 if ((lastPCI == NO_MORE_PCI) && ((num_de4x5s == 0) || forceEISA)) {
1136 eisa_probe(dev, iobase);
1137 }
1138 #endif
1139
1140 return (dev->priv ? 0 : -ENODEV);
1141 }
1142
1143 static int __init
de4x5_hw_init(struct net_device * dev,u_long iobase,struct pci_dev * pdev)1144 de4x5_hw_init(struct net_device *dev, u_long iobase, struct pci_dev *pdev)
1145 {
1146 struct de4x5_bus_type *lp = &bus;
1147 int i, status=0;
1148 char *tmp;
1149
1150 /* Ensure we're not sleeping */
1151 if (lp->bus == EISA) {
1152 outb(WAKEUP, PCI_CFPM);
1153 } else {
1154 pcibios_write_config_byte(lp->bus_num, lp->device << 3,
1155 PCI_CFDA_PSM, WAKEUP);
1156 }
1157 mdelay(10);
1158
1159 RESET_DE4X5;
1160
1161 if ((inl(DE4X5_STS) & (STS_TS | STS_RS)) != 0) {
1162 return -ENXIO; /* Hardware could not reset */
1163 }
1164
1165 /*
1166 ** Now find out what kind of DC21040/DC21041/DC21140 board we have.
1167 */
1168 useSROM = FALSE;
1169 if (lp->bus == PCI) {
1170 PCI_signature(name, lp);
1171 } else {
1172 EISA_signature(name, EISA_ID0);
1173 }
1174
1175 if (*name == '\0') { /* Not found a board signature */
1176 return -ENXIO;
1177 }
1178
1179 dev->base_addr = iobase;
1180 if (lp->bus == EISA) {
1181 printk("%s: %s at 0x%04lx (EISA slot %ld)",
1182 dev->name, name, iobase, ((iobase>>12)&0x0f));
1183 } else { /* PCI port address */
1184 printk("%s: %s at 0x%04lx (PCI bus %d, device %d)", dev->name, name,
1185 iobase, lp->bus_num, lp->device);
1186 }
1187
1188 printk(", h/w address ");
1189 status = get_hw_addr(dev);
1190 for (i = 0; i < ETH_ALEN - 1; i++) { /* get the ethernet addr. */
1191 printk("%2.2x:", dev->dev_addr[i]);
1192 }
1193 printk("%2.2x,\n", dev->dev_addr[i]);
1194
1195 if (status != 0) {
1196 printk(" which has an Ethernet PROM CRC error.\n");
1197 return -ENXIO;
1198 } else {
1199 struct de4x5_private *lp;
1200
1201 /*
1202 ** Reserve a section of kernel memory for the adapter
1203 ** private area and the TX/RX descriptor rings.
1204 */
1205 dev->priv = (void *) kmalloc(sizeof(struct de4x5_private) + DE4X5_ALIGN,
1206 GFP_KERNEL);
1207 if (dev->priv == NULL) {
1208 return -ENOMEM;
1209 }
1210
1211 /*
1212 ** Align to a longword boundary
1213 */
1214 tmp = dev->priv;
1215 dev->priv = (void *)(((u_long)dev->priv + DE4X5_ALIGN) & ~DE4X5_ALIGN);
1216 lp = (struct de4x5_private *)dev->priv;
1217 memset(dev->priv, 0, sizeof(struct de4x5_private));
1218 lp->bus = bus.bus;
1219 lp->bus_num = bus.bus_num;
1220 lp->device = bus.device;
1221 lp->chipset = bus.chipset;
1222 lp->cache.priv = tmp;
1223 lp->cache.gepc = GEP_INIT;
1224 lp->asBit = GEP_SLNK;
1225 lp->asPolarity = GEP_SLNK;
1226 lp->asBitValid = TRUE;
1227 lp->timeout = -1;
1228 lp->useSROM = useSROM;
1229 lp->pdev = pdev;
1230 memcpy((char *)&lp->srom,(char *)&bus.srom,sizeof(struct de4x5_srom));
1231 lp->lock = (spinlock_t) SPIN_LOCK_UNLOCKED;
1232 init_timer(&lp->timer);
1233 de4x5_parse_params(dev);
1234
1235 /*
1236 ** Choose correct autosensing in case someone messed up
1237 */
1238 lp->autosense = lp->params.autosense;
1239 if (lp->chipset != DC21140) {
1240 if ((lp->chipset==DC21040) && (lp->params.autosense&TP_NW)) {
1241 lp->params.autosense = TP;
1242 }
1243 if ((lp->chipset==DC21041) && (lp->params.autosense&BNC_AUI)) {
1244 lp->params.autosense = BNC;
1245 }
1246 }
1247 lp->fdx = lp->params.fdx;
1248 sprintf(lp->adapter_name,"%s (%s)", name, dev->name);
1249
1250 lp->dma_size = (NUM_RX_DESC + NUM_TX_DESC) * sizeof(struct de4x5_desc);
1251 #if defined(__alpha__) || defined(__powerpc__) || defined(__sparc_v9__) || defined(DE4X5_DO_MEMCPY)
1252 lp->dma_size += RX_BUFF_SZ * NUM_RX_DESC + DE4X5_ALIGN;
1253 #endif
1254 lp->rx_ring = pci_alloc_consistent(pdev, lp->dma_size, &lp->dma_rings);
1255 if (lp->rx_ring == NULL) {
1256 kfree(lp->cache.priv);
1257 lp->cache.priv = NULL;
1258 return -ENOMEM;
1259 }
1260
1261 lp->tx_ring = lp->rx_ring + NUM_RX_DESC;
1262
1263 /*
1264 ** Set up the RX descriptor ring (Intels)
1265 ** Allocate contiguous receive buffers, long word aligned (Alphas)
1266 */
1267 #if !defined(__alpha__) && !defined(__powerpc__) && !defined(__sparc_v9__) && !defined(DE4X5_DO_MEMCPY)
1268 for (i=0; i<NUM_RX_DESC; i++) {
1269 lp->rx_ring[i].status = 0;
1270 lp->rx_ring[i].des1 = cpu_to_le32(RX_BUFF_SZ);
1271 lp->rx_ring[i].buf = 0;
1272 lp->rx_ring[i].next = 0;
1273 lp->rx_skb[i] = (struct sk_buff *) 1; /* Dummy entry */
1274 }
1275
1276 #else
1277 {
1278 dma_addr_t dma_rx_bufs;
1279
1280 dma_rx_bufs = lp->dma_rings + (NUM_RX_DESC + NUM_TX_DESC)
1281 * sizeof(struct de4x5_desc);
1282 dma_rx_bufs = (dma_rx_bufs + DE4X5_ALIGN) & ~DE4X5_ALIGN;
1283 lp->rx_bufs = (char *)(((long)(lp->rx_ring + NUM_RX_DESC
1284 + NUM_TX_DESC) + DE4X5_ALIGN) & ~DE4X5_ALIGN);
1285 for (i=0; i<NUM_RX_DESC; i++) {
1286 lp->rx_ring[i].status = 0;
1287 lp->rx_ring[i].des1 = cpu_to_le32(RX_BUFF_SZ);
1288 lp->rx_ring[i].buf =
1289 cpu_to_le32(dma_rx_bufs+i*RX_BUFF_SZ);
1290 lp->rx_ring[i].next = 0;
1291 lp->rx_skb[i] = (struct sk_buff *) 1; /* Dummy entry */
1292 }
1293
1294 }
1295 #endif
1296
1297 barrier();
1298
1299 request_region(iobase, (lp->bus == PCI ? DE4X5_PCI_TOTAL_SIZE :
1300 DE4X5_EISA_TOTAL_SIZE),
1301 lp->adapter_name);
1302
1303 lp->rxRingSize = NUM_RX_DESC;
1304 lp->txRingSize = NUM_TX_DESC;
1305
1306 /* Write the end of list marker to the descriptor lists */
1307 lp->rx_ring[lp->rxRingSize - 1].des1 |= cpu_to_le32(RD_RER);
1308 lp->tx_ring[lp->txRingSize - 1].des1 |= cpu_to_le32(TD_TER);
1309
1310 /* Tell the adapter where the TX/RX rings are located. */
1311 outl(lp->dma_rings, DE4X5_RRBA);
1312 outl(lp->dma_rings + NUM_RX_DESC * sizeof(struct de4x5_desc),
1313 DE4X5_TRBA);
1314
1315 /* Initialise the IRQ mask and Enable/Disable */
1316 lp->irq_mask = IMR_RIM | IMR_TIM | IMR_TUM | IMR_UNM;
1317 lp->irq_en = IMR_NIM | IMR_AIM;
1318
1319 /* Create a loopback packet frame for later media probing */
1320 create_packet(dev, lp->frame, sizeof(lp->frame));
1321
1322 /* Check if the RX overflow bug needs testing for */
1323 i = cfrv & 0x000000fe;
1324 if ((lp->chipset == DC21140) && (i == 0x20)) {
1325 lp->rx_ovf = 1;
1326 }
1327
1328 /* Initialise the SROM pointers if possible */
1329 if (lp->useSROM) {
1330 lp->state = INITIALISED;
1331 if (srom_infoleaf_info(dev)) {
1332 return -ENXIO;
1333 }
1334 srom_init(dev);
1335 }
1336
1337 lp->state = CLOSED;
1338
1339 /*
1340 ** Check for an MII interface
1341 */
1342 if ((lp->chipset != DC21040) && (lp->chipset != DC21041)) {
1343 mii_get_phy(dev);
1344 }
1345
1346 #ifndef __sparc_v9__
1347 printk(" and requires IRQ%d (provided by %s).\n", dev->irq,
1348 #else
1349 printk(" and requires IRQ%x (provided by %s).\n", dev->irq,
1350 #endif
1351 ((lp->bus == PCI) ? "PCI BIOS" : "EISA CNFG"));
1352 }
1353
1354 if (de4x5_debug & DEBUG_VERSION) {
1355 printk(version);
1356 }
1357
1358 /* The DE4X5-specific entries in the device structure. */
1359 dev->open = &de4x5_open;
1360 dev->hard_start_xmit = &de4x5_queue_pkt;
1361 dev->stop = &de4x5_close;
1362 dev->get_stats = &de4x5_get_stats;
1363 dev->set_multicast_list = &set_multicast_list;
1364 dev->do_ioctl = &de4x5_ioctl;
1365
1366 dev->mem_start = 0;
1367
1368 /* Fill in the generic fields of the device structure. */
1369 ether_setup(dev);
1370
1371 /* Let the adapter sleep to save power */
1372 yawn(dev, SLEEP);
1373
1374 return status;
1375 }
1376
1377
1378 static int
de4x5_open(struct net_device * dev)1379 de4x5_open(struct net_device *dev)
1380 {
1381 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
1382 u_long iobase = dev->base_addr;
1383 int i, status = 0;
1384 s32 omr;
1385
1386 /* Allocate the RX buffers */
1387 for (i=0; i<lp->rxRingSize; i++) {
1388 if (de4x5_alloc_rx_buff(dev, i, 0) == NULL) {
1389 de4x5_free_rx_buffs(dev);
1390 return -EAGAIN;
1391 }
1392 }
1393
1394 /*
1395 ** Wake up the adapter
1396 */
1397 yawn(dev, WAKEUP);
1398
1399 /*
1400 ** Re-initialize the DE4X5...
1401 */
1402 status = de4x5_init(dev);
1403 lp->lock = (spinlock_t) SPIN_LOCK_UNLOCKED;
1404 lp->state = OPEN;
1405 de4x5_dbg_open(dev);
1406
1407 if (request_irq(dev->irq, (void *)de4x5_interrupt, SA_SHIRQ,
1408 lp->adapter_name, dev)) {
1409 printk("de4x5_open(): Requested IRQ%d is busy - attemping FAST/SHARE...", dev->irq);
1410 if (request_irq(dev->irq, de4x5_interrupt, SA_INTERRUPT | SA_SHIRQ,
1411 lp->adapter_name, dev)) {
1412 printk("\n Cannot get IRQ- reconfigure your hardware.\n");
1413 disable_ast(dev);
1414 de4x5_free_rx_buffs(dev);
1415 de4x5_free_tx_buffs(dev);
1416 yawn(dev, SLEEP);
1417 lp->state = CLOSED;
1418 return -EAGAIN;
1419 } else {
1420 printk("\n Succeeded, but you should reconfigure your hardware to avoid this.\n");
1421 printk("WARNING: there may be IRQ related problems in heavily loaded systems.\n");
1422 }
1423 }
1424
1425 lp->interrupt = UNMASK_INTERRUPTS;
1426 dev->trans_start = jiffies;
1427
1428 START_DE4X5;
1429
1430 de4x5_setup_intr(dev);
1431
1432 if (de4x5_debug & DEBUG_OPEN) {
1433 printk("\tsts: 0x%08x\n", inl(DE4X5_STS));
1434 printk("\tbmr: 0x%08x\n", inl(DE4X5_BMR));
1435 printk("\timr: 0x%08x\n", inl(DE4X5_IMR));
1436 printk("\tomr: 0x%08x\n", inl(DE4X5_OMR));
1437 printk("\tsisr: 0x%08x\n", inl(DE4X5_SISR));
1438 printk("\tsicr: 0x%08x\n", inl(DE4X5_SICR));
1439 printk("\tstrr: 0x%08x\n", inl(DE4X5_STRR));
1440 printk("\tsigr: 0x%08x\n", inl(DE4X5_SIGR));
1441 }
1442
1443 MOD_INC_USE_COUNT;
1444
1445 return status;
1446 }
1447
1448 /*
1449 ** Initialize the DE4X5 operating conditions. NB: a chip problem with the
1450 ** DC21140 requires using perfect filtering mode for that chip. Since I can't
1451 ** see why I'd want > 14 multicast addresses, I have changed all chips to use
1452 ** the perfect filtering mode. Keep the DMA burst length at 8: there seems
1453 ** to be data corruption problems if it is larger (UDP errors seen from a
1454 ** ttcp source).
1455 */
1456 static int
de4x5_init(struct net_device * dev)1457 de4x5_init(struct net_device *dev)
1458 {
1459 /* Lock out other processes whilst setting up the hardware */
1460 netif_stop_queue(dev);
1461
1462 de4x5_sw_reset(dev);
1463
1464 /* Autoconfigure the connected port */
1465 autoconf_media(dev);
1466
1467 return 0;
1468 }
1469
1470 static int
de4x5_sw_reset(struct net_device * dev)1471 de4x5_sw_reset(struct net_device *dev)
1472 {
1473 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
1474 u_long iobase = dev->base_addr;
1475 int i, j, status = 0;
1476 s32 bmr, omr;
1477
1478 /* Select the MII or SRL port now and RESET the MAC */
1479 if (!lp->useSROM) {
1480 if (lp->phy[lp->active].id != 0) {
1481 lp->infoblock_csr6 = OMR_SDP | OMR_PS | OMR_HBD;
1482 } else {
1483 lp->infoblock_csr6 = OMR_SDP | OMR_TTM;
1484 }
1485 de4x5_switch_mac_port(dev);
1486 }
1487
1488 /*
1489 ** Set the programmable burst length to 8 longwords for all the DC21140
1490 ** Fasternet chips and 4 longwords for all others: DMA errors result
1491 ** without these values. Cache align 16 long.
1492 */
1493 bmr = (lp->chipset==DC21140 ? PBL_8 : PBL_4) | DESC_SKIP_LEN | DE4X5_CACHE_ALIGN;
1494 bmr |= ((lp->chipset & ~0x00ff)==DC2114x ? BMR_RML : 0);
1495 outl(bmr, DE4X5_BMR);
1496
1497 omr = inl(DE4X5_OMR) & ~OMR_PR; /* Turn off promiscuous mode */
1498 if (lp->chipset == DC21140) {
1499 omr |= (OMR_SDP | OMR_SB);
1500 }
1501 lp->setup_f = PERFECT;
1502 outl(lp->dma_rings, DE4X5_RRBA);
1503 outl(lp->dma_rings + NUM_RX_DESC * sizeof(struct de4x5_desc),
1504 DE4X5_TRBA);
1505
1506 lp->rx_new = lp->rx_old = 0;
1507 lp->tx_new = lp->tx_old = 0;
1508
1509 for (i = 0; i < lp->rxRingSize; i++) {
1510 lp->rx_ring[i].status = cpu_to_le32(R_OWN);
1511 }
1512
1513 for (i = 0; i < lp->txRingSize; i++) {
1514 lp->tx_ring[i].status = cpu_to_le32(0);
1515 }
1516
1517 barrier();
1518
1519 /* Build the setup frame depending on filtering mode */
1520 SetMulticastFilter(dev);
1521
1522 load_packet(dev, lp->setup_frame, PERFECT_F|TD_SET|SETUP_FRAME_LEN, (struct sk_buff *)1);
1523 outl(omr|OMR_ST, DE4X5_OMR);
1524
1525 /* Poll for setup frame completion (adapter interrupts are disabled now) */
1526 sti(); /* Ensure timer interrupts */
1527 for (j=0, i=0;(i<500) && (j==0);i++) { /* Upto 500ms delay */
1528 mdelay(1);
1529 if ((s32)le32_to_cpu(lp->tx_ring[lp->tx_new].status) >= 0) j=1;
1530 }
1531 outl(omr, DE4X5_OMR); /* Stop everything! */
1532
1533 if (j == 0) {
1534 printk("%s: Setup frame timed out, status %08x\n", dev->name,
1535 inl(DE4X5_STS));
1536 status = -EIO;
1537 }
1538
1539 lp->tx_new = (++lp->tx_new) % lp->txRingSize;
1540 lp->tx_old = lp->tx_new;
1541
1542 return status;
1543 }
1544
1545 /*
1546 ** Writes a socket buffer address to the next available transmit descriptor.
1547 */
1548 static int
de4x5_queue_pkt(struct sk_buff * skb,struct net_device * dev)1549 de4x5_queue_pkt(struct sk_buff *skb, struct net_device *dev)
1550 {
1551 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
1552 u_long iobase = dev->base_addr;
1553 int status = 0;
1554 u_long flags = 0;
1555
1556 netif_stop_queue(dev);
1557 if (lp->tx_enable == NO) { /* Cannot send for now */
1558 return -1;
1559 }
1560
1561 /*
1562 ** Clean out the TX ring asynchronously to interrupts - sometimes the
1563 ** interrupts are lost by delayed descriptor status updates relative to
1564 ** the irq assertion, especially with a busy PCI bus.
1565 */
1566 spin_lock_irqsave(&lp->lock, flags);
1567 de4x5_tx(dev);
1568 spin_unlock_irqrestore(&lp->lock, flags);
1569
1570 /* Test if cache is already locked - requeue skb if so */
1571 if (test_and_set_bit(0, (void *)&lp->cache.lock) && !lp->interrupt)
1572 return -1;
1573
1574 /* Transmit descriptor ring full or stale skb */
1575 if (netif_queue_stopped(dev) || (u_long) lp->tx_skb[lp->tx_new] > 1) {
1576 if (lp->interrupt) {
1577 de4x5_putb_cache(dev, skb); /* Requeue the buffer */
1578 } else {
1579 de4x5_put_cache(dev, skb);
1580 }
1581 if (de4x5_debug & DEBUG_TX) {
1582 printk("%s: transmit busy, lost media or stale skb found:\n STS:%08x\n tbusy:%d\n IMR:%08x\n OMR:%08x\n Stale skb: %s\n",dev->name, inl(DE4X5_STS), netif_queue_stopped(dev), inl(DE4X5_IMR), inl(DE4X5_OMR), ((u_long) lp->tx_skb[lp->tx_new] > 1) ? "YES" : "NO");
1583 }
1584 } else if (skb->len > 0) {
1585 /* If we already have stuff queued locally, use that first */
1586 if (lp->cache.skb && !lp->interrupt) {
1587 de4x5_put_cache(dev, skb);
1588 skb = de4x5_get_cache(dev);
1589 }
1590
1591 while (skb && !netif_queue_stopped(dev) &&
1592 (u_long) lp->tx_skb[lp->tx_new] <= 1) {
1593 spin_lock_irqsave(&lp->lock, flags);
1594 netif_stop_queue(dev);
1595 load_packet(dev, skb->data, TD_IC | TD_LS | TD_FS | skb->len, skb);
1596 lp->stats.tx_bytes += skb->len;
1597 outl(POLL_DEMAND, DE4X5_TPD);/* Start the TX */
1598
1599 lp->tx_new = (++lp->tx_new) % lp->txRingSize;
1600 dev->trans_start = jiffies;
1601
1602 if (TX_BUFFS_AVAIL) {
1603 netif_start_queue(dev); /* Another pkt may be queued */
1604 }
1605 skb = de4x5_get_cache(dev);
1606 spin_unlock_irqrestore(&lp->lock, flags);
1607 }
1608 if (skb) de4x5_putb_cache(dev, skb);
1609 }
1610
1611 lp->cache.lock = 0;
1612
1613 return status;
1614 }
1615
1616 /*
1617 ** The DE4X5 interrupt handler.
1618 **
1619 ** I/O Read/Writes through intermediate PCI bridges are never 'posted',
1620 ** so that the asserted interrupt always has some real data to work with -
1621 ** if these I/O accesses are ever changed to memory accesses, ensure the
1622 ** STS write is read immediately to complete the transaction if the adapter
1623 ** is not on bus 0. Lost interrupts can still occur when the PCI bus load
1624 ** is high and descriptor status bits cannot be set before the associated
1625 ** interrupt is asserted and this routine entered.
1626 */
1627 static void
de4x5_interrupt(int irq,void * dev_id,struct pt_regs * regs)1628 de4x5_interrupt(int irq, void *dev_id, struct pt_regs *regs)
1629 {
1630 struct net_device *dev = (struct net_device *)dev_id;
1631 struct de4x5_private *lp;
1632 s32 imr, omr, sts, limit;
1633 u_long iobase;
1634
1635 if (dev == NULL) {
1636 printk ("de4x5_interrupt(): irq %d for unknown device.\n", irq);
1637 return;
1638 }
1639 lp = (struct de4x5_private *)dev->priv;
1640 spin_lock(&lp->lock);
1641 iobase = dev->base_addr;
1642
1643 DISABLE_IRQs; /* Ensure non re-entrancy */
1644
1645 if (test_and_set_bit(MASK_INTERRUPTS, (void*) &lp->interrupt))
1646 printk("%s: Re-entering the interrupt handler.\n", dev->name);
1647
1648 synchronize_irq();
1649
1650 for (limit=0; limit<8; limit++) {
1651 sts = inl(DE4X5_STS); /* Read IRQ status */
1652 outl(sts, DE4X5_STS); /* Reset the board interrupts */
1653
1654 if (!(sts & lp->irq_mask)) break;/* All done */
1655
1656 if (sts & (STS_RI | STS_RU)) /* Rx interrupt (packet[s] arrived) */
1657 de4x5_rx(dev);
1658
1659 if (sts & (STS_TI | STS_TU)) /* Tx interrupt (packet sent) */
1660 de4x5_tx(dev);
1661
1662 if (sts & STS_LNF) { /* TP Link has failed */
1663 lp->irq_mask &= ~IMR_LFM;
1664 }
1665
1666 if (sts & STS_UNF) { /* Transmit underrun */
1667 de4x5_txur(dev);
1668 }
1669
1670 if (sts & STS_SE) { /* Bus Error */
1671 STOP_DE4X5;
1672 printk("%s: Fatal bus error occurred, sts=%#8x, device stopped.\n",
1673 dev->name, sts);
1674 spin_unlock(&lp->lock);
1675 return;
1676 }
1677 }
1678
1679 /* Load the TX ring with any locally stored packets */
1680 if (!test_and_set_bit(0, (void *)&lp->cache.lock)) {
1681 while (lp->cache.skb && !netif_queue_stopped(dev) && lp->tx_enable) {
1682 de4x5_queue_pkt(de4x5_get_cache(dev), dev);
1683 }
1684 lp->cache.lock = 0;
1685 }
1686
1687 lp->interrupt = UNMASK_INTERRUPTS;
1688 ENABLE_IRQs;
1689 spin_unlock(&lp->lock);
1690
1691 return;
1692 }
1693
1694 static int
de4x5_rx(struct net_device * dev)1695 de4x5_rx(struct net_device *dev)
1696 {
1697 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
1698 u_long iobase = dev->base_addr;
1699 int entry;
1700 s32 status;
1701
1702 for (entry=lp->rx_new; (s32)le32_to_cpu(lp->rx_ring[entry].status)>=0;
1703 entry=lp->rx_new) {
1704 status = (s32)le32_to_cpu(lp->rx_ring[entry].status);
1705
1706 if (lp->rx_ovf) {
1707 if (inl(DE4X5_MFC) & MFC_FOCM) {
1708 de4x5_rx_ovfc(dev);
1709 break;
1710 }
1711 }
1712
1713 if (status & RD_FS) { /* Remember the start of frame */
1714 lp->rx_old = entry;
1715 }
1716
1717 if (status & RD_LS) { /* Valid frame status */
1718 if (lp->tx_enable) lp->linkOK++;
1719 if (status & RD_ES) { /* There was an error. */
1720 lp->stats.rx_errors++; /* Update the error stats. */
1721 if (status & (RD_RF | RD_TL)) lp->stats.rx_frame_errors++;
1722 if (status & RD_CE) lp->stats.rx_crc_errors++;
1723 if (status & RD_OF) lp->stats.rx_fifo_errors++;
1724 if (status & RD_TL) lp->stats.rx_length_errors++;
1725 if (status & RD_RF) lp->pktStats.rx_runt_frames++;
1726 if (status & RD_CS) lp->pktStats.rx_collision++;
1727 if (status & RD_DB) lp->pktStats.rx_dribble++;
1728 if (status & RD_OF) lp->pktStats.rx_overflow++;
1729 } else { /* A valid frame received */
1730 struct sk_buff *skb;
1731 short pkt_len = (short)(le32_to_cpu(lp->rx_ring[entry].status)
1732 >> 16) - 4;
1733
1734 if ((skb = de4x5_alloc_rx_buff(dev, entry, pkt_len)) == NULL) {
1735 printk("%s: Insufficient memory; nuking packet.\n",
1736 dev->name);
1737 lp->stats.rx_dropped++;
1738 } else {
1739 de4x5_dbg_rx(skb, pkt_len);
1740
1741 /* Push up the protocol stack */
1742 skb->protocol=eth_type_trans(skb,dev);
1743 de4x5_local_stats(dev, skb->data, pkt_len);
1744 netif_rx(skb);
1745
1746 /* Update stats */
1747 dev->last_rx = jiffies;
1748 lp->stats.rx_packets++;
1749 lp->stats.rx_bytes += pkt_len;
1750 }
1751 }
1752
1753 /* Change buffer ownership for this frame, back to the adapter */
1754 for (;lp->rx_old!=entry;lp->rx_old=(++lp->rx_old)%lp->rxRingSize) {
1755 lp->rx_ring[lp->rx_old].status = cpu_to_le32(R_OWN);
1756 barrier();
1757 }
1758 lp->rx_ring[entry].status = cpu_to_le32(R_OWN);
1759 barrier();
1760 }
1761
1762 /*
1763 ** Update entry information
1764 */
1765 lp->rx_new = (++lp->rx_new) % lp->rxRingSize;
1766 }
1767
1768 return 0;
1769 }
1770
1771 static inline void
de4x5_free_tx_buff(struct de4x5_private * lp,int entry)1772 de4x5_free_tx_buff(struct de4x5_private *lp, int entry)
1773 {
1774 pci_unmap_single(lp->pdev, le32_to_cpu(lp->tx_ring[entry].buf),
1775 le32_to_cpu(lp->tx_ring[entry].des1) & TD_TBS1,
1776 PCI_DMA_TODEVICE);
1777 if ((u_long) lp->tx_skb[entry] > 1)
1778 dev_kfree_skb_irq(lp->tx_skb[entry]);
1779 lp->tx_skb[entry] = NULL;
1780 }
1781
1782 /*
1783 ** Buffer sent - check for TX buffer errors.
1784 */
1785 static int
de4x5_tx(struct net_device * dev)1786 de4x5_tx(struct net_device *dev)
1787 {
1788 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
1789 u_long iobase = dev->base_addr;
1790 int entry;
1791 s32 status;
1792
1793 for (entry = lp->tx_old; entry != lp->tx_new; entry = lp->tx_old) {
1794 status = (s32)le32_to_cpu(lp->tx_ring[entry].status);
1795 if (status < 0) { /* Buffer not sent yet */
1796 break;
1797 } else if (status != 0x7fffffff) { /* Not setup frame */
1798 if (status & TD_ES) { /* An error happened */
1799 lp->stats.tx_errors++;
1800 if (status & TD_NC) lp->stats.tx_carrier_errors++;
1801 if (status & TD_LC) lp->stats.tx_window_errors++;
1802 if (status & TD_UF) lp->stats.tx_fifo_errors++;
1803 if (status & TD_EC) lp->pktStats.excessive_collisions++;
1804 if (status & TD_DE) lp->stats.tx_aborted_errors++;
1805
1806 if (TX_PKT_PENDING) {
1807 outl(POLL_DEMAND, DE4X5_TPD);/* Restart a stalled TX */
1808 }
1809 } else { /* Packet sent */
1810 lp->stats.tx_packets++;
1811 if (lp->tx_enable) lp->linkOK++;
1812 }
1813 /* Update the collision counter */
1814 lp->stats.collisions += ((status & TD_EC) ? 16 :
1815 ((status & TD_CC) >> 3));
1816
1817 /* Free the buffer. */
1818 if (lp->tx_skb[entry] != NULL)
1819 de4x5_free_tx_buff(lp, entry);
1820 }
1821
1822 /* Update all the pointers */
1823 lp->tx_old = (++lp->tx_old) % lp->txRingSize;
1824 }
1825
1826 /* Any resources available? */
1827 if (TX_BUFFS_AVAIL && netif_queue_stopped(dev)) {
1828 if (lp->interrupt)
1829 netif_wake_queue(dev);
1830 else
1831 netif_start_queue(dev);
1832 }
1833
1834 return 0;
1835 }
1836
1837 static int
de4x5_ast(struct net_device * dev)1838 de4x5_ast(struct net_device *dev)
1839 {
1840 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
1841 int next_tick = DE4X5_AUTOSENSE_MS;
1842
1843 disable_ast(dev);
1844
1845 if (lp->useSROM) {
1846 next_tick = srom_autoconf(dev);
1847 } else if (lp->chipset == DC21140) {
1848 next_tick = dc21140m_autoconf(dev);
1849 } else if (lp->chipset == DC21041) {
1850 next_tick = dc21041_autoconf(dev);
1851 } else if (lp->chipset == DC21040) {
1852 next_tick = dc21040_autoconf(dev);
1853 }
1854 lp->linkOK = 0;
1855 enable_ast(dev, next_tick);
1856
1857 return 0;
1858 }
1859
1860 static int
de4x5_txur(struct net_device * dev)1861 de4x5_txur(struct net_device *dev)
1862 {
1863 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
1864 u_long iobase = dev->base_addr;
1865 int omr;
1866
1867 omr = inl(DE4X5_OMR);
1868 if (!(omr & OMR_SF) || (lp->chipset==DC21041) || (lp->chipset==DC21040)) {
1869 omr &= ~(OMR_ST|OMR_SR);
1870 outl(omr, DE4X5_OMR);
1871 while (inl(DE4X5_STS) & STS_TS);
1872 if ((omr & OMR_TR) < OMR_TR) {
1873 omr += 0x4000;
1874 } else {
1875 omr |= OMR_SF;
1876 }
1877 outl(omr | OMR_ST | OMR_SR, DE4X5_OMR);
1878 }
1879
1880 return 0;
1881 }
1882
1883 static int
de4x5_rx_ovfc(struct net_device * dev)1884 de4x5_rx_ovfc(struct net_device *dev)
1885 {
1886 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
1887 u_long iobase = dev->base_addr;
1888 int omr;
1889
1890 omr = inl(DE4X5_OMR);
1891 outl(omr & ~OMR_SR, DE4X5_OMR);
1892 while (inl(DE4X5_STS) & STS_RS);
1893
1894 for (; (s32)le32_to_cpu(lp->rx_ring[lp->rx_new].status)>=0;) {
1895 lp->rx_ring[lp->rx_new].status = cpu_to_le32(R_OWN);
1896 lp->rx_new = (++lp->rx_new % lp->rxRingSize);
1897 }
1898
1899 outl(omr, DE4X5_OMR);
1900
1901 return 0;
1902 }
1903
1904 static int
de4x5_close(struct net_device * dev)1905 de4x5_close(struct net_device *dev)
1906 {
1907 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
1908 u_long iobase = dev->base_addr;
1909 s32 imr, omr;
1910
1911 disable_ast(dev);
1912
1913 netif_stop_queue(dev);
1914
1915 if (de4x5_debug & DEBUG_CLOSE) {
1916 printk("%s: Shutting down ethercard, status was %8.8x.\n",
1917 dev->name, inl(DE4X5_STS));
1918 }
1919
1920 /*
1921 ** We stop the DE4X5 here... mask interrupts and stop TX & RX
1922 */
1923 DISABLE_IRQs;
1924 STOP_DE4X5;
1925
1926 /* Free the associated irq */
1927 free_irq(dev->irq, dev);
1928 lp->state = CLOSED;
1929
1930 /* Free any socket buffers */
1931 de4x5_free_rx_buffs(dev);
1932 de4x5_free_tx_buffs(dev);
1933
1934 MOD_DEC_USE_COUNT;
1935
1936 /* Put the adapter to sleep to save power */
1937 yawn(dev, SLEEP);
1938
1939 return 0;
1940 }
1941
1942 static struct net_device_stats *
de4x5_get_stats(struct net_device * dev)1943 de4x5_get_stats(struct net_device *dev)
1944 {
1945 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
1946 u_long iobase = dev->base_addr;
1947
1948 lp->stats.rx_missed_errors = (int)(inl(DE4X5_MFC) & (MFC_OVFL | MFC_CNTR));
1949
1950 return &lp->stats;
1951 }
1952
1953 static void
de4x5_local_stats(struct net_device * dev,char * buf,int pkt_len)1954 de4x5_local_stats(struct net_device *dev, char *buf, int pkt_len)
1955 {
1956 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
1957 int i;
1958
1959 for (i=1; i<DE4X5_PKT_STAT_SZ-1; i++) {
1960 if (pkt_len < (i*DE4X5_PKT_BIN_SZ)) {
1961 lp->pktStats.bins[i]++;
1962 i = DE4X5_PKT_STAT_SZ;
1963 }
1964 }
1965 if (buf[0] & 0x01) { /* Multicast/Broadcast */
1966 if ((*(s32 *)&buf[0] == -1) && (*(s16 *)&buf[4] == -1)) {
1967 lp->pktStats.broadcast++;
1968 } else {
1969 lp->pktStats.multicast++;
1970 }
1971 } else if ((*(s32 *)&buf[0] == *(s32 *)&dev->dev_addr[0]) &&
1972 (*(s16 *)&buf[4] == *(s16 *)&dev->dev_addr[4])) {
1973 lp->pktStats.unicast++;
1974 }
1975
1976 lp->pktStats.bins[0]++; /* Duplicates stats.rx_packets */
1977 if (lp->pktStats.bins[0] == 0) { /* Reset counters */
1978 memset((char *)&lp->pktStats, 0, sizeof(lp->pktStats));
1979 }
1980
1981 return;
1982 }
1983
1984 /*
1985 ** Removes the TD_IC flag from previous descriptor to improve TX performance.
1986 ** If the flag is changed on a descriptor that is being read by the hardware,
1987 ** I assume PCI transaction ordering will mean you are either successful or
1988 ** just miss asserting the change to the hardware. Anyway you're messing with
1989 ** a descriptor you don't own, but this shouldn't kill the chip provided
1990 ** the descriptor register is read only to the hardware.
1991 */
1992 static void
load_packet(struct net_device * dev,char * buf,u32 flags,struct sk_buff * skb)1993 load_packet(struct net_device *dev, char *buf, u32 flags, struct sk_buff *skb)
1994 {
1995 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
1996 int entry = (lp->tx_new ? lp->tx_new-1 : lp->txRingSize-1);
1997 dma_addr_t buf_dma = pci_map_single(lp->pdev, buf, flags & TD_TBS1, PCI_DMA_TODEVICE);
1998
1999 lp->tx_ring[lp->tx_new].buf = cpu_to_le32(buf_dma);
2000 lp->tx_ring[lp->tx_new].des1 &= cpu_to_le32(TD_TER);
2001 lp->tx_ring[lp->tx_new].des1 |= cpu_to_le32(flags);
2002 lp->tx_skb[lp->tx_new] = skb;
2003 lp->tx_ring[entry].des1 &= cpu_to_le32(~TD_IC);
2004 barrier();
2005
2006 lp->tx_ring[lp->tx_new].status = cpu_to_le32(T_OWN);
2007 barrier();
2008 }
2009
2010 /*
2011 ** Set or clear the multicast filter for this adaptor.
2012 */
2013 static void
set_multicast_list(struct net_device * dev)2014 set_multicast_list(struct net_device *dev)
2015 {
2016 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
2017 u_long iobase = dev->base_addr;
2018
2019 /* First, double check that the adapter is open */
2020 if (lp->state == OPEN) {
2021 if (dev->flags & IFF_PROMISC) { /* set promiscuous mode */
2022 u32 omr;
2023 omr = inl(DE4X5_OMR);
2024 omr |= OMR_PR;
2025 outl(omr, DE4X5_OMR);
2026 } else {
2027 SetMulticastFilter(dev);
2028 load_packet(dev, lp->setup_frame, TD_IC | PERFECT_F | TD_SET |
2029 SETUP_FRAME_LEN, (struct sk_buff *)1);
2030
2031 lp->tx_new = (++lp->tx_new) % lp->txRingSize;
2032 outl(POLL_DEMAND, DE4X5_TPD); /* Start the TX */
2033 dev->trans_start = jiffies;
2034 }
2035 }
2036
2037 return;
2038 }
2039
2040 /*
2041 ** Calculate the hash code and update the logical address filter
2042 ** from a list of ethernet multicast addresses.
2043 ** Little endian crc one liner from Matt Thomas, DEC.
2044 */
2045 static void
SetMulticastFilter(struct net_device * dev)2046 SetMulticastFilter(struct net_device *dev)
2047 {
2048 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
2049 struct dev_mc_list *dmi=dev->mc_list;
2050 u_long iobase = dev->base_addr;
2051 int i, j, bit, byte;
2052 u16 hashcode;
2053 u32 omr, crc;
2054 char *pa;
2055 unsigned char *addrs;
2056
2057 omr = inl(DE4X5_OMR);
2058 omr &= ~(OMR_PR | OMR_PM);
2059 pa = build_setup_frame(dev, ALL); /* Build the basic frame */
2060
2061 if ((dev->flags & IFF_ALLMULTI) || (dev->mc_count > 14)) {
2062 omr |= OMR_PM; /* Pass all multicasts */
2063 } else if (lp->setup_f == HASH_PERF) { /* Hash Filtering */
2064 for (i=0;i<dev->mc_count;i++) { /* for each address in the list */
2065 addrs=dmi->dmi_addr;
2066 dmi=dmi->next;
2067 if ((*addrs & 0x01) == 1) { /* multicast address? */
2068 crc = ether_crc_le(ETH_ALEN, addrs);
2069 hashcode = crc & HASH_BITS; /* hashcode is 9 LSb of CRC */
2070
2071 byte = hashcode >> 3; /* bit[3-8] -> byte in filter */
2072 bit = 1 << (hashcode & 0x07);/* bit[0-2] -> bit in byte */
2073
2074 byte <<= 1; /* calc offset into setup frame */
2075 if (byte & 0x02) {
2076 byte -= 1;
2077 }
2078 lp->setup_frame[byte] |= bit;
2079 }
2080 }
2081 } else { /* Perfect filtering */
2082 for (j=0; j<dev->mc_count; j++) {
2083 addrs=dmi->dmi_addr;
2084 dmi=dmi->next;
2085 for (i=0; i<ETH_ALEN; i++) {
2086 *(pa + (i&1)) = *addrs++;
2087 if (i & 0x01) pa += 4;
2088 }
2089 }
2090 }
2091 outl(omr, DE4X5_OMR);
2092
2093 return;
2094 }
2095
2096 #ifdef CONFIG_EISA
2097 /*
2098 ** EISA bus I/O device probe. Probe from slot 1 since slot 0 is usually
2099 ** the motherboard. Upto 15 EISA devices are supported.
2100 */
2101 static void __init
eisa_probe(struct net_device * dev,u_long ioaddr)2102 eisa_probe(struct net_device *dev, u_long ioaddr)
2103 {
2104 int i, maxSlots, status, device;
2105 u_char irq;
2106 u_short vendor;
2107 u32 cfid;
2108 u_long iobase;
2109 struct de4x5_bus_type *lp = &bus;
2110 char name[DE4X5_STRLEN];
2111
2112 if (lastEISA == MAX_EISA_SLOTS) return;/* No more EISA devices to search */
2113
2114 lp->bus = EISA;
2115
2116 if (ioaddr == 0) { /* Autoprobing */
2117 iobase = EISA_SLOT_INC; /* Get the first slot address */
2118 i = 1;
2119 maxSlots = MAX_EISA_SLOTS;
2120 } else { /* Probe a specific location */
2121 iobase = ioaddr;
2122 i = (ioaddr >> 12);
2123 maxSlots = i + 1;
2124 }
2125
2126 for (status = -ENODEV; (i<maxSlots) && (dev!=NULL); i++, iobase+=EISA_SLOT_INC) {
2127 if (check_region(iobase, DE4X5_EISA_TOTAL_SIZE)) continue;
2128 if (!EISA_signature(name, EISA_ID)) continue;
2129
2130 cfid = (u32) inl(PCI_CFID);
2131 cfrv = (u_short) inl(PCI_CFRV);
2132 device = (cfid >> 8) & 0x00ffff00;
2133 vendor = (u_short) cfid;
2134
2135 /* Read the EISA Configuration Registers */
2136 irq = inb(EISA_REG0);
2137 irq = de4x5_irq[(irq >> 1) & 0x03];
2138
2139 if (is_DC2114x) {
2140 device = ((cfrv & CFRV_RN) < DC2114x_BRK ? DC21142 : DC21143);
2141 }
2142 lp->chipset = device;
2143
2144 /* Write the PCI Configuration Registers */
2145 outl(PCI_COMMAND_IO | PCI_COMMAND_MASTER, PCI_CFCS);
2146 outl(0x00006000, PCI_CFLT);
2147 outl(iobase, PCI_CBIO);
2148
2149 DevicePresent(EISA_APROM);
2150
2151 dev->irq = irq;
2152 if ((status = de4x5_hw_init(dev, iobase, NULL)) == 0) {
2153 num_de4x5s++;
2154 if (loading_module) link_modules(lastModule, dev);
2155 lastEISA = i;
2156 return;
2157 }
2158 }
2159
2160 if (ioaddr == 0) lastEISA = i;
2161
2162 return;
2163 }
2164 #endif /* !(__sparc_v9__) && !(__powerpc__) && !defined(__alpha__) */
2165
2166 /*
2167 ** PCI bus I/O device probe
2168 ** NB: PCI I/O accesses and Bus Mastering are enabled by the PCI BIOS, not
2169 ** the driver. Some PCI BIOS's, pre V2.1, need the slot + features to be
2170 ** enabled by the user first in the set up utility. Hence we just check for
2171 ** enabled features and silently ignore the card if they're not.
2172 **
2173 ** STOP PRESS: Some BIOS's __require__ the driver to enable the bus mastering
2174 ** bit. Here, check for I/O accesses and then set BM. If you put the card in
2175 ** a non BM slot, you're on your own (and complain to the PC vendor that your
2176 ** PC doesn't conform to the PCI standard)!
2177 **
2178 ** This function is only compatible with the *latest* 2.1.x kernels. For 2.0.x
2179 ** kernels use the V0.535[n] drivers.
2180 */
2181 #define PCI_LAST_DEV 32
2182
2183 static void __init
pci_probe(struct net_device * dev,u_long ioaddr)2184 pci_probe(struct net_device *dev, u_long ioaddr)
2185 {
2186 u_char pb, pbus, dev_num, dnum, timer;
2187 u_short vendor, index, status;
2188 u_int irq = 0, device, class = DE4X5_CLASS_CODE;
2189 u_long iobase = 0; /* Clear upper 32 bits in Alphas */
2190 struct de4x5_bus_type *lp = &bus;
2191
2192 if (lastPCI == NO_MORE_PCI) return;
2193
2194 if (!pcibios_present()) {
2195 lastPCI = NO_MORE_PCI;
2196 return; /* No PCI bus in this machine! */
2197 }
2198
2199 lp->bus = PCI;
2200 lp->bus_num = 0;
2201
2202 if ((ioaddr < 0x1000) && loading_module) {
2203 pbus = (u_short)(ioaddr >> 8);
2204 dnum = (u_short)(ioaddr & 0xff);
2205 } else {
2206 pbus = 0;
2207 dnum = 0;
2208 }
2209
2210 for (index=lastPCI+1;(pdev = pci_find_class(class, pdev))!=NULL;index++) {
2211 dev_num = PCI_SLOT(pdev->devfn);
2212 pb = pdev->bus->number;
2213 if ((pbus || dnum) && ((pbus != pb) || (dnum != dev_num))) continue;
2214
2215 vendor = pdev->vendor;
2216 device = pdev->device << 8;
2217 if (!(is_DC21040 || is_DC21041 || is_DC21140 || is_DC2114x)) continue;
2218
2219 /* Search for an SROM on this bus */
2220 if (lp->bus_num != pb) {
2221 lp->bus_num = pb;
2222 srom_search(pdev);
2223 }
2224
2225 /* Get the chip configuration revision register */
2226 pcibios_read_config_dword(pb, pdev->devfn, PCI_REVISION_ID, &cfrv);
2227
2228 /* Set the device number information */
2229 lp->device = dev_num;
2230 lp->bus_num = pb;
2231
2232 /* Set the chipset information */
2233 if (is_DC2114x) {
2234 device = ((cfrv & CFRV_RN) < DC2114x_BRK ? DC21142 : DC21143);
2235 }
2236 lp->chipset = device;
2237
2238 /* Get the board I/O address (64 bits on sparc64) */
2239 iobase = pci_resource_start(pdev, 0);
2240
2241 /* Fetch the IRQ to be used */
2242 irq = pdev->irq;
2243 if ((irq == 0) || (irq == 0xff) || ((int)irq == -1)) continue;
2244
2245 /* Check if I/O accesses and Bus Mastering are enabled */
2246 pcibios_read_config_word(pb, pdev->devfn, PCI_COMMAND, &status);
2247 #ifdef __powerpc__
2248 if (!(status & PCI_COMMAND_IO)) {
2249 status |= PCI_COMMAND_IO;
2250 pcibios_write_config_word(pb, pdev->devfn, PCI_COMMAND, status);
2251 pcibios_read_config_word(pb, pdev->devfn, PCI_COMMAND, &status);
2252 }
2253 #endif /* __powerpc__ */
2254 if (!(status & PCI_COMMAND_IO)) continue;
2255
2256 if (!(status & PCI_COMMAND_MASTER)) {
2257 status |= PCI_COMMAND_MASTER;
2258 pcibios_write_config_word(pb, pdev->devfn, PCI_COMMAND, status);
2259 pcibios_read_config_word(pb, pdev->devfn, PCI_COMMAND, &status);
2260 }
2261 if (!(status & PCI_COMMAND_MASTER)) continue;
2262
2263 /* Check the latency timer for values >= 0x60 */
2264 pcibios_read_config_byte(pb, pdev->devfn, PCI_LATENCY_TIMER, &timer);
2265 if (timer < 0x60) {
2266 pcibios_write_config_byte(pb, pdev->devfn, PCI_LATENCY_TIMER, 0x60);
2267 }
2268
2269 DevicePresent(DE4X5_APROM);
2270 if (check_region(iobase, DE4X5_PCI_TOTAL_SIZE) == 0) {
2271 dev->irq = irq;
2272 if ((status = de4x5_hw_init(dev, iobase, pdev)) == 0) {
2273 num_de4x5s++;
2274 lastPCI = index;
2275 if (loading_module) link_modules(lastModule, dev);
2276 return;
2277 }
2278 } else if (ioaddr != 0) {
2279 printk("%s: region already allocated at 0x%04lx.\n", dev->name,
2280 iobase);
2281 }
2282 }
2283
2284 lastPCI = NO_MORE_PCI;
2285
2286 return;
2287 }
2288
2289 /*
2290 ** This function searches the current bus (which is >0) for a DECchip with an
2291 ** SROM, so that in multiport cards that have one SROM shared between multiple
2292 ** DECchips, we can find the base SROM irrespective of the BIOS scan direction.
2293 ** For single port cards this is a time waster...
2294 */
2295 static void __init
srom_search(struct pci_dev * dev)2296 srom_search(struct pci_dev *dev)
2297 {
2298 u_char pb;
2299 u_short vendor, status;
2300 u_int irq = 0, device;
2301 u_long iobase = 0; /* Clear upper 32 bits in Alphas */
2302 int i, j;
2303 struct de4x5_bus_type *lp = &bus;
2304 struct list_head *walk = &dev->bus_list;
2305
2306 for (walk = walk->next; walk != &dev->bus_list; walk = walk->next) {
2307 struct pci_dev *this_dev = pci_dev_b(walk);
2308
2309 /* Skip the pci_bus list entry */
2310 if (list_entry(walk, struct pci_bus, devices) == dev->bus) continue;
2311
2312 vendor = this_dev->vendor;
2313 device = this_dev->device << 8;
2314 if (!(is_DC21040 || is_DC21041 || is_DC21140 || is_DC2114x)) continue;
2315
2316 /* Get the chip configuration revision register */
2317 pb = this_dev->bus->number;
2318 pcibios_read_config_dword(pb, this_dev->devfn, PCI_REVISION_ID, &cfrv);
2319
2320 /* Set the device number information */
2321 lp->device = PCI_SLOT(this_dev->devfn);
2322 lp->bus_num = pb;
2323
2324 /* Set the chipset information */
2325 if (is_DC2114x) {
2326 device = ((cfrv & CFRV_RN) < DC2114x_BRK ? DC21142 : DC21143);
2327 }
2328 lp->chipset = device;
2329
2330 /* Get the board I/O address (64 bits on sparc64) */
2331 iobase = pci_resource_start(this_dev, 0);
2332
2333 /* Fetch the IRQ to be used */
2334 irq = this_dev->irq;
2335 if ((irq == 0) || (irq == 0xff) || ((int)irq == -1)) continue;
2336
2337 /* Check if I/O accesses are enabled */
2338 pcibios_read_config_word(pb, this_dev->devfn, PCI_COMMAND, &status);
2339 if (!(status & PCI_COMMAND_IO)) continue;
2340
2341 /* Search for a valid SROM attached to this DECchip */
2342 DevicePresent(DE4X5_APROM);
2343 for (j=0, i=0; i<ETH_ALEN; i++) {
2344 j += (u_char) *((u_char *)&lp->srom + SROM_HWADD + i);
2345 }
2346 if ((j != 0) && (j != 0x5fa)) {
2347 last.chipset = device;
2348 last.bus = pb;
2349 last.irq = irq;
2350 for (i=0; i<ETH_ALEN; i++) {
2351 last.addr[i] = (u_char)*((u_char *)&lp->srom + SROM_HWADD + i);
2352 }
2353 return;
2354 }
2355 }
2356
2357 return;
2358 }
2359
2360 static void __init
link_modules(struct net_device * dev,struct net_device * tmp)2361 link_modules(struct net_device *dev, struct net_device *tmp)
2362 {
2363 struct net_device *p=dev;
2364
2365 if (p) {
2366 while (((struct de4x5_private *)(p->priv))->next_module) {
2367 p = ((struct de4x5_private *)(p->priv))->next_module;
2368 }
2369
2370 if (dev != tmp) {
2371 ((struct de4x5_private *)(p->priv))->next_module = tmp;
2372 } else {
2373 ((struct de4x5_private *)(p->priv))->next_module = NULL;
2374 }
2375 }
2376
2377 return;
2378 }
2379
2380 /*
2381 ** Auto configure the media here rather than setting the port at compile
2382 ** time. This routine is called by de4x5_init() and when a loss of media is
2383 ** detected (excessive collisions, loss of carrier, no carrier or link fail
2384 ** [TP] or no recent receive activity) to check whether the user has been
2385 ** sneaky and changed the port on us.
2386 */
2387 static int
autoconf_media(struct net_device * dev)2388 autoconf_media(struct net_device *dev)
2389 {
2390 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
2391 u_long iobase = dev->base_addr;
2392 int next_tick = DE4X5_AUTOSENSE_MS;
2393
2394 lp->linkOK = 0;
2395 lp->c_media = AUTO; /* Bogus last media */
2396 disable_ast(dev);
2397 inl(DE4X5_MFC); /* Zero the lost frames counter */
2398 lp->media = INIT;
2399 lp->tcount = 0;
2400
2401 if (lp->useSROM) {
2402 next_tick = srom_autoconf(dev);
2403 } else if (lp->chipset == DC21040) {
2404 next_tick = dc21040_autoconf(dev);
2405 } else if (lp->chipset == DC21041) {
2406 next_tick = dc21041_autoconf(dev);
2407 } else if (lp->chipset == DC21140) {
2408 next_tick = dc21140m_autoconf(dev);
2409 }
2410
2411 enable_ast(dev, next_tick);
2412
2413 return (lp->media);
2414 }
2415
2416 /*
2417 ** Autoconfigure the media when using the DC21040. AUI cannot be distinguished
2418 ** from BNC as the port has a jumper to set thick or thin wire. When set for
2419 ** BNC, the BNC port will indicate activity if it's not terminated correctly.
2420 ** The only way to test for that is to place a loopback packet onto the
2421 ** network and watch for errors. Since we're messing with the interrupt mask
2422 ** register, disable the board interrupts and do not allow any more packets to
2423 ** be queued to the hardware. Re-enable everything only when the media is
2424 ** found.
2425 ** I may have to "age out" locally queued packets so that the higher layer
2426 ** timeouts don't effectively duplicate packets on the network.
2427 */
2428 static int
dc21040_autoconf(struct net_device * dev)2429 dc21040_autoconf(struct net_device *dev)
2430 {
2431 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
2432 u_long iobase = dev->base_addr;
2433 int next_tick = DE4X5_AUTOSENSE_MS;
2434 s32 imr;
2435
2436 switch (lp->media) {
2437 case INIT:
2438 DISABLE_IRQs;
2439 lp->tx_enable = NO;
2440 lp->timeout = -1;
2441 de4x5_save_skbs(dev);
2442 if ((lp->autosense == AUTO) || (lp->autosense == TP)) {
2443 lp->media = TP;
2444 } else if ((lp->autosense == BNC) || (lp->autosense == AUI) || (lp->autosense == BNC_AUI)) {
2445 lp->media = BNC_AUI;
2446 } else if (lp->autosense == EXT_SIA) {
2447 lp->media = EXT_SIA;
2448 } else {
2449 lp->media = NC;
2450 }
2451 lp->local_state = 0;
2452 next_tick = dc21040_autoconf(dev);
2453 break;
2454
2455 case TP:
2456 next_tick = dc21040_state(dev, 0x8f01, 0xffff, 0x0000, 3000, BNC_AUI,
2457 TP_SUSPECT, test_tp);
2458 break;
2459
2460 case TP_SUSPECT:
2461 next_tick = de4x5_suspect_state(dev, 1000, TP, test_tp, dc21040_autoconf);
2462 break;
2463
2464 case BNC:
2465 case AUI:
2466 case BNC_AUI:
2467 next_tick = dc21040_state(dev, 0x8f09, 0x0705, 0x0006, 3000, EXT_SIA,
2468 BNC_AUI_SUSPECT, ping_media);
2469 break;
2470
2471 case BNC_AUI_SUSPECT:
2472 next_tick = de4x5_suspect_state(dev, 1000, BNC_AUI, ping_media, dc21040_autoconf);
2473 break;
2474
2475 case EXT_SIA:
2476 next_tick = dc21040_state(dev, 0x3041, 0x0000, 0x0006, 3000,
2477 NC, EXT_SIA_SUSPECT, ping_media);
2478 break;
2479
2480 case EXT_SIA_SUSPECT:
2481 next_tick = de4x5_suspect_state(dev, 1000, EXT_SIA, ping_media, dc21040_autoconf);
2482 break;
2483
2484 case NC:
2485 /* default to TP for all */
2486 reset_init_sia(dev, 0x8f01, 0xffff, 0x0000);
2487 if (lp->media != lp->c_media) {
2488 de4x5_dbg_media(dev);
2489 lp->c_media = lp->media;
2490 }
2491 lp->media = INIT;
2492 lp->tx_enable = NO;
2493 break;
2494 }
2495
2496 return next_tick;
2497 }
2498
2499 static int
dc21040_state(struct net_device * dev,int csr13,int csr14,int csr15,int timeout,int next_state,int suspect_state,int (* fn)(struct net_device *,int))2500 dc21040_state(struct net_device *dev, int csr13, int csr14, int csr15, int timeout,
2501 int next_state, int suspect_state,
2502 int (*fn)(struct net_device *, int))
2503 {
2504 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
2505 int next_tick = DE4X5_AUTOSENSE_MS;
2506 int linkBad;
2507
2508 switch (lp->local_state) {
2509 case 0:
2510 reset_init_sia(dev, csr13, csr14, csr15);
2511 lp->local_state++;
2512 next_tick = 500;
2513 break;
2514
2515 case 1:
2516 if (!lp->tx_enable) {
2517 linkBad = fn(dev, timeout);
2518 if (linkBad < 0) {
2519 next_tick = linkBad & ~TIMER_CB;
2520 } else {
2521 if (linkBad && (lp->autosense == AUTO)) {
2522 lp->local_state = 0;
2523 lp->media = next_state;
2524 } else {
2525 de4x5_init_connection(dev);
2526 }
2527 }
2528 } else if (!lp->linkOK && (lp->autosense == AUTO)) {
2529 lp->media = suspect_state;
2530 next_tick = 3000;
2531 }
2532 break;
2533 }
2534
2535 return next_tick;
2536 }
2537
2538 static int
de4x5_suspect_state(struct net_device * dev,int timeout,int prev_state,int (* fn)(struct net_device *,int),int (* asfn)(struct net_device *))2539 de4x5_suspect_state(struct net_device *dev, int timeout, int prev_state,
2540 int (*fn)(struct net_device *, int),
2541 int (*asfn)(struct net_device *))
2542 {
2543 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
2544 int next_tick = DE4X5_AUTOSENSE_MS;
2545 int linkBad;
2546
2547 switch (lp->local_state) {
2548 case 1:
2549 if (lp->linkOK) {
2550 lp->media = prev_state;
2551 } else {
2552 lp->local_state++;
2553 next_tick = asfn(dev);
2554 }
2555 break;
2556
2557 case 2:
2558 linkBad = fn(dev, timeout);
2559 if (linkBad < 0) {
2560 next_tick = linkBad & ~TIMER_CB;
2561 } else if (!linkBad) {
2562 lp->local_state--;
2563 lp->media = prev_state;
2564 } else {
2565 lp->media = INIT;
2566 lp->tcount++;
2567 }
2568 }
2569
2570 return next_tick;
2571 }
2572
2573 /*
2574 ** Autoconfigure the media when using the DC21041. AUI needs to be tested
2575 ** before BNC, because the BNC port will indicate activity if it's not
2576 ** terminated correctly. The only way to test for that is to place a loopback
2577 ** packet onto the network and watch for errors. Since we're messing with
2578 ** the interrupt mask register, disable the board interrupts and do not allow
2579 ** any more packets to be queued to the hardware. Re-enable everything only
2580 ** when the media is found.
2581 */
2582 static int
dc21041_autoconf(struct net_device * dev)2583 dc21041_autoconf(struct net_device *dev)
2584 {
2585 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
2586 u_long iobase = dev->base_addr;
2587 s32 sts, irqs, irq_mask, imr, omr;
2588 int next_tick = DE4X5_AUTOSENSE_MS;
2589
2590 switch (lp->media) {
2591 case INIT:
2592 DISABLE_IRQs;
2593 lp->tx_enable = NO;
2594 lp->timeout = -1;
2595 de4x5_save_skbs(dev); /* Save non transmitted skb's */
2596 if ((lp->autosense == AUTO) || (lp->autosense == TP_NW)) {
2597 lp->media = TP; /* On chip auto negotiation is broken */
2598 } else if (lp->autosense == TP) {
2599 lp->media = TP;
2600 } else if (lp->autosense == BNC) {
2601 lp->media = BNC;
2602 } else if (lp->autosense == AUI) {
2603 lp->media = AUI;
2604 } else {
2605 lp->media = NC;
2606 }
2607 lp->local_state = 0;
2608 next_tick = dc21041_autoconf(dev);
2609 break;
2610
2611 case TP_NW:
2612 if (lp->timeout < 0) {
2613 omr = inl(DE4X5_OMR);/* Set up full duplex for the autonegotiate */
2614 outl(omr | OMR_FDX, DE4X5_OMR);
2615 }
2616 irqs = STS_LNF | STS_LNP;
2617 irq_mask = IMR_LFM | IMR_LPM;
2618 sts = test_media(dev, irqs, irq_mask, 0xef01, 0xffff, 0x0008, 2400);
2619 if (sts < 0) {
2620 next_tick = sts & ~TIMER_CB;
2621 } else {
2622 if (sts & STS_LNP) {
2623 lp->media = ANS;
2624 } else {
2625 lp->media = AUI;
2626 }
2627 next_tick = dc21041_autoconf(dev);
2628 }
2629 break;
2630
2631 case ANS:
2632 if (!lp->tx_enable) {
2633 irqs = STS_LNP;
2634 irq_mask = IMR_LPM;
2635 sts = test_ans(dev, irqs, irq_mask, 3000);
2636 if (sts < 0) {
2637 next_tick = sts & ~TIMER_CB;
2638 } else {
2639 if (!(sts & STS_LNP) && (lp->autosense == AUTO)) {
2640 lp->media = TP;
2641 next_tick = dc21041_autoconf(dev);
2642 } else {
2643 lp->local_state = 1;
2644 de4x5_init_connection(dev);
2645 }
2646 }
2647 } else if (!lp->linkOK && (lp->autosense == AUTO)) {
2648 lp->media = ANS_SUSPECT;
2649 next_tick = 3000;
2650 }
2651 break;
2652
2653 case ANS_SUSPECT:
2654 next_tick = de4x5_suspect_state(dev, 1000, ANS, test_tp, dc21041_autoconf);
2655 break;
2656
2657 case TP:
2658 if (!lp->tx_enable) {
2659 if (lp->timeout < 0) {
2660 omr = inl(DE4X5_OMR); /* Set up half duplex for TP */
2661 outl(omr & ~OMR_FDX, DE4X5_OMR);
2662 }
2663 irqs = STS_LNF | STS_LNP;
2664 irq_mask = IMR_LFM | IMR_LPM;
2665 sts = test_media(dev,irqs, irq_mask, 0xef01, 0xff3f, 0x0008, 2400);
2666 if (sts < 0) {
2667 next_tick = sts & ~TIMER_CB;
2668 } else {
2669 if (!(sts & STS_LNP) && (lp->autosense == AUTO)) {
2670 if (inl(DE4X5_SISR) & SISR_NRA) {
2671 lp->media = AUI; /* Non selected port activity */
2672 } else {
2673 lp->media = BNC;
2674 }
2675 next_tick = dc21041_autoconf(dev);
2676 } else {
2677 lp->local_state = 1;
2678 de4x5_init_connection(dev);
2679 }
2680 }
2681 } else if (!lp->linkOK && (lp->autosense == AUTO)) {
2682 lp->media = TP_SUSPECT;
2683 next_tick = 3000;
2684 }
2685 break;
2686
2687 case TP_SUSPECT:
2688 next_tick = de4x5_suspect_state(dev, 1000, TP, test_tp, dc21041_autoconf);
2689 break;
2690
2691 case AUI:
2692 if (!lp->tx_enable) {
2693 if (lp->timeout < 0) {
2694 omr = inl(DE4X5_OMR); /* Set up half duplex for AUI */
2695 outl(omr & ~OMR_FDX, DE4X5_OMR);
2696 }
2697 irqs = 0;
2698 irq_mask = 0;
2699 sts = test_media(dev,irqs, irq_mask, 0xef09, 0xf73d, 0x000e, 1000);
2700 if (sts < 0) {
2701 next_tick = sts & ~TIMER_CB;
2702 } else {
2703 if (!(inl(DE4X5_SISR) & SISR_SRA) && (lp->autosense == AUTO)) {
2704 lp->media = BNC;
2705 next_tick = dc21041_autoconf(dev);
2706 } else {
2707 lp->local_state = 1;
2708 de4x5_init_connection(dev);
2709 }
2710 }
2711 } else if (!lp->linkOK && (lp->autosense == AUTO)) {
2712 lp->media = AUI_SUSPECT;
2713 next_tick = 3000;
2714 }
2715 break;
2716
2717 case AUI_SUSPECT:
2718 next_tick = de4x5_suspect_state(dev, 1000, AUI, ping_media, dc21041_autoconf);
2719 break;
2720
2721 case BNC:
2722 switch (lp->local_state) {
2723 case 0:
2724 if (lp->timeout < 0) {
2725 omr = inl(DE4X5_OMR); /* Set up half duplex for BNC */
2726 outl(omr & ~OMR_FDX, DE4X5_OMR);
2727 }
2728 irqs = 0;
2729 irq_mask = 0;
2730 sts = test_media(dev,irqs, irq_mask, 0xef09, 0xf73d, 0x0006, 1000);
2731 if (sts < 0) {
2732 next_tick = sts & ~TIMER_CB;
2733 } else {
2734 lp->local_state++; /* Ensure media connected */
2735 next_tick = dc21041_autoconf(dev);
2736 }
2737 break;
2738
2739 case 1:
2740 if (!lp->tx_enable) {
2741 if ((sts = ping_media(dev, 3000)) < 0) {
2742 next_tick = sts & ~TIMER_CB;
2743 } else {
2744 if (sts) {
2745 lp->local_state = 0;
2746 lp->media = NC;
2747 } else {
2748 de4x5_init_connection(dev);
2749 }
2750 }
2751 } else if (!lp->linkOK && (lp->autosense == AUTO)) {
2752 lp->media = BNC_SUSPECT;
2753 next_tick = 3000;
2754 }
2755 break;
2756 }
2757 break;
2758
2759 case BNC_SUSPECT:
2760 next_tick = de4x5_suspect_state(dev, 1000, BNC, ping_media, dc21041_autoconf);
2761 break;
2762
2763 case NC:
2764 omr = inl(DE4X5_OMR); /* Set up full duplex for the autonegotiate */
2765 outl(omr | OMR_FDX, DE4X5_OMR);
2766 reset_init_sia(dev, 0xef01, 0xffff, 0x0008);/* Initialise the SIA */
2767 if (lp->media != lp->c_media) {
2768 de4x5_dbg_media(dev);
2769 lp->c_media = lp->media;
2770 }
2771 lp->media = INIT;
2772 lp->tx_enable = NO;
2773 break;
2774 }
2775
2776 return next_tick;
2777 }
2778
2779 /*
2780 ** Some autonegotiation chips are broken in that they do not return the
2781 ** acknowledge bit (anlpa & MII_ANLPA_ACK) in the link partner advertisement
2782 ** register, except at the first power up negotiation.
2783 */
2784 static int
dc21140m_autoconf(struct net_device * dev)2785 dc21140m_autoconf(struct net_device *dev)
2786 {
2787 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
2788 int ana, anlpa, cap, cr, slnk, sr;
2789 int next_tick = DE4X5_AUTOSENSE_MS;
2790 u_long imr, omr, iobase = dev->base_addr;
2791
2792 switch(lp->media) {
2793 case INIT:
2794 if (lp->timeout < 0) {
2795 DISABLE_IRQs;
2796 lp->tx_enable = FALSE;
2797 lp->linkOK = 0;
2798 de4x5_save_skbs(dev); /* Save non transmitted skb's */
2799 }
2800 if ((next_tick = de4x5_reset_phy(dev)) < 0) {
2801 next_tick &= ~TIMER_CB;
2802 } else {
2803 if (lp->useSROM) {
2804 if (srom_map_media(dev) < 0) {
2805 lp->tcount++;
2806 return next_tick;
2807 }
2808 srom_exec(dev, lp->phy[lp->active].gep);
2809 if (lp->infoblock_media == ANS) {
2810 ana = lp->phy[lp->active].ana | MII_ANA_CSMA;
2811 mii_wr(ana, MII_ANA, lp->phy[lp->active].addr, DE4X5_MII);
2812 }
2813 } else {
2814 lp->tmp = MII_SR_ASSC; /* Fake out the MII speed set */
2815 SET_10Mb;
2816 if (lp->autosense == _100Mb) {
2817 lp->media = _100Mb;
2818 } else if (lp->autosense == _10Mb) {
2819 lp->media = _10Mb;
2820 } else if ((lp->autosense == AUTO) &&
2821 ((sr=is_anc_capable(dev)) & MII_SR_ANC)) {
2822 ana = (((sr >> 6) & MII_ANA_TAF) | MII_ANA_CSMA);
2823 ana &= (lp->fdx ? ~0 : ~MII_ANA_FDAM);
2824 mii_wr(ana, MII_ANA, lp->phy[lp->active].addr, DE4X5_MII);
2825 lp->media = ANS;
2826 } else if (lp->autosense == AUTO) {
2827 lp->media = SPD_DET;
2828 } else if (is_spd_100(dev) && is_100_up(dev)) {
2829 lp->media = _100Mb;
2830 } else {
2831 lp->media = NC;
2832 }
2833 }
2834 lp->local_state = 0;
2835 next_tick = dc21140m_autoconf(dev);
2836 }
2837 break;
2838
2839 case ANS:
2840 switch (lp->local_state) {
2841 case 0:
2842 if (lp->timeout < 0) {
2843 mii_wr(MII_CR_ASSE | MII_CR_RAN, MII_CR, lp->phy[lp->active].addr, DE4X5_MII);
2844 }
2845 cr = test_mii_reg(dev, MII_CR, MII_CR_RAN, FALSE, 500);
2846 if (cr < 0) {
2847 next_tick = cr & ~TIMER_CB;
2848 } else {
2849 if (cr) {
2850 lp->local_state = 0;
2851 lp->media = SPD_DET;
2852 } else {
2853 lp->local_state++;
2854 }
2855 next_tick = dc21140m_autoconf(dev);
2856 }
2857 break;
2858
2859 case 1:
2860 if ((sr=test_mii_reg(dev, MII_SR, MII_SR_ASSC, TRUE, 2000)) < 0) {
2861 next_tick = sr & ~TIMER_CB;
2862 } else {
2863 lp->media = SPD_DET;
2864 lp->local_state = 0;
2865 if (sr) { /* Success! */
2866 lp->tmp = MII_SR_ASSC;
2867 anlpa = mii_rd(MII_ANLPA, lp->phy[lp->active].addr, DE4X5_MII);
2868 ana = mii_rd(MII_ANA, lp->phy[lp->active].addr, DE4X5_MII);
2869 if (!(anlpa & MII_ANLPA_RF) &&
2870 (cap = anlpa & MII_ANLPA_TAF & ana)) {
2871 if (cap & MII_ANA_100M) {
2872 lp->fdx = ((ana & anlpa & MII_ANA_FDAM & MII_ANA_100M) ? TRUE : FALSE);
2873 lp->media = _100Mb;
2874 } else if (cap & MII_ANA_10M) {
2875 lp->fdx = ((ana & anlpa & MII_ANA_FDAM & MII_ANA_10M) ? TRUE : FALSE);
2876
2877 lp->media = _10Mb;
2878 }
2879 }
2880 } /* Auto Negotiation failed to finish */
2881 next_tick = dc21140m_autoconf(dev);
2882 } /* Auto Negotiation failed to start */
2883 break;
2884 }
2885 break;
2886
2887 case SPD_DET: /* Choose 10Mb/s or 100Mb/s */
2888 if (lp->timeout < 0) {
2889 lp->tmp = (lp->phy[lp->active].id ? MII_SR_LKS :
2890 (~gep_rd(dev) & GEP_LNP));
2891 SET_100Mb_PDET;
2892 }
2893 if ((slnk = test_for_100Mb(dev, 6500)) < 0) {
2894 next_tick = slnk & ~TIMER_CB;
2895 } else {
2896 if (is_spd_100(dev) && is_100_up(dev)) {
2897 lp->media = _100Mb;
2898 } else if ((!is_spd_100(dev) && (is_10_up(dev) & lp->tmp))) {
2899 lp->media = _10Mb;
2900 } else {
2901 lp->media = NC;
2902 }
2903 next_tick = dc21140m_autoconf(dev);
2904 }
2905 break;
2906
2907 case _100Mb: /* Set 100Mb/s */
2908 next_tick = 3000;
2909 if (!lp->tx_enable) {
2910 SET_100Mb;
2911 de4x5_init_connection(dev);
2912 } else {
2913 if (!lp->linkOK && (lp->autosense == AUTO)) {
2914 if (!is_100_up(dev) || (!lp->useSROM && !is_spd_100(dev))) {
2915 lp->media = INIT;
2916 lp->tcount++;
2917 next_tick = DE4X5_AUTOSENSE_MS;
2918 }
2919 }
2920 }
2921 break;
2922
2923 case BNC:
2924 case AUI:
2925 case _10Mb: /* Set 10Mb/s */
2926 next_tick = 3000;
2927 if (!lp->tx_enable) {
2928 SET_10Mb;
2929 de4x5_init_connection(dev);
2930 } else {
2931 if (!lp->linkOK && (lp->autosense == AUTO)) {
2932 if (!is_10_up(dev) || (!lp->useSROM && is_spd_100(dev))) {
2933 lp->media = INIT;
2934 lp->tcount++;
2935 next_tick = DE4X5_AUTOSENSE_MS;
2936 }
2937 }
2938 }
2939 break;
2940
2941 case NC:
2942 if (lp->media != lp->c_media) {
2943 de4x5_dbg_media(dev);
2944 lp->c_media = lp->media;
2945 }
2946 lp->media = INIT;
2947 lp->tx_enable = FALSE;
2948 break;
2949 }
2950
2951 return next_tick;
2952 }
2953
2954 /*
2955 ** This routine may be merged into dc21140m_autoconf() sometime as I'm
2956 ** changing how I figure out the media - but trying to keep it backwards
2957 ** compatible with the de500-xa and de500-aa.
2958 ** Whether it's BNC, AUI, SYM or MII is sorted out in the infoblock
2959 ** functions and set during de4x5_mac_port() and/or de4x5_reset_phy().
2960 ** This routine just has to figure out whether 10Mb/s or 100Mb/s is
2961 ** active.
2962 ** When autonegotiation is working, the ANS part searches the SROM for
2963 ** the highest common speed (TP) link that both can run and if that can
2964 ** be full duplex. That infoblock is executed and then the link speed set.
2965 **
2966 ** Only _10Mb and _100Mb are tested here.
2967 */
2968 static int
dc2114x_autoconf(struct net_device * dev)2969 dc2114x_autoconf(struct net_device *dev)
2970 {
2971 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
2972 u_long iobase = dev->base_addr;
2973 s32 cr, anlpa, ana, cap, irqs, irq_mask, imr, omr, slnk, sr, sts;
2974 int next_tick = DE4X5_AUTOSENSE_MS;
2975
2976 switch (lp->media) {
2977 case INIT:
2978 if (lp->timeout < 0) {
2979 DISABLE_IRQs;
2980 lp->tx_enable = FALSE;
2981 lp->linkOK = 0;
2982 lp->timeout = -1;
2983 de4x5_save_skbs(dev); /* Save non transmitted skb's */
2984 if (lp->params.autosense & ~AUTO) {
2985 srom_map_media(dev); /* Fixed media requested */
2986 if (lp->media != lp->params.autosense) {
2987 lp->tcount++;
2988 lp->media = INIT;
2989 return next_tick;
2990 }
2991 lp->media = INIT;
2992 }
2993 }
2994 if ((next_tick = de4x5_reset_phy(dev)) < 0) {
2995 next_tick &= ~TIMER_CB;
2996 } else {
2997 if (lp->autosense == _100Mb) {
2998 lp->media = _100Mb;
2999 } else if (lp->autosense == _10Mb) {
3000 lp->media = _10Mb;
3001 } else if (lp->autosense == TP) {
3002 lp->media = TP;
3003 } else if (lp->autosense == BNC) {
3004 lp->media = BNC;
3005 } else if (lp->autosense == AUI) {
3006 lp->media = AUI;
3007 } else {
3008 lp->media = SPD_DET;
3009 if ((lp->infoblock_media == ANS) &&
3010 ((sr=is_anc_capable(dev)) & MII_SR_ANC)) {
3011 ana = (((sr >> 6) & MII_ANA_TAF) | MII_ANA_CSMA);
3012 ana &= (lp->fdx ? ~0 : ~MII_ANA_FDAM);
3013 mii_wr(ana, MII_ANA, lp->phy[lp->active].addr, DE4X5_MII);
3014 lp->media = ANS;
3015 }
3016 }
3017 lp->local_state = 0;
3018 next_tick = dc2114x_autoconf(dev);
3019 }
3020 break;
3021
3022 case ANS:
3023 switch (lp->local_state) {
3024 case 0:
3025 if (lp->timeout < 0) {
3026 mii_wr(MII_CR_ASSE | MII_CR_RAN, MII_CR, lp->phy[lp->active].addr, DE4X5_MII);
3027 }
3028 cr = test_mii_reg(dev, MII_CR, MII_CR_RAN, FALSE, 500);
3029 if (cr < 0) {
3030 next_tick = cr & ~TIMER_CB;
3031 } else {
3032 if (cr) {
3033 lp->local_state = 0;
3034 lp->media = SPD_DET;
3035 } else {
3036 lp->local_state++;
3037 }
3038 next_tick = dc2114x_autoconf(dev);
3039 }
3040 break;
3041
3042 case 1:
3043 if ((sr=test_mii_reg(dev, MII_SR, MII_SR_ASSC, TRUE, 2000)) < 0) {
3044 next_tick = sr & ~TIMER_CB;
3045 } else {
3046 lp->media = SPD_DET;
3047 lp->local_state = 0;
3048 if (sr) { /* Success! */
3049 lp->tmp = MII_SR_ASSC;
3050 anlpa = mii_rd(MII_ANLPA, lp->phy[lp->active].addr, DE4X5_MII);
3051 ana = mii_rd(MII_ANA, lp->phy[lp->active].addr, DE4X5_MII);
3052 if (!(anlpa & MII_ANLPA_RF) &&
3053 (cap = anlpa & MII_ANLPA_TAF & ana)) {
3054 if (cap & MII_ANA_100M) {
3055 lp->fdx = ((ana & anlpa & MII_ANA_FDAM & MII_ANA_100M) ? TRUE : FALSE);
3056 lp->media = _100Mb;
3057 } else if (cap & MII_ANA_10M) {
3058 lp->fdx = ((ana & anlpa & MII_ANA_FDAM & MII_ANA_10M) ? TRUE : FALSE);
3059 lp->media = _10Mb;
3060 }
3061 }
3062 } /* Auto Negotiation failed to finish */
3063 next_tick = dc2114x_autoconf(dev);
3064 } /* Auto Negotiation failed to start */
3065 break;
3066 }
3067 break;
3068
3069 case AUI:
3070 if (!lp->tx_enable) {
3071 if (lp->timeout < 0) {
3072 omr = inl(DE4X5_OMR); /* Set up half duplex for AUI */
3073 outl(omr & ~OMR_FDX, DE4X5_OMR);
3074 }
3075 irqs = 0;
3076 irq_mask = 0;
3077 sts = test_media(dev,irqs, irq_mask, 0, 0, 0, 1000);
3078 if (sts < 0) {
3079 next_tick = sts & ~TIMER_CB;
3080 } else {
3081 if (!(inl(DE4X5_SISR) & SISR_SRA) && (lp->autosense == AUTO)) {
3082 lp->media = BNC;
3083 next_tick = dc2114x_autoconf(dev);
3084 } else {
3085 lp->local_state = 1;
3086 de4x5_init_connection(dev);
3087 }
3088 }
3089 } else if (!lp->linkOK && (lp->autosense == AUTO)) {
3090 lp->media = AUI_SUSPECT;
3091 next_tick = 3000;
3092 }
3093 break;
3094
3095 case AUI_SUSPECT:
3096 next_tick = de4x5_suspect_state(dev, 1000, AUI, ping_media, dc2114x_autoconf);
3097 break;
3098
3099 case BNC:
3100 switch (lp->local_state) {
3101 case 0:
3102 if (lp->timeout < 0) {
3103 omr = inl(DE4X5_OMR); /* Set up half duplex for BNC */
3104 outl(omr & ~OMR_FDX, DE4X5_OMR);
3105 }
3106 irqs = 0;
3107 irq_mask = 0;
3108 sts = test_media(dev,irqs, irq_mask, 0, 0, 0, 1000);
3109 if (sts < 0) {
3110 next_tick = sts & ~TIMER_CB;
3111 } else {
3112 lp->local_state++; /* Ensure media connected */
3113 next_tick = dc2114x_autoconf(dev);
3114 }
3115 break;
3116
3117 case 1:
3118 if (!lp->tx_enable) {
3119 if ((sts = ping_media(dev, 3000)) < 0) {
3120 next_tick = sts & ~TIMER_CB;
3121 } else {
3122 if (sts) {
3123 lp->local_state = 0;
3124 lp->tcount++;
3125 lp->media = INIT;
3126 } else {
3127 de4x5_init_connection(dev);
3128 }
3129 }
3130 } else if (!lp->linkOK && (lp->autosense == AUTO)) {
3131 lp->media = BNC_SUSPECT;
3132 next_tick = 3000;
3133 }
3134 break;
3135 }
3136 break;
3137
3138 case BNC_SUSPECT:
3139 next_tick = de4x5_suspect_state(dev, 1000, BNC, ping_media, dc2114x_autoconf);
3140 break;
3141
3142 case SPD_DET: /* Choose 10Mb/s or 100Mb/s */
3143 if (srom_map_media(dev) < 0) {
3144 lp->tcount++;
3145 lp->media = INIT;
3146 return next_tick;
3147 }
3148 if (lp->media == _100Mb) {
3149 if ((slnk = test_for_100Mb(dev, 6500)) < 0) {
3150 lp->media = SPD_DET;
3151 return (slnk & ~TIMER_CB);
3152 }
3153 } else {
3154 if (wait_for_link(dev) < 0) {
3155 lp->media = SPD_DET;
3156 return PDET_LINK_WAIT;
3157 }
3158 }
3159 if (lp->media == ANS) { /* Do MII parallel detection */
3160 if (is_spd_100(dev)) {
3161 lp->media = _100Mb;
3162 } else {
3163 lp->media = _10Mb;
3164 }
3165 next_tick = dc2114x_autoconf(dev);
3166 } else if (((lp->media == _100Mb) && is_100_up(dev)) ||
3167 (((lp->media == _10Mb) || (lp->media == TP) ||
3168 (lp->media == BNC) || (lp->media == AUI)) &&
3169 is_10_up(dev))) {
3170 next_tick = dc2114x_autoconf(dev);
3171 } else {
3172 lp->tcount++;
3173 lp->media = INIT;
3174 }
3175 break;
3176
3177 case _10Mb:
3178 next_tick = 3000;
3179 if (!lp->tx_enable) {
3180 SET_10Mb;
3181 de4x5_init_connection(dev);
3182 } else {
3183 if (!lp->linkOK && (lp->autosense == AUTO)) {
3184 if (!is_10_up(dev) || (!lp->useSROM && is_spd_100(dev))) {
3185 lp->media = INIT;
3186 lp->tcount++;
3187 next_tick = DE4X5_AUTOSENSE_MS;
3188 }
3189 }
3190 }
3191 break;
3192
3193 case _100Mb:
3194 next_tick = 3000;
3195 if (!lp->tx_enable) {
3196 SET_100Mb;
3197 de4x5_init_connection(dev);
3198 } else {
3199 if (!lp->linkOK && (lp->autosense == AUTO)) {
3200 if (!is_100_up(dev) || (!lp->useSROM && !is_spd_100(dev))) {
3201 lp->media = INIT;
3202 lp->tcount++;
3203 next_tick = DE4X5_AUTOSENSE_MS;
3204 }
3205 }
3206 }
3207 break;
3208
3209 default:
3210 lp->tcount++;
3211 printk("Huh?: media:%02x\n", lp->media);
3212 lp->media = INIT;
3213 break;
3214 }
3215
3216 return next_tick;
3217 }
3218
3219 static int
srom_autoconf(struct net_device * dev)3220 srom_autoconf(struct net_device *dev)
3221 {
3222 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
3223
3224 return lp->infoleaf_fn(dev);
3225 }
3226
3227 /*
3228 ** This mapping keeps the original media codes and FDX flag unchanged.
3229 ** While it isn't strictly necessary, it helps me for the moment...
3230 ** The early return avoids a media state / SROM media space clash.
3231 */
3232 static int
srom_map_media(struct net_device * dev)3233 srom_map_media(struct net_device *dev)
3234 {
3235 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
3236
3237 lp->fdx = 0;
3238 if (lp->infoblock_media == lp->media)
3239 return 0;
3240
3241 switch(lp->infoblock_media) {
3242 case SROM_10BASETF:
3243 if (!lp->params.fdx) return -1;
3244 lp->fdx = TRUE;
3245 case SROM_10BASET:
3246 if (lp->params.fdx && !lp->fdx) return -1;
3247 if ((lp->chipset == DC21140) || ((lp->chipset & ~0x00ff) == DC2114x)) {
3248 lp->media = _10Mb;
3249 } else {
3250 lp->media = TP;
3251 }
3252 break;
3253
3254 case SROM_10BASE2:
3255 lp->media = BNC;
3256 break;
3257
3258 case SROM_10BASE5:
3259 lp->media = AUI;
3260 break;
3261
3262 case SROM_100BASETF:
3263 if (!lp->params.fdx) return -1;
3264 lp->fdx = TRUE;
3265 case SROM_100BASET:
3266 if (lp->params.fdx && !lp->fdx) return -1;
3267 lp->media = _100Mb;
3268 break;
3269
3270 case SROM_100BASET4:
3271 lp->media = _100Mb;
3272 break;
3273
3274 case SROM_100BASEFF:
3275 if (!lp->params.fdx) return -1;
3276 lp->fdx = TRUE;
3277 case SROM_100BASEF:
3278 if (lp->params.fdx && !lp->fdx) return -1;
3279 lp->media = _100Mb;
3280 break;
3281
3282 case ANS:
3283 lp->media = ANS;
3284 lp->fdx = lp->params.fdx;
3285 break;
3286
3287 default:
3288 printk("%s: Bad media code [%d] detected in SROM!\n", dev->name,
3289 lp->infoblock_media);
3290 return -1;
3291 break;
3292 }
3293
3294 return 0;
3295 }
3296
3297 static void
de4x5_init_connection(struct net_device * dev)3298 de4x5_init_connection(struct net_device *dev)
3299 {
3300 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
3301 u_long iobase = dev->base_addr;
3302 u_long flags = 0;
3303
3304 if (lp->media != lp->c_media) {
3305 de4x5_dbg_media(dev);
3306 lp->c_media = lp->media; /* Stop scrolling media messages */
3307 }
3308
3309 spin_lock_irqsave(&lp->lock, flags);
3310 de4x5_rst_desc_ring(dev);
3311 de4x5_setup_intr(dev);
3312 lp->tx_enable = YES;
3313 spin_unlock_irqrestore(&lp->lock, flags);
3314 outl(POLL_DEMAND, DE4X5_TPD);
3315
3316 netif_wake_queue(dev);
3317
3318 return;
3319 }
3320
3321 /*
3322 ** General PHY reset function. Some MII devices don't reset correctly
3323 ** since their MII address pins can float at voltages that are dependent
3324 ** on the signal pin use. Do a double reset to ensure a reset.
3325 */
3326 static int
de4x5_reset_phy(struct net_device * dev)3327 de4x5_reset_phy(struct net_device *dev)
3328 {
3329 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
3330 u_long iobase = dev->base_addr;
3331 int next_tick = 0;
3332
3333 if ((lp->useSROM) || (lp->phy[lp->active].id)) {
3334 if (lp->timeout < 0) {
3335 if (lp->useSROM) {
3336 if (lp->phy[lp->active].rst) {
3337 srom_exec(dev, lp->phy[lp->active].rst);
3338 srom_exec(dev, lp->phy[lp->active].rst);
3339 } else if (lp->rst) { /* Type 5 infoblock reset */
3340 srom_exec(dev, lp->rst);
3341 srom_exec(dev, lp->rst);
3342 }
3343 } else {
3344 PHY_HARD_RESET;
3345 }
3346 if (lp->useMII) {
3347 mii_wr(MII_CR_RST, MII_CR, lp->phy[lp->active].addr, DE4X5_MII);
3348 }
3349 }
3350 if (lp->useMII) {
3351 next_tick = test_mii_reg(dev, MII_CR, MII_CR_RST, FALSE, 500);
3352 }
3353 } else if (lp->chipset == DC21140) {
3354 PHY_HARD_RESET;
3355 }
3356
3357 return next_tick;
3358 }
3359
3360 static int
test_media(struct net_device * dev,s32 irqs,s32 irq_mask,s32 csr13,s32 csr14,s32 csr15,s32 msec)3361 test_media(struct net_device *dev, s32 irqs, s32 irq_mask, s32 csr13, s32 csr14, s32 csr15, s32 msec)
3362 {
3363 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
3364 u_long iobase = dev->base_addr;
3365 s32 sts, csr12;
3366
3367 if (lp->timeout < 0) {
3368 lp->timeout = msec/100;
3369 if (!lp->useSROM) { /* Already done if by SROM, else dc2104[01] */
3370 reset_init_sia(dev, csr13, csr14, csr15);
3371 }
3372
3373 /* set up the interrupt mask */
3374 outl(irq_mask, DE4X5_IMR);
3375
3376 /* clear all pending interrupts */
3377 sts = inl(DE4X5_STS);
3378 outl(sts, DE4X5_STS);
3379
3380 /* clear csr12 NRA and SRA bits */
3381 if ((lp->chipset == DC21041) || lp->useSROM) {
3382 csr12 = inl(DE4X5_SISR);
3383 outl(csr12, DE4X5_SISR);
3384 }
3385 }
3386
3387 sts = inl(DE4X5_STS) & ~TIMER_CB;
3388
3389 if (!(sts & irqs) && --lp->timeout) {
3390 sts = 100 | TIMER_CB;
3391 } else {
3392 lp->timeout = -1;
3393 }
3394
3395 return sts;
3396 }
3397
3398 static int
test_tp(struct net_device * dev,s32 msec)3399 test_tp(struct net_device *dev, s32 msec)
3400 {
3401 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
3402 u_long iobase = dev->base_addr;
3403 int sisr;
3404
3405 if (lp->timeout < 0) {
3406 lp->timeout = msec/100;
3407 }
3408
3409 sisr = (inl(DE4X5_SISR) & ~TIMER_CB) & (SISR_LKF | SISR_NCR);
3410
3411 if (sisr && --lp->timeout) {
3412 sisr = 100 | TIMER_CB;
3413 } else {
3414 lp->timeout = -1;
3415 }
3416
3417 return sisr;
3418 }
3419
3420 /*
3421 ** Samples the 100Mb Link State Signal. The sample interval is important
3422 ** because too fast a rate can give erroneous results and confuse the
3423 ** speed sense algorithm.
3424 */
3425 #define SAMPLE_INTERVAL 500 /* ms */
3426 #define SAMPLE_DELAY 2000 /* ms */
3427 static int
test_for_100Mb(struct net_device * dev,int msec)3428 test_for_100Mb(struct net_device *dev, int msec)
3429 {
3430 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
3431 int gep = 0, ret = ((lp->chipset & ~0x00ff)==DC2114x? -1 :GEP_SLNK);
3432
3433 if (lp->timeout < 0) {
3434 if ((msec/SAMPLE_INTERVAL) <= 0) return 0;
3435 if (msec > SAMPLE_DELAY) {
3436 lp->timeout = (msec - SAMPLE_DELAY)/SAMPLE_INTERVAL;
3437 gep = SAMPLE_DELAY | TIMER_CB;
3438 return gep;
3439 } else {
3440 lp->timeout = msec/SAMPLE_INTERVAL;
3441 }
3442 }
3443
3444 if (lp->phy[lp->active].id || lp->useSROM) {
3445 gep = is_100_up(dev) | is_spd_100(dev);
3446 } else {
3447 gep = (~gep_rd(dev) & (GEP_SLNK | GEP_LNP));
3448 }
3449 if (!(gep & ret) && --lp->timeout) {
3450 gep = SAMPLE_INTERVAL | TIMER_CB;
3451 } else {
3452 lp->timeout = -1;
3453 }
3454
3455 return gep;
3456 }
3457
3458 static int
wait_for_link(struct net_device * dev)3459 wait_for_link(struct net_device *dev)
3460 {
3461 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
3462
3463 if (lp->timeout < 0) {
3464 lp->timeout = 1;
3465 }
3466
3467 if (lp->timeout--) {
3468 return TIMER_CB;
3469 } else {
3470 lp->timeout = -1;
3471 }
3472
3473 return 0;
3474 }
3475
3476 /*
3477 **
3478 **
3479 */
3480 static int
test_mii_reg(struct net_device * dev,int reg,int mask,int pol,long msec)3481 test_mii_reg(struct net_device *dev, int reg, int mask, int pol, long msec)
3482 {
3483 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
3484 int test;
3485 u_long iobase = dev->base_addr;
3486
3487 if (lp->timeout < 0) {
3488 lp->timeout = msec/100;
3489 }
3490
3491 if (pol) pol = ~0;
3492 reg = mii_rd((u_char)reg, lp->phy[lp->active].addr, DE4X5_MII) & mask;
3493 test = (reg ^ pol) & mask;
3494
3495 if (test && --lp->timeout) {
3496 reg = 100 | TIMER_CB;
3497 } else {
3498 lp->timeout = -1;
3499 }
3500
3501 return reg;
3502 }
3503
3504 static int
is_spd_100(struct net_device * dev)3505 is_spd_100(struct net_device *dev)
3506 {
3507 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
3508 u_long iobase = dev->base_addr;
3509 int spd;
3510
3511 if (lp->useMII) {
3512 spd = mii_rd(lp->phy[lp->active].spd.reg, lp->phy[lp->active].addr, DE4X5_MII);
3513 spd = ~(spd ^ lp->phy[lp->active].spd.value);
3514 spd &= lp->phy[lp->active].spd.mask;
3515 } else if (!lp->useSROM) { /* de500-xa */
3516 spd = ((~gep_rd(dev)) & GEP_SLNK);
3517 } else {
3518 if ((lp->ibn == 2) || !lp->asBitValid)
3519 return ((lp->chipset == DC21143)?(~inl(DE4X5_SISR)&SISR_LS100):0);
3520
3521 spd = (lp->asBitValid & (lp->asPolarity ^ (gep_rd(dev) & lp->asBit))) |
3522 (lp->linkOK & ~lp->asBitValid);
3523 }
3524
3525 return spd;
3526 }
3527
3528 static int
is_100_up(struct net_device * dev)3529 is_100_up(struct net_device *dev)
3530 {
3531 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
3532 u_long iobase = dev->base_addr;
3533
3534 if (lp->useMII) {
3535 /* Double read for sticky bits & temporary drops */
3536 mii_rd(MII_SR, lp->phy[lp->active].addr, DE4X5_MII);
3537 return (mii_rd(MII_SR, lp->phy[lp->active].addr, DE4X5_MII) & MII_SR_LKS);
3538 } else if (!lp->useSROM) { /* de500-xa */
3539 return ((~gep_rd(dev)) & GEP_SLNK);
3540 } else {
3541 if ((lp->ibn == 2) || !lp->asBitValid)
3542 return ((lp->chipset == DC21143)?(~inl(DE4X5_SISR)&SISR_LS100):0);
3543
3544 return ((lp->asBitValid&(lp->asPolarity^(gep_rd(dev)&lp->asBit))) |
3545 (lp->linkOK & ~lp->asBitValid));
3546 }
3547 }
3548
3549 static int
is_10_up(struct net_device * dev)3550 is_10_up(struct net_device *dev)
3551 {
3552 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
3553 u_long iobase = dev->base_addr;
3554
3555 if (lp->useMII) {
3556 /* Double read for sticky bits & temporary drops */
3557 mii_rd(MII_SR, lp->phy[lp->active].addr, DE4X5_MII);
3558 return (mii_rd(MII_SR, lp->phy[lp->active].addr, DE4X5_MII) & MII_SR_LKS);
3559 } else if (!lp->useSROM) { /* de500-xa */
3560 return ((~gep_rd(dev)) & GEP_LNP);
3561 } else {
3562 if ((lp->ibn == 2) || !lp->asBitValid)
3563 return (((lp->chipset & ~0x00ff) == DC2114x) ?
3564 (~inl(DE4X5_SISR)&SISR_LS10):
3565 0);
3566
3567 return ((lp->asBitValid&(lp->asPolarity^(gep_rd(dev)&lp->asBit))) |
3568 (lp->linkOK & ~lp->asBitValid));
3569 }
3570 }
3571
3572 static int
is_anc_capable(struct net_device * dev)3573 is_anc_capable(struct net_device *dev)
3574 {
3575 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
3576 u_long iobase = dev->base_addr;
3577
3578 if (lp->phy[lp->active].id && (!lp->useSROM || lp->useMII)) {
3579 return (mii_rd(MII_SR, lp->phy[lp->active].addr, DE4X5_MII));
3580 } else if ((lp->chipset & ~0x00ff) == DC2114x) {
3581 return (inl(DE4X5_SISR) & SISR_LPN) >> 12;
3582 } else {
3583 return 0;
3584 }
3585 }
3586
3587 /*
3588 ** Send a packet onto the media and watch for send errors that indicate the
3589 ** media is bad or unconnected.
3590 */
3591 static int
ping_media(struct net_device * dev,int msec)3592 ping_media(struct net_device *dev, int msec)
3593 {
3594 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
3595 u_long iobase = dev->base_addr;
3596 int sisr;
3597
3598 if (lp->timeout < 0) {
3599 lp->timeout = msec/100;
3600
3601 lp->tmp = lp->tx_new; /* Remember the ring position */
3602 load_packet(dev, lp->frame, TD_LS | TD_FS | sizeof(lp->frame), (struct sk_buff *)1);
3603 lp->tx_new = (++lp->tx_new) % lp->txRingSize;
3604 outl(POLL_DEMAND, DE4X5_TPD);
3605 }
3606
3607 sisr = inl(DE4X5_SISR);
3608
3609 if ((!(sisr & SISR_NCR)) &&
3610 ((s32)le32_to_cpu(lp->tx_ring[lp->tmp].status) < 0) &&
3611 (--lp->timeout)) {
3612 sisr = 100 | TIMER_CB;
3613 } else {
3614 if ((!(sisr & SISR_NCR)) &&
3615 !(le32_to_cpu(lp->tx_ring[lp->tmp].status) & (T_OWN | TD_ES)) &&
3616 lp->timeout) {
3617 sisr = 0;
3618 } else {
3619 sisr = 1;
3620 }
3621 lp->timeout = -1;
3622 }
3623
3624 return sisr;
3625 }
3626
3627 /*
3628 ** This function does 2 things: on Intels it kmalloc's another buffer to
3629 ** replace the one about to be passed up. On Alpha's it kmallocs a buffer
3630 ** into which the packet is copied.
3631 */
3632 static struct sk_buff *
de4x5_alloc_rx_buff(struct net_device * dev,int index,int len)3633 de4x5_alloc_rx_buff(struct net_device *dev, int index, int len)
3634 {
3635 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
3636 struct sk_buff *p;
3637
3638 #if !defined(__alpha__) && !defined(__powerpc__) && !defined(__sparc_v9__) && !defined(DE4X5_DO_MEMCPY)
3639 struct sk_buff *ret;
3640 u_long i=0, tmp;
3641
3642 p = dev_alloc_skb(IEEE802_3_SZ + DE4X5_ALIGN + 2);
3643 if (!p) return NULL;
3644
3645 p->dev = dev;
3646 tmp = virt_to_bus(p->data);
3647 i = ((tmp + DE4X5_ALIGN) & ~DE4X5_ALIGN) - tmp;
3648 skb_reserve(p, i);
3649 lp->rx_ring[index].buf = cpu_to_le32(tmp + i);
3650
3651 ret = lp->rx_skb[index];
3652 lp->rx_skb[index] = p;
3653
3654 if ((u_long) ret > 1) {
3655 skb_put(ret, len);
3656 }
3657
3658 return ret;
3659
3660 #else
3661 if (lp->state != OPEN) return (struct sk_buff *)1; /* Fake out the open */
3662
3663 p = dev_alloc_skb(len + 2);
3664 if (!p) return NULL;
3665
3666 p->dev = dev;
3667 skb_reserve(p, 2); /* Align */
3668 if (index < lp->rx_old) { /* Wrapped buffer */
3669 short tlen = (lp->rxRingSize - lp->rx_old) * RX_BUFF_SZ;
3670 memcpy(skb_put(p,tlen),lp->rx_bufs + lp->rx_old * RX_BUFF_SZ,tlen);
3671 memcpy(skb_put(p,len-tlen),lp->rx_bufs,len-tlen);
3672 } else { /* Linear buffer */
3673 memcpy(skb_put(p,len),lp->rx_bufs + lp->rx_old * RX_BUFF_SZ,len);
3674 }
3675
3676 return p;
3677 #endif
3678 }
3679
3680 static void
de4x5_free_rx_buffs(struct net_device * dev)3681 de4x5_free_rx_buffs(struct net_device *dev)
3682 {
3683 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
3684 int i;
3685
3686 for (i=0; i<lp->rxRingSize; i++) {
3687 if ((u_long) lp->rx_skb[i] > 1) {
3688 dev_kfree_skb(lp->rx_skb[i]);
3689 }
3690 lp->rx_ring[i].status = 0;
3691 lp->rx_skb[i] = (struct sk_buff *)1; /* Dummy entry */
3692 }
3693
3694 return;
3695 }
3696
3697 static void
de4x5_free_tx_buffs(struct net_device * dev)3698 de4x5_free_tx_buffs(struct net_device *dev)
3699 {
3700 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
3701 int i;
3702
3703 for (i=0; i<lp->txRingSize; i++) {
3704 if (lp->tx_skb[i])
3705 de4x5_free_tx_buff(lp, i);
3706 lp->tx_ring[i].status = 0;
3707 }
3708
3709 /* Unload the locally queued packets */
3710 while (lp->cache.skb) {
3711 dev_kfree_skb(de4x5_get_cache(dev));
3712 }
3713
3714 return;
3715 }
3716
3717 /*
3718 ** When a user pulls a connection, the DECchip can end up in a
3719 ** 'running - waiting for end of transmission' state. This means that we
3720 ** have to perform a chip soft reset to ensure that we can synchronize
3721 ** the hardware and software and make any media probes using a loopback
3722 ** packet meaningful.
3723 */
3724 static void
de4x5_save_skbs(struct net_device * dev)3725 de4x5_save_skbs(struct net_device *dev)
3726 {
3727 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
3728 u_long iobase = dev->base_addr;
3729 s32 omr;
3730
3731 if (!lp->cache.save_cnt) {
3732 STOP_DE4X5;
3733 de4x5_tx(dev); /* Flush any sent skb's */
3734 de4x5_free_tx_buffs(dev);
3735 de4x5_cache_state(dev, DE4X5_SAVE_STATE);
3736 de4x5_sw_reset(dev);
3737 de4x5_cache_state(dev, DE4X5_RESTORE_STATE);
3738 lp->cache.save_cnt++;
3739 START_DE4X5;
3740 }
3741
3742 return;
3743 }
3744
3745 static void
de4x5_rst_desc_ring(struct net_device * dev)3746 de4x5_rst_desc_ring(struct net_device *dev)
3747 {
3748 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
3749 u_long iobase = dev->base_addr;
3750 int i;
3751 s32 omr;
3752
3753 if (lp->cache.save_cnt) {
3754 STOP_DE4X5;
3755 outl(lp->dma_rings, DE4X5_RRBA);
3756 outl(lp->dma_rings + NUM_RX_DESC * sizeof(struct de4x5_desc),
3757 DE4X5_TRBA);
3758
3759 lp->rx_new = lp->rx_old = 0;
3760 lp->tx_new = lp->tx_old = 0;
3761
3762 for (i = 0; i < lp->rxRingSize; i++) {
3763 lp->rx_ring[i].status = cpu_to_le32(R_OWN);
3764 }
3765
3766 for (i = 0; i < lp->txRingSize; i++) {
3767 lp->tx_ring[i].status = cpu_to_le32(0);
3768 }
3769
3770 barrier();
3771 lp->cache.save_cnt--;
3772 START_DE4X5;
3773 }
3774
3775 return;
3776 }
3777
3778 static void
de4x5_cache_state(struct net_device * dev,int flag)3779 de4x5_cache_state(struct net_device *dev, int flag)
3780 {
3781 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
3782 u_long iobase = dev->base_addr;
3783
3784 switch(flag) {
3785 case DE4X5_SAVE_STATE:
3786 lp->cache.csr0 = inl(DE4X5_BMR);
3787 lp->cache.csr6 = (inl(DE4X5_OMR) & ~(OMR_ST | OMR_SR));
3788 lp->cache.csr7 = inl(DE4X5_IMR);
3789 break;
3790
3791 case DE4X5_RESTORE_STATE:
3792 outl(lp->cache.csr0, DE4X5_BMR);
3793 outl(lp->cache.csr6, DE4X5_OMR);
3794 outl(lp->cache.csr7, DE4X5_IMR);
3795 if (lp->chipset == DC21140) {
3796 gep_wr(lp->cache.gepc, dev);
3797 gep_wr(lp->cache.gep, dev);
3798 } else {
3799 reset_init_sia(dev, lp->cache.csr13, lp->cache.csr14,
3800 lp->cache.csr15);
3801 }
3802 break;
3803 }
3804
3805 return;
3806 }
3807
3808 static void
de4x5_put_cache(struct net_device * dev,struct sk_buff * skb)3809 de4x5_put_cache(struct net_device *dev, struct sk_buff *skb)
3810 {
3811 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
3812 struct sk_buff *p;
3813
3814 if (lp->cache.skb) {
3815 for (p=lp->cache.skb; p->next; p=p->next);
3816 p->next = skb;
3817 } else {
3818 lp->cache.skb = skb;
3819 }
3820 skb->next = NULL;
3821
3822 return;
3823 }
3824
3825 static void
de4x5_putb_cache(struct net_device * dev,struct sk_buff * skb)3826 de4x5_putb_cache(struct net_device *dev, struct sk_buff *skb)
3827 {
3828 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
3829 struct sk_buff *p = lp->cache.skb;
3830
3831 lp->cache.skb = skb;
3832 skb->next = p;
3833
3834 return;
3835 }
3836
3837 static struct sk_buff *
de4x5_get_cache(struct net_device * dev)3838 de4x5_get_cache(struct net_device *dev)
3839 {
3840 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
3841 struct sk_buff *p = lp->cache.skb;
3842
3843 if (p) {
3844 lp->cache.skb = p->next;
3845 p->next = NULL;
3846 }
3847
3848 return p;
3849 }
3850
3851 /*
3852 ** Check the Auto Negotiation State. Return OK when a link pass interrupt
3853 ** is received and the auto-negotiation status is NWAY OK.
3854 */
3855 static int
test_ans(struct net_device * dev,s32 irqs,s32 irq_mask,s32 msec)3856 test_ans(struct net_device *dev, s32 irqs, s32 irq_mask, s32 msec)
3857 {
3858 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
3859 u_long iobase = dev->base_addr;
3860 s32 sts, ans;
3861
3862 if (lp->timeout < 0) {
3863 lp->timeout = msec/100;
3864 outl(irq_mask, DE4X5_IMR);
3865
3866 /* clear all pending interrupts */
3867 sts = inl(DE4X5_STS);
3868 outl(sts, DE4X5_STS);
3869 }
3870
3871 ans = inl(DE4X5_SISR) & SISR_ANS;
3872 sts = inl(DE4X5_STS) & ~TIMER_CB;
3873
3874 if (!(sts & irqs) && (ans ^ ANS_NWOK) && --lp->timeout) {
3875 sts = 100 | TIMER_CB;
3876 } else {
3877 lp->timeout = -1;
3878 }
3879
3880 return sts;
3881 }
3882
3883 static void
de4x5_setup_intr(struct net_device * dev)3884 de4x5_setup_intr(struct net_device *dev)
3885 {
3886 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
3887 u_long iobase = dev->base_addr;
3888 s32 imr, sts;
3889
3890 if (inl(DE4X5_OMR) & OMR_SR) { /* Only unmask if TX/RX is enabled */
3891 imr = 0;
3892 UNMASK_IRQs;
3893 sts = inl(DE4X5_STS); /* Reset any pending (stale) interrupts */
3894 outl(sts, DE4X5_STS);
3895 ENABLE_IRQs;
3896 }
3897
3898 return;
3899 }
3900
3901 /*
3902 **
3903 */
3904 static void
reset_init_sia(struct net_device * dev,s32 csr13,s32 csr14,s32 csr15)3905 reset_init_sia(struct net_device *dev, s32 csr13, s32 csr14, s32 csr15)
3906 {
3907 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
3908 u_long iobase = dev->base_addr;
3909
3910 RESET_SIA;
3911 if (lp->useSROM) {
3912 if (lp->ibn == 3) {
3913 srom_exec(dev, lp->phy[lp->active].rst);
3914 srom_exec(dev, lp->phy[lp->active].gep);
3915 outl(1, DE4X5_SICR);
3916 return;
3917 } else {
3918 csr15 = lp->cache.csr15;
3919 csr14 = lp->cache.csr14;
3920 csr13 = lp->cache.csr13;
3921 outl(csr15 | lp->cache.gepc, DE4X5_SIGR);
3922 outl(csr15 | lp->cache.gep, DE4X5_SIGR);
3923 }
3924 } else {
3925 outl(csr15, DE4X5_SIGR);
3926 }
3927 outl(csr14, DE4X5_STRR);
3928 outl(csr13, DE4X5_SICR);
3929
3930 mdelay(10);
3931
3932 return;
3933 }
3934
3935 /*
3936 ** Create a loopback ethernet packet
3937 */
3938 static void
create_packet(struct net_device * dev,char * frame,int len)3939 create_packet(struct net_device *dev, char *frame, int len)
3940 {
3941 int i;
3942 char *buf = frame;
3943
3944 for (i=0; i<ETH_ALEN; i++) { /* Use this source address */
3945 *buf++ = dev->dev_addr[i];
3946 }
3947 for (i=0; i<ETH_ALEN; i++) { /* Use this destination address */
3948 *buf++ = dev->dev_addr[i];
3949 }
3950
3951 *buf++ = 0; /* Packet length (2 bytes) */
3952 *buf++ = 1;
3953
3954 return;
3955 }
3956
3957 /*
3958 ** Look for a particular board name in the EISA configuration space
3959 */
3960 static int
EISA_signature(char * name,s32 eisa_id)3961 EISA_signature(char *name, s32 eisa_id)
3962 {
3963 static c_char *signatures[] = DE4X5_SIGNATURE;
3964 char ManCode[DE4X5_STRLEN];
3965 union {
3966 s32 ID;
3967 char Id[4];
3968 } Eisa;
3969 int i, status = 0, siglen = sizeof(signatures)/sizeof(c_char *);
3970
3971 *name = '\0';
3972 Eisa.ID = inl(eisa_id);
3973
3974 ManCode[0]=(((Eisa.Id[0]>>2)&0x1f)+0x40);
3975 ManCode[1]=(((Eisa.Id[1]&0xe0)>>5)+((Eisa.Id[0]&0x03)<<3)+0x40);
3976 ManCode[2]=(((Eisa.Id[2]>>4)&0x0f)+0x30);
3977 ManCode[3]=((Eisa.Id[2]&0x0f)+0x30);
3978 ManCode[4]=(((Eisa.Id[3]>>4)&0x0f)+0x30);
3979 ManCode[5]='\0';
3980
3981 for (i=0;i<siglen;i++) {
3982 if (strstr(ManCode, signatures[i]) != NULL) {
3983 strcpy(name,ManCode);
3984 status = 1;
3985 break;
3986 }
3987 }
3988
3989 return status; /* return the device name string */
3990 }
3991
3992 /*
3993 ** Look for a particular board name in the PCI configuration space
3994 */
3995 static int
PCI_signature(char * name,struct de4x5_bus_type * lp)3996 PCI_signature(char *name, struct de4x5_bus_type *lp)
3997 {
3998 static c_char *de4x5_signatures[] = DE4X5_SIGNATURE;
3999 int i, status = 0, siglen = sizeof(de4x5_signatures)/sizeof(c_char *);
4000
4001 if (lp->chipset == DC21040) {
4002 strcpy(name, "DE434/5");
4003 return status;
4004 } else { /* Search for a DEC name in the SROM */
4005 int i = *((char *)&lp->srom + 19) * 3;
4006 strncpy(name, (char *)&lp->srom + 26 + i, 8);
4007 }
4008 name[8] = '\0';
4009 for (i=0; i<siglen; i++) {
4010 if (strstr(name,de4x5_signatures[i])!=NULL) break;
4011 }
4012 if (i == siglen) {
4013 if (dec_only) {
4014 *name = '\0';
4015 } else { /* Use chip name to avoid confusion */
4016 strcpy(name, (((lp->chipset == DC21040) ? "DC21040" :
4017 ((lp->chipset == DC21041) ? "DC21041" :
4018 ((lp->chipset == DC21140) ? "DC21140" :
4019 ((lp->chipset == DC21142) ? "DC21142" :
4020 ((lp->chipset == DC21143) ? "DC21143" : "UNKNOWN"
4021 )))))));
4022 }
4023 if (lp->chipset != DC21041) {
4024 useSROM = TRUE; /* card is not recognisably DEC */
4025 }
4026 } else if ((lp->chipset & ~0x00ff) == DC2114x) {
4027 useSROM = TRUE;
4028 }
4029
4030 return status;
4031 }
4032
4033 /*
4034 ** Set up the Ethernet PROM counter to the start of the Ethernet address on
4035 ** the DC21040, else read the SROM for the other chips.
4036 ** The SROM may not be present in a multi-MAC card, so first read the
4037 ** MAC address and check for a bad address. If there is a bad one then exit
4038 ** immediately with the prior srom contents intact (the h/w address will
4039 ** be fixed up later).
4040 */
4041 static void
DevicePresent(u_long aprom_addr)4042 DevicePresent(u_long aprom_addr)
4043 {
4044 int i, j=0;
4045 struct de4x5_bus_type *lp = &bus;
4046
4047 if (lp->chipset == DC21040) {
4048 if (lp->bus == EISA) {
4049 enet_addr_rst(aprom_addr); /* Reset Ethernet Address ROM Pointer */
4050 } else {
4051 outl(0, aprom_addr); /* Reset Ethernet Address ROM Pointer */
4052 }
4053 } else { /* Read new srom */
4054 u_short tmp, *p = (short *)((char *)&lp->srom + SROM_HWADD);
4055 for (i=0; i<(ETH_ALEN>>1); i++) {
4056 tmp = srom_rd(aprom_addr, (SROM_HWADD>>1) + i);
4057 *p = le16_to_cpu(tmp);
4058 j += *p++;
4059 }
4060 if ((j == 0) || (j == 0x2fffd)) {
4061 return;
4062 }
4063
4064 p=(short *)&lp->srom;
4065 for (i=0; i<(sizeof(struct de4x5_srom)>>1); i++) {
4066 tmp = srom_rd(aprom_addr, i);
4067 *p++ = le16_to_cpu(tmp);
4068 }
4069 de4x5_dbg_srom((struct de4x5_srom *)&lp->srom);
4070 }
4071
4072 return;
4073 }
4074
4075 /*
4076 ** Since the write on the Enet PROM register doesn't seem to reset the PROM
4077 ** pointer correctly (at least on my DE425 EISA card), this routine should do
4078 ** it...from depca.c.
4079 */
4080 static void
enet_addr_rst(u_long aprom_addr)4081 enet_addr_rst(u_long aprom_addr)
4082 {
4083 union {
4084 struct {
4085 u32 a;
4086 u32 b;
4087 } llsig;
4088 char Sig[sizeof(u32) << 1];
4089 } dev;
4090 short sigLength=0;
4091 s8 data;
4092 int i, j;
4093
4094 dev.llsig.a = ETH_PROM_SIG;
4095 dev.llsig.b = ETH_PROM_SIG;
4096 sigLength = sizeof(u32) << 1;
4097
4098 for (i=0,j=0;j<sigLength && i<PROBE_LENGTH+sigLength-1;i++) {
4099 data = inb(aprom_addr);
4100 if (dev.Sig[j] == data) { /* track signature */
4101 j++;
4102 } else { /* lost signature; begin search again */
4103 if (data == dev.Sig[0]) { /* rare case.... */
4104 j=1;
4105 } else {
4106 j=0;
4107 }
4108 }
4109 }
4110
4111 return;
4112 }
4113
4114 /*
4115 ** For the bad status case and no SROM, then add one to the previous
4116 ** address. However, need to add one backwards in case we have 0xff
4117 ** as one or more of the bytes. Only the last 3 bytes should be checked
4118 ** as the first three are invariant - assigned to an organisation.
4119 */
4120 static int
get_hw_addr(struct net_device * dev)4121 get_hw_addr(struct net_device *dev)
4122 {
4123 u_long iobase = dev->base_addr;
4124 int broken, i, k, tmp, status = 0;
4125 u_short j,chksum;
4126 struct de4x5_bus_type *lp = &bus;
4127
4128 broken = de4x5_bad_srom(lp);
4129
4130 for (i=0,k=0,j=0;j<3;j++) {
4131 k <<= 1;
4132 if (k > 0xffff) k-=0xffff;
4133
4134 if (lp->bus == PCI) {
4135 if (lp->chipset == DC21040) {
4136 while ((tmp = inl(DE4X5_APROM)) < 0);
4137 k += (u_char) tmp;
4138 dev->dev_addr[i++] = (u_char) tmp;
4139 while ((tmp = inl(DE4X5_APROM)) < 0);
4140 k += (u_short) (tmp << 8);
4141 dev->dev_addr[i++] = (u_char) tmp;
4142 } else if (!broken) {
4143 dev->dev_addr[i] = (u_char) lp->srom.ieee_addr[i]; i++;
4144 dev->dev_addr[i] = (u_char) lp->srom.ieee_addr[i]; i++;
4145 } else if ((broken == SMC) || (broken == ACCTON)) {
4146 dev->dev_addr[i] = *((u_char *)&lp->srom + i); i++;
4147 dev->dev_addr[i] = *((u_char *)&lp->srom + i); i++;
4148 }
4149 } else {
4150 k += (u_char) (tmp = inb(EISA_APROM));
4151 dev->dev_addr[i++] = (u_char) tmp;
4152 k += (u_short) ((tmp = inb(EISA_APROM)) << 8);
4153 dev->dev_addr[i++] = (u_char) tmp;
4154 }
4155
4156 if (k > 0xffff) k-=0xffff;
4157 }
4158 if (k == 0xffff) k=0;
4159
4160 if (lp->bus == PCI) {
4161 if (lp->chipset == DC21040) {
4162 while ((tmp = inl(DE4X5_APROM)) < 0);
4163 chksum = (u_char) tmp;
4164 while ((tmp = inl(DE4X5_APROM)) < 0);
4165 chksum |= (u_short) (tmp << 8);
4166 if ((k != chksum) && (dec_only)) status = -1;
4167 }
4168 } else {
4169 chksum = (u_char) inb(EISA_APROM);
4170 chksum |= (u_short) (inb(EISA_APROM) << 8);
4171 if ((k != chksum) && (dec_only)) status = -1;
4172 }
4173
4174 /* If possible, try to fix a broken card - SMC only so far */
4175 srom_repair(dev, broken);
4176
4177 #ifdef CONFIG_PPC
4178 /*
4179 ** If the address starts with 00 a0, we have to bit-reverse
4180 ** each byte of the address.
4181 */
4182 if ( (ppc_md.ppc_machine & _MACH_Pmac) &&
4183 (dev->dev_addr[0] == 0) &&
4184 (dev->dev_addr[1] == 0xa0) )
4185 {
4186 for (i = 0; i < ETH_ALEN; ++i)
4187 {
4188 int x = dev->dev_addr[i];
4189 x = ((x & 0xf) << 4) + ((x & 0xf0) >> 4);
4190 x = ((x & 0x33) << 2) + ((x & 0xcc) >> 2);
4191 dev->dev_addr[i] = ((x & 0x55) << 1) + ((x & 0xaa) >> 1);
4192 }
4193 }
4194 #endif /* CONFIG_PPC */
4195
4196 /* Test for a bad enet address */
4197 status = test_bad_enet(dev, status);
4198
4199 return status;
4200 }
4201
4202 /*
4203 ** Test for enet addresses in the first 32 bytes. The built-in strncmp
4204 ** didn't seem to work here...?
4205 */
4206 static int
de4x5_bad_srom(struct de4x5_bus_type * lp)4207 de4x5_bad_srom(struct de4x5_bus_type *lp)
4208 {
4209 int i, status = 0;
4210
4211 for (i=0; i<sizeof(enet_det)/ETH_ALEN; i++) {
4212 if (!de4x5_strncmp((char *)&lp->srom, (char *)&enet_det[i], 3) &&
4213 !de4x5_strncmp((char *)&lp->srom+0x10, (char *)&enet_det[i], 3)) {
4214 if (i == 0) {
4215 status = SMC;
4216 } else if (i == 1) {
4217 status = ACCTON;
4218 }
4219 break;
4220 }
4221 }
4222
4223 return status;
4224 }
4225
4226 static int
de4x5_strncmp(char * a,char * b,int n)4227 de4x5_strncmp(char *a, char *b, int n)
4228 {
4229 int ret=0;
4230
4231 for (;n && !ret;n--) {
4232 ret = *a++ - *b++;
4233 }
4234
4235 return ret;
4236 }
4237
4238 static void
srom_repair(struct net_device * dev,int card)4239 srom_repair(struct net_device *dev, int card)
4240 {
4241 struct de4x5_bus_type *lp = &bus;
4242
4243 switch(card) {
4244 case SMC:
4245 memset((char *)&bus.srom, 0, sizeof(struct de4x5_srom));
4246 memcpy(lp->srom.ieee_addr, (char *)dev->dev_addr, ETH_ALEN);
4247 memcpy(lp->srom.info, (char *)&srom_repair_info[SMC-1], 100);
4248 useSROM = TRUE;
4249 break;
4250 }
4251
4252 return;
4253 }
4254
4255 /*
4256 ** Assume that the irq's do not follow the PCI spec - this is seems
4257 ** to be true so far (2 for 2).
4258 */
4259 static int
test_bad_enet(struct net_device * dev,int status)4260 test_bad_enet(struct net_device *dev, int status)
4261 {
4262 struct de4x5_bus_type *lp = &bus;
4263 int i, tmp;
4264
4265 for (tmp=0,i=0; i<ETH_ALEN; i++) tmp += (u_char)dev->dev_addr[i];
4266 if ((tmp == 0) || (tmp == 0x5fa)) {
4267 if ((lp->chipset == last.chipset) &&
4268 (lp->bus_num == last.bus) && (lp->bus_num > 0)) {
4269 for (i=0; i<ETH_ALEN; i++) dev->dev_addr[i] = last.addr[i];
4270 for (i=ETH_ALEN-1; i>2; --i) {
4271 dev->dev_addr[i] += 1;
4272 if (dev->dev_addr[i] != 0) break;
4273 }
4274 for (i=0; i<ETH_ALEN; i++) last.addr[i] = dev->dev_addr[i];
4275 if (!an_exception(lp)) {
4276 dev->irq = last.irq;
4277 }
4278
4279 status = 0;
4280 }
4281 } else if (!status) {
4282 last.chipset = lp->chipset;
4283 last.bus = lp->bus_num;
4284 last.irq = dev->irq;
4285 for (i=0; i<ETH_ALEN; i++) last.addr[i] = dev->dev_addr[i];
4286 }
4287
4288 return status;
4289 }
4290
4291 /*
4292 ** List of board exceptions with correctly wired IRQs
4293 */
4294 static int
an_exception(struct de4x5_bus_type * lp)4295 an_exception(struct de4x5_bus_type *lp)
4296 {
4297 if ((*(u_short *)lp->srom.sub_vendor_id == 0x00c0) &&
4298 (*(u_short *)lp->srom.sub_system_id == 0x95e0)) {
4299 return -1;
4300 }
4301
4302 return 0;
4303 }
4304
4305 /*
4306 ** SROM Read
4307 */
4308 static short
srom_rd(u_long addr,u_char offset)4309 srom_rd(u_long addr, u_char offset)
4310 {
4311 sendto_srom(SROM_RD | SROM_SR, addr);
4312
4313 srom_latch(SROM_RD | SROM_SR | DT_CS, addr);
4314 srom_command(SROM_RD | SROM_SR | DT_IN | DT_CS, addr);
4315 srom_address(SROM_RD | SROM_SR | DT_CS, addr, offset);
4316
4317 return srom_data(SROM_RD | SROM_SR | DT_CS, addr);
4318 }
4319
4320 static void
srom_latch(u_int command,u_long addr)4321 srom_latch(u_int command, u_long addr)
4322 {
4323 sendto_srom(command, addr);
4324 sendto_srom(command | DT_CLK, addr);
4325 sendto_srom(command, addr);
4326
4327 return;
4328 }
4329
4330 static void
srom_command(u_int command,u_long addr)4331 srom_command(u_int command, u_long addr)
4332 {
4333 srom_latch(command, addr);
4334 srom_latch(command, addr);
4335 srom_latch((command & 0x0000ff00) | DT_CS, addr);
4336
4337 return;
4338 }
4339
4340 static void
srom_address(u_int command,u_long addr,u_char offset)4341 srom_address(u_int command, u_long addr, u_char offset)
4342 {
4343 int i, a;
4344
4345 a = offset << 2;
4346 for (i=0; i<6; i++, a <<= 1) {
4347 srom_latch(command | ((a & 0x80) ? DT_IN : 0), addr);
4348 }
4349 udelay(1);
4350
4351 i = (getfrom_srom(addr) >> 3) & 0x01;
4352
4353 return;
4354 }
4355
4356 static short
srom_data(u_int command,u_long addr)4357 srom_data(u_int command, u_long addr)
4358 {
4359 int i;
4360 short word = 0;
4361 s32 tmp;
4362
4363 for (i=0; i<16; i++) {
4364 sendto_srom(command | DT_CLK, addr);
4365 tmp = getfrom_srom(addr);
4366 sendto_srom(command, addr);
4367
4368 word = (word << 1) | ((tmp >> 3) & 0x01);
4369 }
4370
4371 sendto_srom(command & 0x0000ff00, addr);
4372
4373 return word;
4374 }
4375
4376 /*
4377 static void
4378 srom_busy(u_int command, u_long addr)
4379 {
4380 sendto_srom((command & 0x0000ff00) | DT_CS, addr);
4381
4382 while (!((getfrom_srom(addr) >> 3) & 0x01)) {
4383 mdelay(1);
4384 }
4385
4386 sendto_srom(command & 0x0000ff00, addr);
4387
4388 return;
4389 }
4390 */
4391
4392 static void
sendto_srom(u_int command,u_long addr)4393 sendto_srom(u_int command, u_long addr)
4394 {
4395 outl(command, addr);
4396 udelay(1);
4397
4398 return;
4399 }
4400
4401 static int
getfrom_srom(u_long addr)4402 getfrom_srom(u_long addr)
4403 {
4404 s32 tmp;
4405
4406 tmp = inl(addr);
4407 udelay(1);
4408
4409 return tmp;
4410 }
4411
4412 static int
srom_infoleaf_info(struct net_device * dev)4413 srom_infoleaf_info(struct net_device *dev)
4414 {
4415 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
4416 int i, count;
4417 u_char *p;
4418
4419 /* Find the infoleaf decoder function that matches this chipset */
4420 for (i=0; i<INFOLEAF_SIZE; i++) {
4421 if (lp->chipset == infoleaf_array[i].chipset) break;
4422 }
4423 if (i == INFOLEAF_SIZE) {
4424 lp->useSROM = FALSE;
4425 printk("%s: Cannot find correct chipset for SROM decoding!\n",
4426 dev->name);
4427 return -ENXIO;
4428 }
4429
4430 lp->infoleaf_fn = infoleaf_array[i].fn;
4431
4432 /* Find the information offset that this function should use */
4433 count = *((u_char *)&lp->srom + 19);
4434 p = (u_char *)&lp->srom + 26;
4435
4436 if (count > 1) {
4437 for (i=count; i; --i, p+=3) {
4438 if (lp->device == *p) break;
4439 }
4440 if (i == 0) {
4441 lp->useSROM = FALSE;
4442 printk("%s: Cannot find correct PCI device [%d] for SROM decoding!\n",
4443 dev->name, lp->device);
4444 return -ENXIO;
4445 }
4446 }
4447
4448 lp->infoleaf_offset = TWIDDLE(p+1);
4449
4450 return 0;
4451 }
4452
4453 /*
4454 ** This routine loads any type 1 or 3 MII info into the mii device
4455 ** struct and executes any type 5 code to reset PHY devices for this
4456 ** controller.
4457 ** The info for the MII devices will be valid since the index used
4458 ** will follow the discovery process from MII address 1-31 then 0.
4459 */
4460 static void
srom_init(struct net_device * dev)4461 srom_init(struct net_device *dev)
4462 {
4463 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
4464 u_char *p = (u_char *)&lp->srom + lp->infoleaf_offset;
4465 u_char count;
4466
4467 p+=2;
4468 if (lp->chipset == DC21140) {
4469 lp->cache.gepc = (*p++ | GEP_CTRL);
4470 gep_wr(lp->cache.gepc, dev);
4471 }
4472
4473 /* Block count */
4474 count = *p++;
4475
4476 /* Jump the infoblocks to find types */
4477 for (;count; --count) {
4478 if (*p < 128) {
4479 p += COMPACT_LEN;
4480 } else if (*(p+1) == 5) {
4481 type5_infoblock(dev, 1, p);
4482 p += ((*p & BLOCK_LEN) + 1);
4483 } else if (*(p+1) == 4) {
4484 p += ((*p & BLOCK_LEN) + 1);
4485 } else if (*(p+1) == 3) {
4486 type3_infoblock(dev, 1, p);
4487 p += ((*p & BLOCK_LEN) + 1);
4488 } else if (*(p+1) == 2) {
4489 p += ((*p & BLOCK_LEN) + 1);
4490 } else if (*(p+1) == 1) {
4491 type1_infoblock(dev, 1, p);
4492 p += ((*p & BLOCK_LEN) + 1);
4493 } else {
4494 p += ((*p & BLOCK_LEN) + 1);
4495 }
4496 }
4497
4498 return;
4499 }
4500
4501 /*
4502 ** A generic routine that writes GEP control, data and reset information
4503 ** to the GEP register (21140) or csr15 GEP portion (2114[23]).
4504 */
4505 static void
srom_exec(struct net_device * dev,u_char * p)4506 srom_exec(struct net_device *dev, u_char *p)
4507 {
4508 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
4509 u_long iobase = dev->base_addr;
4510 u_char count = (p ? *p++ : 0);
4511 u_short *w = (u_short *)p;
4512
4513 if (((lp->ibn != 1) && (lp->ibn != 3) && (lp->ibn != 5)) || !count) return;
4514
4515 if (lp->chipset != DC21140) RESET_SIA;
4516
4517 while (count--) {
4518 gep_wr(((lp->chipset==DC21140) && (lp->ibn!=5) ?
4519 *p++ : TWIDDLE(w++)), dev);
4520 mdelay(2); /* 2ms per action */
4521 }
4522
4523 if (lp->chipset != DC21140) {
4524 outl(lp->cache.csr14, DE4X5_STRR);
4525 outl(lp->cache.csr13, DE4X5_SICR);
4526 }
4527
4528 return;
4529 }
4530
4531 /*
4532 ** Basically this function is a NOP since it will never be called,
4533 ** unless I implement the DC21041 SROM functions. There's no need
4534 ** since the existing code will be satisfactory for all boards.
4535 */
4536 static int
dc21041_infoleaf(struct net_device * dev)4537 dc21041_infoleaf(struct net_device *dev)
4538 {
4539 return DE4X5_AUTOSENSE_MS;
4540 }
4541
4542 static int
dc21140_infoleaf(struct net_device * dev)4543 dc21140_infoleaf(struct net_device *dev)
4544 {
4545 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
4546 u_char count = 0;
4547 u_char *p = (u_char *)&lp->srom + lp->infoleaf_offset;
4548 int next_tick = DE4X5_AUTOSENSE_MS;
4549
4550 /* Read the connection type */
4551 p+=2;
4552
4553 /* GEP control */
4554 lp->cache.gepc = (*p++ | GEP_CTRL);
4555
4556 /* Block count */
4557 count = *p++;
4558
4559 /* Recursively figure out the info blocks */
4560 if (*p < 128) {
4561 next_tick = dc_infoblock[COMPACT](dev, count, p);
4562 } else {
4563 next_tick = dc_infoblock[*(p+1)](dev, count, p);
4564 }
4565
4566 if (lp->tcount == count) {
4567 lp->media = NC;
4568 if (lp->media != lp->c_media) {
4569 de4x5_dbg_media(dev);
4570 lp->c_media = lp->media;
4571 }
4572 lp->media = INIT;
4573 lp->tcount = 0;
4574 lp->tx_enable = FALSE;
4575 }
4576
4577 return next_tick & ~TIMER_CB;
4578 }
4579
4580 static int
dc21142_infoleaf(struct net_device * dev)4581 dc21142_infoleaf(struct net_device *dev)
4582 {
4583 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
4584 u_char count = 0;
4585 u_char *p = (u_char *)&lp->srom + lp->infoleaf_offset;
4586 int next_tick = DE4X5_AUTOSENSE_MS;
4587
4588 /* Read the connection type */
4589 p+=2;
4590
4591 /* Block count */
4592 count = *p++;
4593
4594 /* Recursively figure out the info blocks */
4595 if (*p < 128) {
4596 next_tick = dc_infoblock[COMPACT](dev, count, p);
4597 } else {
4598 next_tick = dc_infoblock[*(p+1)](dev, count, p);
4599 }
4600
4601 if (lp->tcount == count) {
4602 lp->media = NC;
4603 if (lp->media != lp->c_media) {
4604 de4x5_dbg_media(dev);
4605 lp->c_media = lp->media;
4606 }
4607 lp->media = INIT;
4608 lp->tcount = 0;
4609 lp->tx_enable = FALSE;
4610 }
4611
4612 return next_tick & ~TIMER_CB;
4613 }
4614
4615 static int
dc21143_infoleaf(struct net_device * dev)4616 dc21143_infoleaf(struct net_device *dev)
4617 {
4618 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
4619 u_char count = 0;
4620 u_char *p = (u_char *)&lp->srom + lp->infoleaf_offset;
4621 int next_tick = DE4X5_AUTOSENSE_MS;
4622
4623 /* Read the connection type */
4624 p+=2;
4625
4626 /* Block count */
4627 count = *p++;
4628
4629 /* Recursively figure out the info blocks */
4630 if (*p < 128) {
4631 next_tick = dc_infoblock[COMPACT](dev, count, p);
4632 } else {
4633 next_tick = dc_infoblock[*(p+1)](dev, count, p);
4634 }
4635 if (lp->tcount == count) {
4636 lp->media = NC;
4637 if (lp->media != lp->c_media) {
4638 de4x5_dbg_media(dev);
4639 lp->c_media = lp->media;
4640 }
4641 lp->media = INIT;
4642 lp->tcount = 0;
4643 lp->tx_enable = FALSE;
4644 }
4645
4646 return next_tick & ~TIMER_CB;
4647 }
4648
4649 /*
4650 ** The compact infoblock is only designed for DC21140[A] chips, so
4651 ** we'll reuse the dc21140m_autoconf function. Non MII media only.
4652 */
4653 static int
compact_infoblock(struct net_device * dev,u_char count,u_char * p)4654 compact_infoblock(struct net_device *dev, u_char count, u_char *p)
4655 {
4656 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
4657 u_char flags, csr6;
4658
4659 /* Recursively figure out the info blocks */
4660 if (--count > lp->tcount) {
4661 if (*(p+COMPACT_LEN) < 128) {
4662 return dc_infoblock[COMPACT](dev, count, p+COMPACT_LEN);
4663 } else {
4664 return dc_infoblock[*(p+COMPACT_LEN+1)](dev, count, p+COMPACT_LEN);
4665 }
4666 }
4667
4668 if ((lp->media == INIT) && (lp->timeout < 0)) {
4669 lp->ibn = COMPACT;
4670 lp->active = 0;
4671 gep_wr(lp->cache.gepc, dev);
4672 lp->infoblock_media = (*p++) & COMPACT_MC;
4673 lp->cache.gep = *p++;
4674 csr6 = *p++;
4675 flags = *p++;
4676
4677 lp->asBitValid = (flags & 0x80) ? 0 : -1;
4678 lp->defMedium = (flags & 0x40) ? -1 : 0;
4679 lp->asBit = 1 << ((csr6 >> 1) & 0x07);
4680 lp->asPolarity = ((csr6 & 0x80) ? -1 : 0) & lp->asBit;
4681 lp->infoblock_csr6 = OMR_DEF | ((csr6 & 0x71) << 18);
4682 lp->useMII = FALSE;
4683
4684 de4x5_switch_mac_port(dev);
4685 }
4686
4687 return dc21140m_autoconf(dev);
4688 }
4689
4690 /*
4691 ** This block describes non MII media for the DC21140[A] only.
4692 */
4693 static int
type0_infoblock(struct net_device * dev,u_char count,u_char * p)4694 type0_infoblock(struct net_device *dev, u_char count, u_char *p)
4695 {
4696 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
4697 u_char flags, csr6, len = (*p & BLOCK_LEN)+1;
4698
4699 /* Recursively figure out the info blocks */
4700 if (--count > lp->tcount) {
4701 if (*(p+len) < 128) {
4702 return dc_infoblock[COMPACT](dev, count, p+len);
4703 } else {
4704 return dc_infoblock[*(p+len+1)](dev, count, p+len);
4705 }
4706 }
4707
4708 if ((lp->media == INIT) && (lp->timeout < 0)) {
4709 lp->ibn = 0;
4710 lp->active = 0;
4711 gep_wr(lp->cache.gepc, dev);
4712 p+=2;
4713 lp->infoblock_media = (*p++) & BLOCK0_MC;
4714 lp->cache.gep = *p++;
4715 csr6 = *p++;
4716 flags = *p++;
4717
4718 lp->asBitValid = (flags & 0x80) ? 0 : -1;
4719 lp->defMedium = (flags & 0x40) ? -1 : 0;
4720 lp->asBit = 1 << ((csr6 >> 1) & 0x07);
4721 lp->asPolarity = ((csr6 & 0x80) ? -1 : 0) & lp->asBit;
4722 lp->infoblock_csr6 = OMR_DEF | ((csr6 & 0x71) << 18);
4723 lp->useMII = FALSE;
4724
4725 de4x5_switch_mac_port(dev);
4726 }
4727
4728 return dc21140m_autoconf(dev);
4729 }
4730
4731 /* These functions are under construction! */
4732
4733 static int
type1_infoblock(struct net_device * dev,u_char count,u_char * p)4734 type1_infoblock(struct net_device *dev, u_char count, u_char *p)
4735 {
4736 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
4737 u_char len = (*p & BLOCK_LEN)+1;
4738
4739 /* Recursively figure out the info blocks */
4740 if (--count > lp->tcount) {
4741 if (*(p+len) < 128) {
4742 return dc_infoblock[COMPACT](dev, count, p+len);
4743 } else {
4744 return dc_infoblock[*(p+len+1)](dev, count, p+len);
4745 }
4746 }
4747
4748 p += 2;
4749 if (lp->state == INITIALISED) {
4750 lp->ibn = 1;
4751 lp->active = *p++;
4752 lp->phy[lp->active].gep = (*p ? p : 0); p += (*p + 1);
4753 lp->phy[lp->active].rst = (*p ? p : 0); p += (*p + 1);
4754 lp->phy[lp->active].mc = TWIDDLE(p); p += 2;
4755 lp->phy[lp->active].ana = TWIDDLE(p); p += 2;
4756 lp->phy[lp->active].fdx = TWIDDLE(p); p += 2;
4757 lp->phy[lp->active].ttm = TWIDDLE(p);
4758 return 0;
4759 } else if ((lp->media == INIT) && (lp->timeout < 0)) {
4760 lp->ibn = 1;
4761 lp->active = *p;
4762 lp->infoblock_csr6 = OMR_MII_100;
4763 lp->useMII = TRUE;
4764 lp->infoblock_media = ANS;
4765
4766 de4x5_switch_mac_port(dev);
4767 }
4768
4769 return dc21140m_autoconf(dev);
4770 }
4771
4772 static int
type2_infoblock(struct net_device * dev,u_char count,u_char * p)4773 type2_infoblock(struct net_device *dev, u_char count, u_char *p)
4774 {
4775 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
4776 u_char len = (*p & BLOCK_LEN)+1;
4777
4778 /* Recursively figure out the info blocks */
4779 if (--count > lp->tcount) {
4780 if (*(p+len) < 128) {
4781 return dc_infoblock[COMPACT](dev, count, p+len);
4782 } else {
4783 return dc_infoblock[*(p+len+1)](dev, count, p+len);
4784 }
4785 }
4786
4787 if ((lp->media == INIT) && (lp->timeout < 0)) {
4788 lp->ibn = 2;
4789 lp->active = 0;
4790 p += 2;
4791 lp->infoblock_media = (*p) & MEDIA_CODE;
4792
4793 if ((*p++) & EXT_FIELD) {
4794 lp->cache.csr13 = TWIDDLE(p); p += 2;
4795 lp->cache.csr14 = TWIDDLE(p); p += 2;
4796 lp->cache.csr15 = TWIDDLE(p); p += 2;
4797 } else {
4798 lp->cache.csr13 = CSR13;
4799 lp->cache.csr14 = CSR14;
4800 lp->cache.csr15 = CSR15;
4801 }
4802 lp->cache.gepc = ((s32)(TWIDDLE(p)) << 16); p += 2;
4803 lp->cache.gep = ((s32)(TWIDDLE(p)) << 16);
4804 lp->infoblock_csr6 = OMR_SIA;
4805 lp->useMII = FALSE;
4806
4807 de4x5_switch_mac_port(dev);
4808 }
4809
4810 return dc2114x_autoconf(dev);
4811 }
4812
4813 static int
type3_infoblock(struct net_device * dev,u_char count,u_char * p)4814 type3_infoblock(struct net_device *dev, u_char count, u_char *p)
4815 {
4816 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
4817 u_char len = (*p & BLOCK_LEN)+1;
4818
4819 /* Recursively figure out the info blocks */
4820 if (--count > lp->tcount) {
4821 if (*(p+len) < 128) {
4822 return dc_infoblock[COMPACT](dev, count, p+len);
4823 } else {
4824 return dc_infoblock[*(p+len+1)](dev, count, p+len);
4825 }
4826 }
4827
4828 p += 2;
4829 if (lp->state == INITIALISED) {
4830 lp->ibn = 3;
4831 lp->active = *p++;
4832 if (MOTO_SROM_BUG) lp->active = 0;
4833 lp->phy[lp->active].gep = (*p ? p : 0); p += (2 * (*p) + 1);
4834 lp->phy[lp->active].rst = (*p ? p : 0); p += (2 * (*p) + 1);
4835 lp->phy[lp->active].mc = TWIDDLE(p); p += 2;
4836 lp->phy[lp->active].ana = TWIDDLE(p); p += 2;
4837 lp->phy[lp->active].fdx = TWIDDLE(p); p += 2;
4838 lp->phy[lp->active].ttm = TWIDDLE(p); p += 2;
4839 lp->phy[lp->active].mci = *p;
4840 return 0;
4841 } else if ((lp->media == INIT) && (lp->timeout < 0)) {
4842 lp->ibn = 3;
4843 lp->active = *p;
4844 if (MOTO_SROM_BUG) lp->active = 0;
4845 lp->infoblock_csr6 = OMR_MII_100;
4846 lp->useMII = TRUE;
4847 lp->infoblock_media = ANS;
4848
4849 de4x5_switch_mac_port(dev);
4850 }
4851
4852 return dc2114x_autoconf(dev);
4853 }
4854
4855 static int
type4_infoblock(struct net_device * dev,u_char count,u_char * p)4856 type4_infoblock(struct net_device *dev, u_char count, u_char *p)
4857 {
4858 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
4859 u_char flags, csr6, len = (*p & BLOCK_LEN)+1;
4860
4861 /* Recursively figure out the info blocks */
4862 if (--count > lp->tcount) {
4863 if (*(p+len) < 128) {
4864 return dc_infoblock[COMPACT](dev, count, p+len);
4865 } else {
4866 return dc_infoblock[*(p+len+1)](dev, count, p+len);
4867 }
4868 }
4869
4870 if ((lp->media == INIT) && (lp->timeout < 0)) {
4871 lp->ibn = 4;
4872 lp->active = 0;
4873 p+=2;
4874 lp->infoblock_media = (*p++) & MEDIA_CODE;
4875 lp->cache.csr13 = CSR13; /* Hard coded defaults */
4876 lp->cache.csr14 = CSR14;
4877 lp->cache.csr15 = CSR15;
4878 lp->cache.gepc = ((s32)(TWIDDLE(p)) << 16); p += 2;
4879 lp->cache.gep = ((s32)(TWIDDLE(p)) << 16); p += 2;
4880 csr6 = *p++;
4881 flags = *p++;
4882
4883 lp->asBitValid = (flags & 0x80) ? 0 : -1;
4884 lp->defMedium = (flags & 0x40) ? -1 : 0;
4885 lp->asBit = 1 << ((csr6 >> 1) & 0x07);
4886 lp->asPolarity = ((csr6 & 0x80) ? -1 : 0) & lp->asBit;
4887 lp->infoblock_csr6 = OMR_DEF | ((csr6 & 0x71) << 18);
4888 lp->useMII = FALSE;
4889
4890 de4x5_switch_mac_port(dev);
4891 }
4892
4893 return dc2114x_autoconf(dev);
4894 }
4895
4896 /*
4897 ** This block type provides information for resetting external devices
4898 ** (chips) through the General Purpose Register.
4899 */
4900 static int
type5_infoblock(struct net_device * dev,u_char count,u_char * p)4901 type5_infoblock(struct net_device *dev, u_char count, u_char *p)
4902 {
4903 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
4904 u_char len = (*p & BLOCK_LEN)+1;
4905
4906 /* Recursively figure out the info blocks */
4907 if (--count > lp->tcount) {
4908 if (*(p+len) < 128) {
4909 return dc_infoblock[COMPACT](dev, count, p+len);
4910 } else {
4911 return dc_infoblock[*(p+len+1)](dev, count, p+len);
4912 }
4913 }
4914
4915 /* Must be initializing to run this code */
4916 if ((lp->state == INITIALISED) || (lp->media == INIT)) {
4917 p+=2;
4918 lp->rst = p;
4919 srom_exec(dev, lp->rst);
4920 }
4921
4922 return DE4X5_AUTOSENSE_MS;
4923 }
4924
4925 /*
4926 ** MII Read/Write
4927 */
4928
4929 static int
mii_rd(u_char phyreg,u_char phyaddr,u_long ioaddr)4930 mii_rd(u_char phyreg, u_char phyaddr, u_long ioaddr)
4931 {
4932 mii_wdata(MII_PREAMBLE, 2, ioaddr); /* Start of 34 bit preamble... */
4933 mii_wdata(MII_PREAMBLE, 32, ioaddr); /* ...continued */
4934 mii_wdata(MII_STRD, 4, ioaddr); /* SFD and Read operation */
4935 mii_address(phyaddr, ioaddr); /* PHY address to be accessed */
4936 mii_address(phyreg, ioaddr); /* PHY Register to read */
4937 mii_ta(MII_STRD, ioaddr); /* Turn around time - 2 MDC */
4938
4939 return mii_rdata(ioaddr); /* Read data */
4940 }
4941
4942 static void
mii_wr(int data,u_char phyreg,u_char phyaddr,u_long ioaddr)4943 mii_wr(int data, u_char phyreg, u_char phyaddr, u_long ioaddr)
4944 {
4945 mii_wdata(MII_PREAMBLE, 2, ioaddr); /* Start of 34 bit preamble... */
4946 mii_wdata(MII_PREAMBLE, 32, ioaddr); /* ...continued */
4947 mii_wdata(MII_STWR, 4, ioaddr); /* SFD and Write operation */
4948 mii_address(phyaddr, ioaddr); /* PHY address to be accessed */
4949 mii_address(phyreg, ioaddr); /* PHY Register to write */
4950 mii_ta(MII_STWR, ioaddr); /* Turn around time - 2 MDC */
4951 data = mii_swap(data, 16); /* Swap data bit ordering */
4952 mii_wdata(data, 16, ioaddr); /* Write data */
4953
4954 return;
4955 }
4956
4957 static int
mii_rdata(u_long ioaddr)4958 mii_rdata(u_long ioaddr)
4959 {
4960 int i;
4961 s32 tmp = 0;
4962
4963 for (i=0; i<16; i++) {
4964 tmp <<= 1;
4965 tmp |= getfrom_mii(MII_MRD | MII_RD, ioaddr);
4966 }
4967
4968 return tmp;
4969 }
4970
4971 static void
mii_wdata(int data,int len,u_long ioaddr)4972 mii_wdata(int data, int len, u_long ioaddr)
4973 {
4974 int i;
4975
4976 for (i=0; i<len; i++) {
4977 sendto_mii(MII_MWR | MII_WR, data, ioaddr);
4978 data >>= 1;
4979 }
4980
4981 return;
4982 }
4983
4984 static void
mii_address(u_char addr,u_long ioaddr)4985 mii_address(u_char addr, u_long ioaddr)
4986 {
4987 int i;
4988
4989 addr = mii_swap(addr, 5);
4990 for (i=0; i<5; i++) {
4991 sendto_mii(MII_MWR | MII_WR, addr, ioaddr);
4992 addr >>= 1;
4993 }
4994
4995 return;
4996 }
4997
4998 static void
mii_ta(u_long rw,u_long ioaddr)4999 mii_ta(u_long rw, u_long ioaddr)
5000 {
5001 if (rw == MII_STWR) {
5002 sendto_mii(MII_MWR | MII_WR, 1, ioaddr);
5003 sendto_mii(MII_MWR | MII_WR, 0, ioaddr);
5004 } else {
5005 getfrom_mii(MII_MRD | MII_RD, ioaddr); /* Tri-state MDIO */
5006 }
5007
5008 return;
5009 }
5010
5011 static int
mii_swap(int data,int len)5012 mii_swap(int data, int len)
5013 {
5014 int i, tmp = 0;
5015
5016 for (i=0; i<len; i++) {
5017 tmp <<= 1;
5018 tmp |= (data & 1);
5019 data >>= 1;
5020 }
5021
5022 return tmp;
5023 }
5024
5025 static void
sendto_mii(u32 command,int data,u_long ioaddr)5026 sendto_mii(u32 command, int data, u_long ioaddr)
5027 {
5028 u32 j;
5029
5030 j = (data & 1) << 17;
5031 outl(command | j, ioaddr);
5032 udelay(1);
5033 outl(command | MII_MDC | j, ioaddr);
5034 udelay(1);
5035
5036 return;
5037 }
5038
5039 static int
getfrom_mii(u32 command,u_long ioaddr)5040 getfrom_mii(u32 command, u_long ioaddr)
5041 {
5042 outl(command, ioaddr);
5043 udelay(1);
5044 outl(command | MII_MDC, ioaddr);
5045 udelay(1);
5046
5047 return ((inl(ioaddr) >> 19) & 1);
5048 }
5049
5050 /*
5051 ** Here's 3 ways to calculate the OUI from the ID registers.
5052 */
5053 static int
mii_get_oui(u_char phyaddr,u_long ioaddr)5054 mii_get_oui(u_char phyaddr, u_long ioaddr)
5055 {
5056 /*
5057 union {
5058 u_short reg;
5059 u_char breg[2];
5060 } a;
5061 int i, r2, r3, ret=0;*/
5062 int r2, r3;
5063
5064 /* Read r2 and r3 */
5065 r2 = mii_rd(MII_ID0, phyaddr, ioaddr);
5066 r3 = mii_rd(MII_ID1, phyaddr, ioaddr);
5067 /* SEEQ and Cypress way * /
5068 / * Shuffle r2 and r3 * /
5069 a.reg=0;
5070 r3 = ((r3>>10)|(r2<<6))&0x0ff;
5071 r2 = ((r2>>2)&0x3fff);
5072
5073 / * Bit reverse r3 * /
5074 for (i=0;i<8;i++) {
5075 ret<<=1;
5076 ret |= (r3&1);
5077 r3>>=1;
5078 }
5079
5080 / * Bit reverse r2 * /
5081 for (i=0;i<16;i++) {
5082 a.reg<<=1;
5083 a.reg |= (r2&1);
5084 r2>>=1;
5085 }
5086
5087 / * Swap r2 bytes * /
5088 i=a.breg[0];
5089 a.breg[0]=a.breg[1];
5090 a.breg[1]=i;
5091
5092 return ((a.reg<<8)|ret); */ /* SEEQ and Cypress way */
5093 /* return ((r2<<6)|(u_int)(r3>>10)); */ /* NATIONAL and BROADCOM way */
5094 return r2; /* (I did it) My way */
5095 }
5096
5097 /*
5098 ** The SROM spec forces us to search addresses [1-31 0]. Bummer.
5099 */
5100 static int
mii_get_phy(struct net_device * dev)5101 mii_get_phy(struct net_device *dev)
5102 {
5103 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
5104 u_long iobase = dev->base_addr;
5105 int i, j, k, n, limit=sizeof(phy_info)/sizeof(struct phy_table);
5106 int id;
5107
5108 lp->active = 0;
5109 lp->useMII = TRUE;
5110
5111 /* Search the MII address space for possible PHY devices */
5112 for (n=0, lp->mii_cnt=0, i=1; !((i==1) && (n==1)); i=(i+1)%DE4X5_MAX_MII) {
5113 lp->phy[lp->active].addr = i;
5114 if (i==0) n++; /* Count cycles */
5115 while (de4x5_reset_phy(dev)<0) udelay(100);/* Wait for reset */
5116 id = mii_get_oui(i, DE4X5_MII);
5117 if ((id == 0) || (id == 65535)) continue; /* Valid ID? */
5118 for (j=0; j<limit; j++) { /* Search PHY table */
5119 if (id != phy_info[j].id) continue; /* ID match? */
5120 for (k=0; lp->phy[k].id && (k < DE4X5_MAX_PHY); k++);
5121 if (k < DE4X5_MAX_PHY) {
5122 memcpy((char *)&lp->phy[k],
5123 (char *)&phy_info[j], sizeof(struct phy_table));
5124 lp->phy[k].addr = i;
5125 lp->mii_cnt++;
5126 lp->active++;
5127 } else {
5128 goto purgatory; /* Stop the search */
5129 }
5130 break;
5131 }
5132 if ((j == limit) && (i < DE4X5_MAX_MII)) {
5133 for (k=0; lp->phy[k].id && (k < DE4X5_MAX_PHY); k++);
5134 lp->phy[k].addr = i;
5135 lp->phy[k].id = id;
5136 lp->phy[k].spd.reg = GENERIC_REG; /* ANLPA register */
5137 lp->phy[k].spd.mask = GENERIC_MASK; /* 100Mb/s technologies */
5138 lp->phy[k].spd.value = GENERIC_VALUE; /* TX & T4, H/F Duplex */
5139 lp->mii_cnt++;
5140 lp->active++;
5141 printk("%s: Using generic MII device control. If the board doesn't operate, \nplease mail the following dump to the author:\n", dev->name);
5142 j = de4x5_debug;
5143 de4x5_debug |= DEBUG_MII;
5144 de4x5_dbg_mii(dev, k);
5145 de4x5_debug = j;
5146 printk("\n");
5147 }
5148 }
5149 purgatory:
5150 lp->active = 0;
5151 if (lp->phy[0].id) { /* Reset the PHY devices */
5152 for (k=0; lp->phy[k].id && (k < DE4X5_MAX_PHY); k++) { /*For each PHY*/
5153 mii_wr(MII_CR_RST, MII_CR, lp->phy[k].addr, DE4X5_MII);
5154 while (mii_rd(MII_CR, lp->phy[k].addr, DE4X5_MII) & MII_CR_RST);
5155
5156 de4x5_dbg_mii(dev, k);
5157 }
5158 }
5159 if (!lp->mii_cnt) lp->useMII = FALSE;
5160
5161 return lp->mii_cnt;
5162 }
5163
5164 static char *
build_setup_frame(struct net_device * dev,int mode)5165 build_setup_frame(struct net_device *dev, int mode)
5166 {
5167 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
5168 int i;
5169 char *pa = lp->setup_frame;
5170
5171 /* Initialise the setup frame */
5172 if (mode == ALL) {
5173 memset(lp->setup_frame, 0, SETUP_FRAME_LEN);
5174 }
5175
5176 if (lp->setup_f == HASH_PERF) {
5177 for (pa=lp->setup_frame+IMPERF_PA_OFFSET, i=0; i<ETH_ALEN; i++) {
5178 *(pa + i) = dev->dev_addr[i]; /* Host address */
5179 if (i & 0x01) pa += 2;
5180 }
5181 *(lp->setup_frame + (HASH_TABLE_LEN >> 3) - 3) = 0x80;
5182 } else {
5183 for (i=0; i<ETH_ALEN; i++) { /* Host address */
5184 *(pa + (i&1)) = dev->dev_addr[i];
5185 if (i & 0x01) pa += 4;
5186 }
5187 for (i=0; i<ETH_ALEN; i++) { /* Broadcast address */
5188 *(pa + (i&1)) = (char) 0xff;
5189 if (i & 0x01) pa += 4;
5190 }
5191 }
5192
5193 return pa; /* Points to the next entry */
5194 }
5195
5196 static void
enable_ast(struct net_device * dev,u32 time_out)5197 enable_ast(struct net_device *dev, u32 time_out)
5198 {
5199 timeout(dev, (void *)&de4x5_ast, (u_long)dev, time_out);
5200
5201 return;
5202 }
5203
5204 static void
disable_ast(struct net_device * dev)5205 disable_ast(struct net_device *dev)
5206 {
5207 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
5208
5209 del_timer(&lp->timer);
5210
5211 return;
5212 }
5213
5214 static long
de4x5_switch_mac_port(struct net_device * dev)5215 de4x5_switch_mac_port(struct net_device *dev)
5216 {
5217 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
5218 u_long iobase = dev->base_addr;
5219 s32 omr;
5220
5221 STOP_DE4X5;
5222
5223 /* Assert the OMR_PS bit in CSR6 */
5224 omr = (inl(DE4X5_OMR) & ~(OMR_PS | OMR_HBD | OMR_TTM | OMR_PCS | OMR_SCR |
5225 OMR_FDX));
5226 omr |= lp->infoblock_csr6;
5227 if (omr & OMR_PS) omr |= OMR_HBD;
5228 outl(omr, DE4X5_OMR);
5229
5230 /* Soft Reset */
5231 RESET_DE4X5;
5232
5233 /* Restore the GEP - especially for COMPACT and Type 0 Infoblocks */
5234 if (lp->chipset == DC21140) {
5235 gep_wr(lp->cache.gepc, dev);
5236 gep_wr(lp->cache.gep, dev);
5237 } else if ((lp->chipset & ~0x0ff) == DC2114x) {
5238 reset_init_sia(dev, lp->cache.csr13, lp->cache.csr14, lp->cache.csr15);
5239 }
5240
5241 /* Restore CSR6 */
5242 outl(omr, DE4X5_OMR);
5243
5244 /* Reset CSR8 */
5245 inl(DE4X5_MFC);
5246
5247 return omr;
5248 }
5249
5250 static void
gep_wr(s32 data,struct net_device * dev)5251 gep_wr(s32 data, struct net_device *dev)
5252 {
5253 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
5254 u_long iobase = dev->base_addr;
5255
5256 if (lp->chipset == DC21140) {
5257 outl(data, DE4X5_GEP);
5258 } else if ((lp->chipset & ~0x00ff) == DC2114x) {
5259 outl((data<<16) | lp->cache.csr15, DE4X5_SIGR);
5260 }
5261
5262 return;
5263 }
5264
5265 static int
gep_rd(struct net_device * dev)5266 gep_rd(struct net_device *dev)
5267 {
5268 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
5269 u_long iobase = dev->base_addr;
5270
5271 if (lp->chipset == DC21140) {
5272 return inl(DE4X5_GEP);
5273 } else if ((lp->chipset & ~0x00ff) == DC2114x) {
5274 return (inl(DE4X5_SIGR) & 0x000fffff);
5275 }
5276
5277 return 0;
5278 }
5279
5280 static void
timeout(struct net_device * dev,void (* fn)(u_long data),u_long data,u_long msec)5281 timeout(struct net_device *dev, void (*fn)(u_long data), u_long data, u_long msec)
5282 {
5283 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
5284 int dt;
5285
5286 /* First, cancel any pending timer events */
5287 del_timer(&lp->timer);
5288
5289 /* Convert msec to ticks */
5290 dt = (msec * HZ) / 1000;
5291 if (dt==0) dt=1;
5292
5293 /* Set up timer */
5294 lp->timer.expires = jiffies + dt;
5295 lp->timer.function = fn;
5296 lp->timer.data = data;
5297 add_timer(&lp->timer);
5298
5299 return;
5300 }
5301
5302 static void
yawn(struct net_device * dev,int state)5303 yawn(struct net_device *dev, int state)
5304 {
5305 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
5306 u_long iobase = dev->base_addr;
5307
5308 if ((lp->chipset == DC21040) || (lp->chipset == DC21140)) return;
5309
5310 if(lp->bus == EISA) {
5311 switch(state) {
5312 case WAKEUP:
5313 outb(WAKEUP, PCI_CFPM);
5314 mdelay(10);
5315 break;
5316
5317 case SNOOZE:
5318 outb(SNOOZE, PCI_CFPM);
5319 break;
5320
5321 case SLEEP:
5322 outl(0, DE4X5_SICR);
5323 outb(SLEEP, PCI_CFPM);
5324 break;
5325 }
5326 } else {
5327 switch(state) {
5328 case WAKEUP:
5329 pcibios_write_config_byte(lp->bus_num, lp->device << 3,
5330 PCI_CFDA_PSM, WAKEUP);
5331 mdelay(10);
5332 break;
5333
5334 case SNOOZE:
5335 pcibios_write_config_byte(lp->bus_num, lp->device << 3,
5336 PCI_CFDA_PSM, SNOOZE);
5337 break;
5338
5339 case SLEEP:
5340 outl(0, DE4X5_SICR);
5341 pcibios_write_config_byte(lp->bus_num, lp->device << 3,
5342 PCI_CFDA_PSM, SLEEP);
5343 break;
5344 }
5345 }
5346
5347 return;
5348 }
5349
5350 static void
de4x5_parse_params(struct net_device * dev)5351 de4x5_parse_params(struct net_device *dev)
5352 {
5353 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
5354 char *p, *q, t;
5355
5356 lp->params.fdx = 0;
5357 lp->params.autosense = AUTO;
5358
5359 if (args == NULL) return;
5360
5361 if ((p = strstr(args, dev->name))) {
5362 if (!(q = strstr(p+strlen(dev->name), "eth"))) q = p + strlen(p);
5363 t = *q;
5364 *q = '\0';
5365
5366 #ifdef CONFIG_EISA
5367 if (strstr(p, "force_eisa") || strstr(p, "FORCE_EISA")) forceEISA = 1;
5368 #endif
5369 if (strstr(p, "fdx") || strstr(p, "FDX")) lp->params.fdx = 1;
5370
5371 if (strstr(p, "autosense") || strstr(p, "AUTOSENSE")) {
5372 if (strstr(p, "TP")) {
5373 lp->params.autosense = TP;
5374 } else if (strstr(p, "TP_NW")) {
5375 lp->params.autosense = TP_NW;
5376 } else if (strstr(p, "BNC")) {
5377 lp->params.autosense = BNC;
5378 } else if (strstr(p, "AUI")) {
5379 lp->params.autosense = AUI;
5380 } else if (strstr(p, "BNC_AUI")) {
5381 lp->params.autosense = BNC;
5382 } else if (strstr(p, "10Mb")) {
5383 lp->params.autosense = _10Mb;
5384 } else if (strstr(p, "100Mb")) {
5385 lp->params.autosense = _100Mb;
5386 } else if (strstr(p, "AUTO")) {
5387 lp->params.autosense = AUTO;
5388 }
5389 }
5390 *q = t;
5391 }
5392
5393 return;
5394 }
5395
5396 static void
de4x5_dbg_open(struct net_device * dev)5397 de4x5_dbg_open(struct net_device *dev)
5398 {
5399 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
5400 int i;
5401
5402 if (de4x5_debug & DEBUG_OPEN) {
5403 printk("%s: de4x5 opening with irq %d\n",dev->name,dev->irq);
5404 printk("\tphysical address: ");
5405 for (i=0;i<6;i++) {
5406 printk("%2.2x:",(short)dev->dev_addr[i]);
5407 }
5408 printk("\n");
5409 printk("Descriptor head addresses:\n");
5410 printk("\t0x%8.8lx 0x%8.8lx\n",(u_long)lp->rx_ring,(u_long)lp->tx_ring);
5411 printk("Descriptor addresses:\nRX: ");
5412 for (i=0;i<lp->rxRingSize-1;i++){
5413 if (i < 3) {
5414 printk("0x%8.8lx ",(u_long)&lp->rx_ring[i].status);
5415 }
5416 }
5417 printk("...0x%8.8lx\n",(u_long)&lp->rx_ring[i].status);
5418 printk("TX: ");
5419 for (i=0;i<lp->txRingSize-1;i++){
5420 if (i < 3) {
5421 printk("0x%8.8lx ", (u_long)&lp->tx_ring[i].status);
5422 }
5423 }
5424 printk("...0x%8.8lx\n", (u_long)&lp->tx_ring[i].status);
5425 printk("Descriptor buffers:\nRX: ");
5426 for (i=0;i<lp->rxRingSize-1;i++){
5427 if (i < 3) {
5428 printk("0x%8.8x ",le32_to_cpu(lp->rx_ring[i].buf));
5429 }
5430 }
5431 printk("...0x%8.8x\n",le32_to_cpu(lp->rx_ring[i].buf));
5432 printk("TX: ");
5433 for (i=0;i<lp->txRingSize-1;i++){
5434 if (i < 3) {
5435 printk("0x%8.8x ", le32_to_cpu(lp->tx_ring[i].buf));
5436 }
5437 }
5438 printk("...0x%8.8x\n", le32_to_cpu(lp->tx_ring[i].buf));
5439 printk("Ring size: \nRX: %d\nTX: %d\n",
5440 (short)lp->rxRingSize,
5441 (short)lp->txRingSize);
5442 }
5443
5444 return;
5445 }
5446
5447 static void
de4x5_dbg_mii(struct net_device * dev,int k)5448 de4x5_dbg_mii(struct net_device *dev, int k)
5449 {
5450 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
5451 u_long iobase = dev->base_addr;
5452
5453 if (de4x5_debug & DEBUG_MII) {
5454 printk("\nMII device address: %d\n", lp->phy[k].addr);
5455 printk("MII CR: %x\n",mii_rd(MII_CR,lp->phy[k].addr,DE4X5_MII));
5456 printk("MII SR: %x\n",mii_rd(MII_SR,lp->phy[k].addr,DE4X5_MII));
5457 printk("MII ID0: %x\n",mii_rd(MII_ID0,lp->phy[k].addr,DE4X5_MII));
5458 printk("MII ID1: %x\n",mii_rd(MII_ID1,lp->phy[k].addr,DE4X5_MII));
5459 if (lp->phy[k].id != BROADCOM_T4) {
5460 printk("MII ANA: %x\n",mii_rd(0x04,lp->phy[k].addr,DE4X5_MII));
5461 printk("MII ANC: %x\n",mii_rd(0x05,lp->phy[k].addr,DE4X5_MII));
5462 }
5463 printk("MII 16: %x\n",mii_rd(0x10,lp->phy[k].addr,DE4X5_MII));
5464 if (lp->phy[k].id != BROADCOM_T4) {
5465 printk("MII 17: %x\n",mii_rd(0x11,lp->phy[k].addr,DE4X5_MII));
5466 printk("MII 18: %x\n",mii_rd(0x12,lp->phy[k].addr,DE4X5_MII));
5467 } else {
5468 printk("MII 20: %x\n",mii_rd(0x14,lp->phy[k].addr,DE4X5_MII));
5469 }
5470 }
5471
5472 return;
5473 }
5474
5475 static void
de4x5_dbg_media(struct net_device * dev)5476 de4x5_dbg_media(struct net_device *dev)
5477 {
5478 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
5479
5480 if (lp->media != lp->c_media) {
5481 if (de4x5_debug & DEBUG_MEDIA) {
5482 printk("%s: media is %s%s\n", dev->name,
5483 (lp->media == NC ? "unconnected, link down or incompatible connection" :
5484 (lp->media == TP ? "TP" :
5485 (lp->media == ANS ? "TP/Nway" :
5486 (lp->media == BNC ? "BNC" :
5487 (lp->media == AUI ? "AUI" :
5488 (lp->media == BNC_AUI ? "BNC/AUI" :
5489 (lp->media == EXT_SIA ? "EXT SIA" :
5490 (lp->media == _100Mb ? "100Mb/s" :
5491 (lp->media == _10Mb ? "10Mb/s" :
5492 "???"
5493 ))))))))), (lp->fdx?" full duplex.":"."));
5494 }
5495 lp->c_media = lp->media;
5496 }
5497
5498 return;
5499 }
5500
5501 static void
de4x5_dbg_srom(struct de4x5_srom * p)5502 de4x5_dbg_srom(struct de4x5_srom *p)
5503 {
5504 int i;
5505
5506 if (de4x5_debug & DEBUG_SROM) {
5507 printk("Sub-system Vendor ID: %04x\n", *((u_short *)p->sub_vendor_id));
5508 printk("Sub-system ID: %04x\n", *((u_short *)p->sub_system_id));
5509 printk("ID Block CRC: %02x\n", (u_char)(p->id_block_crc));
5510 printk("SROM version: %02x\n", (u_char)(p->version));
5511 printk("# controllers: %02x\n", (u_char)(p->num_controllers));
5512
5513 printk("Hardware Address: ");
5514 for (i=0;i<ETH_ALEN-1;i++) {
5515 printk("%02x:", (u_char)*(p->ieee_addr+i));
5516 }
5517 printk("%02x\n", (u_char)*(p->ieee_addr+i));
5518 printk("CRC checksum: %04x\n", (u_short)(p->chksum));
5519 for (i=0; i<64; i++) {
5520 printk("%3d %04x\n", i<<1, (u_short)*((u_short *)p+i));
5521 }
5522 }
5523
5524 return;
5525 }
5526
5527 static void
de4x5_dbg_rx(struct sk_buff * skb,int len)5528 de4x5_dbg_rx(struct sk_buff *skb, int len)
5529 {
5530 int i, j;
5531
5532 if (de4x5_debug & DEBUG_RX) {
5533 printk("R: %02x:%02x:%02x:%02x:%02x:%02x <- %02x:%02x:%02x:%02x:%02x:%02x len/SAP:%02x%02x [%d]\n",
5534 (u_char)skb->data[0],
5535 (u_char)skb->data[1],
5536 (u_char)skb->data[2],
5537 (u_char)skb->data[3],
5538 (u_char)skb->data[4],
5539 (u_char)skb->data[5],
5540 (u_char)skb->data[6],
5541 (u_char)skb->data[7],
5542 (u_char)skb->data[8],
5543 (u_char)skb->data[9],
5544 (u_char)skb->data[10],
5545 (u_char)skb->data[11],
5546 (u_char)skb->data[12],
5547 (u_char)skb->data[13],
5548 len);
5549 for (j=0; len>0;j+=16, len-=16) {
5550 printk(" %03x: ",j);
5551 for (i=0; i<16 && i<len; i++) {
5552 printk("%02x ",(u_char)skb->data[i+j]);
5553 }
5554 printk("\n");
5555 }
5556 }
5557
5558 return;
5559 }
5560
5561 /*
5562 ** Perform IOCTL call functions here. Some are privileged operations and the
5563 ** effective uid is checked in those cases. In the normal course of events
5564 ** this function is only used for my testing.
5565 */
5566 static int
de4x5_ioctl(struct net_device * dev,struct ifreq * rq,int cmd)5567 de4x5_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
5568 {
5569 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
5570 struct de4x5_ioctl *ioc = (struct de4x5_ioctl *) &rq->ifr_data;
5571 u_long iobase = dev->base_addr;
5572 int i, j, status = 0;
5573 s32 omr;
5574 union {
5575 u8 addr[144];
5576 u16 sval[72];
5577 u32 lval[36];
5578 } tmp;
5579 u_long flags = 0;
5580
5581 switch(ioc->cmd) {
5582 case DE4X5_GET_HWADDR: /* Get the hardware address */
5583 ioc->len = ETH_ALEN;
5584 for (i=0; i<ETH_ALEN; i++) {
5585 tmp.addr[i] = dev->dev_addr[i];
5586 }
5587 if (copy_to_user(ioc->data, tmp.addr, ioc->len)) return -EFAULT;
5588 break;
5589
5590 case DE4X5_SET_HWADDR: /* Set the hardware address */
5591 if (!capable(CAP_NET_ADMIN)) return -EPERM;
5592 if (copy_from_user(tmp.addr, ioc->data, ETH_ALEN)) return -EFAULT;
5593 if (netif_queue_stopped(dev))
5594 return -EBUSY;
5595 netif_stop_queue(dev);
5596 for (i=0; i<ETH_ALEN; i++) {
5597 dev->dev_addr[i] = tmp.addr[i];
5598 }
5599 build_setup_frame(dev, PHYS_ADDR_ONLY);
5600 /* Set up the descriptor and give ownership to the card */
5601 load_packet(dev, lp->setup_frame, TD_IC | PERFECT_F | TD_SET |
5602 SETUP_FRAME_LEN, (struct sk_buff *)1);
5603 lp->tx_new = (++lp->tx_new) % lp->txRingSize;
5604 outl(POLL_DEMAND, DE4X5_TPD); /* Start the TX */
5605 netif_wake_queue(dev); /* Unlock the TX ring */
5606 break;
5607
5608 case DE4X5_SET_PROM: /* Set Promiscuous Mode */
5609 if (!capable(CAP_NET_ADMIN)) return -EPERM;
5610 omr = inl(DE4X5_OMR);
5611 omr |= OMR_PR;
5612 outl(omr, DE4X5_OMR);
5613 dev->flags |= IFF_PROMISC;
5614 break;
5615
5616 case DE4X5_CLR_PROM: /* Clear Promiscuous Mode */
5617 if (!capable(CAP_NET_ADMIN)) return -EPERM;
5618 omr = inl(DE4X5_OMR);
5619 omr &= ~OMR_PR;
5620 outl(omr, DE4X5_OMR);
5621 dev->flags &= ~IFF_PROMISC;
5622 break;
5623
5624 case DE4X5_SAY_BOO: /* Say "Boo!" to the kernel log file */
5625 if (!capable(CAP_NET_ADMIN)) return -EPERM;
5626 printk("%s: Boo!\n", dev->name);
5627 break;
5628
5629 case DE4X5_MCA_EN: /* Enable pass all multicast addressing */
5630 if (!capable(CAP_NET_ADMIN)) return -EPERM;
5631 omr = inl(DE4X5_OMR);
5632 omr |= OMR_PM;
5633 outl(omr, DE4X5_OMR);
5634 break;
5635
5636 case DE4X5_GET_STATS: /* Get the driver statistics */
5637 {
5638 struct pkt_stats statbuf;
5639 ioc->len = sizeof(statbuf);
5640 spin_lock_irqsave(&lp->lock, flags);
5641 memcpy(&statbuf, &lp->pktStats, ioc->len);
5642 spin_unlock_irqrestore(&lp->lock, flags);
5643 if (copy_to_user(ioc->data, &statbuf, ioc->len))
5644 return -EFAULT;
5645 break;
5646 }
5647 case DE4X5_CLR_STATS: /* Zero out the driver statistics */
5648 if (!capable(CAP_NET_ADMIN)) return -EPERM;
5649 spin_lock_irqsave(&lp->lock, flags);
5650 memset(&lp->pktStats, 0, sizeof(lp->pktStats));
5651 spin_unlock_irqrestore(&lp->lock, flags);
5652 break;
5653
5654 case DE4X5_GET_OMR: /* Get the OMR Register contents */
5655 tmp.addr[0] = inl(DE4X5_OMR);
5656 if (copy_to_user(ioc->data, tmp.addr, 1)) return -EFAULT;
5657 break;
5658
5659 case DE4X5_SET_OMR: /* Set the OMR Register contents */
5660 if (!capable(CAP_NET_ADMIN)) return -EPERM;
5661 if (copy_from_user(tmp.addr, ioc->data, 1)) return -EFAULT;
5662 outl(tmp.addr[0], DE4X5_OMR);
5663 break;
5664
5665 case DE4X5_GET_REG: /* Get the DE4X5 Registers */
5666 j = 0;
5667 tmp.lval[0] = inl(DE4X5_STS); j+=4;
5668 tmp.lval[1] = inl(DE4X5_BMR); j+=4;
5669 tmp.lval[2] = inl(DE4X5_IMR); j+=4;
5670 tmp.lval[3] = inl(DE4X5_OMR); j+=4;
5671 tmp.lval[4] = inl(DE4X5_SISR); j+=4;
5672 tmp.lval[5] = inl(DE4X5_SICR); j+=4;
5673 tmp.lval[6] = inl(DE4X5_STRR); j+=4;
5674 tmp.lval[7] = inl(DE4X5_SIGR); j+=4;
5675 ioc->len = j;
5676 if (copy_to_user(ioc->data, tmp.addr, ioc->len)) return -EFAULT;
5677 break;
5678
5679 #define DE4X5_DUMP 0x0f /* Dump the DE4X5 Status */
5680 /*
5681 case DE4X5_DUMP:
5682 j = 0;
5683 tmp.addr[j++] = dev->irq;
5684 for (i=0; i<ETH_ALEN; i++) {
5685 tmp.addr[j++] = dev->dev_addr[i];
5686 }
5687 tmp.addr[j++] = lp->rxRingSize;
5688 tmp.lval[j>>2] = (long)lp->rx_ring; j+=4;
5689 tmp.lval[j>>2] = (long)lp->tx_ring; j+=4;
5690
5691 for (i=0;i<lp->rxRingSize-1;i++){
5692 if (i < 3) {
5693 tmp.lval[j>>2] = (long)&lp->rx_ring[i].status; j+=4;
5694 }
5695 }
5696 tmp.lval[j>>2] = (long)&lp->rx_ring[i].status; j+=4;
5697 for (i=0;i<lp->txRingSize-1;i++){
5698 if (i < 3) {
5699 tmp.lval[j>>2] = (long)&lp->tx_ring[i].status; j+=4;
5700 }
5701 }
5702 tmp.lval[j>>2] = (long)&lp->tx_ring[i].status; j+=4;
5703
5704 for (i=0;i<lp->rxRingSize-1;i++){
5705 if (i < 3) {
5706 tmp.lval[j>>2] = (s32)le32_to_cpu(lp->rx_ring[i].buf); j+=4;
5707 }
5708 }
5709 tmp.lval[j>>2] = (s32)le32_to_cpu(lp->rx_ring[i].buf); j+=4;
5710 for (i=0;i<lp->txRingSize-1;i++){
5711 if (i < 3) {
5712 tmp.lval[j>>2] = (s32)le32_to_cpu(lp->tx_ring[i].buf); j+=4;
5713 }
5714 }
5715 tmp.lval[j>>2] = (s32)le32_to_cpu(lp->tx_ring[i].buf); j+=4;
5716
5717 for (i=0;i<lp->rxRingSize;i++){
5718 tmp.lval[j>>2] = le32_to_cpu(lp->rx_ring[i].status); j+=4;
5719 }
5720 for (i=0;i<lp->txRingSize;i++){
5721 tmp.lval[j>>2] = le32_to_cpu(lp->tx_ring[i].status); j+=4;
5722 }
5723
5724 tmp.lval[j>>2] = inl(DE4X5_BMR); j+=4;
5725 tmp.lval[j>>2] = inl(DE4X5_TPD); j+=4;
5726 tmp.lval[j>>2] = inl(DE4X5_RPD); j+=4;
5727 tmp.lval[j>>2] = inl(DE4X5_RRBA); j+=4;
5728 tmp.lval[j>>2] = inl(DE4X5_TRBA); j+=4;
5729 tmp.lval[j>>2] = inl(DE4X5_STS); j+=4;
5730 tmp.lval[j>>2] = inl(DE4X5_OMR); j+=4;
5731 tmp.lval[j>>2] = inl(DE4X5_IMR); j+=4;
5732 tmp.lval[j>>2] = lp->chipset; j+=4;
5733 if (lp->chipset == DC21140) {
5734 tmp.lval[j>>2] = gep_rd(dev); j+=4;
5735 } else {
5736 tmp.lval[j>>2] = inl(DE4X5_SISR); j+=4;
5737 tmp.lval[j>>2] = inl(DE4X5_SICR); j+=4;
5738 tmp.lval[j>>2] = inl(DE4X5_STRR); j+=4;
5739 tmp.lval[j>>2] = inl(DE4X5_SIGR); j+=4;
5740 }
5741 tmp.lval[j>>2] = lp->phy[lp->active].id; j+=4;
5742 if (lp->phy[lp->active].id && (!lp->useSROM || lp->useMII)) {
5743 tmp.lval[j>>2] = lp->active; j+=4;
5744 tmp.lval[j>>2]=mii_rd(MII_CR,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5745 tmp.lval[j>>2]=mii_rd(MII_SR,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5746 tmp.lval[j>>2]=mii_rd(MII_ID0,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5747 tmp.lval[j>>2]=mii_rd(MII_ID1,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5748 if (lp->phy[lp->active].id != BROADCOM_T4) {
5749 tmp.lval[j>>2]=mii_rd(MII_ANA,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5750 tmp.lval[j>>2]=mii_rd(MII_ANLPA,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5751 }
5752 tmp.lval[j>>2]=mii_rd(0x10,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5753 if (lp->phy[lp->active].id != BROADCOM_T4) {
5754 tmp.lval[j>>2]=mii_rd(0x11,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5755 tmp.lval[j>>2]=mii_rd(0x12,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5756 } else {
5757 tmp.lval[j>>2]=mii_rd(0x14,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5758 }
5759 }
5760
5761 tmp.addr[j++] = lp->txRingSize;
5762 tmp.addr[j++] = netif_queue_stopped(dev);
5763
5764 ioc->len = j;
5765 if (copy_to_user(ioc->data, tmp.addr, ioc->len)) return -EFAULT;
5766 break;
5767
5768 */
5769 default:
5770 return -EOPNOTSUPP;
5771 }
5772
5773 return status;
5774 }
5775
5776 #ifdef MODULE
5777 /*
5778 ** Note now that module autoprobing is allowed under EISA and PCI. The
5779 ** IRQ lines will not be auto-detected; instead I'll rely on the BIOSes
5780 ** to "do the right thing".
5781 */
5782 #define LP(a) ((struct de4x5_private *)(a))
5783 static struct net_device *mdev = NULL;
5784 static int io=0x0;/* EDIT THIS LINE FOR YOUR CONFIGURATION IF NEEDED */
5785 MODULE_PARM(io, "i");
5786 MODULE_PARM_DESC(io, "de4x5 I/O base address");
5787
5788 int
init_module(void)5789 init_module(void)
5790 {
5791 int i, num, status = -EIO;
5792 struct net_device *p;
5793
5794 num = count_adapters();
5795
5796 for (i=0; i<num; i++) {
5797 if ((p = insert_device(NULL, io, de4x5_probe)) == NULL)
5798 return -ENOMEM;
5799
5800 if (!mdev) mdev = p;
5801
5802 if (register_netdev(p) != 0) {
5803 struct de4x5_private *lp = (struct de4x5_private *)p->priv;
5804 if (lp) {
5805 release_region(p->base_addr, (lp->bus == PCI ?
5806 DE4X5_PCI_TOTAL_SIZE :
5807 DE4X5_EISA_TOTAL_SIZE));
5808 if (lp->cache.priv) { /* Private area allocated? */
5809 kfree(lp->cache.priv); /* Free the private area */
5810 }
5811 if (lp->rx_ring) {
5812 pci_free_consistent(lp->pdev, lp->dma_size, lp->rx_ring,
5813 lp->dma_rings);
5814 }
5815 }
5816 kfree(p);
5817 } else {
5818 status = 0; /* At least one adapter will work */
5819 lastModule = p;
5820 }
5821 }
5822
5823 return status;
5824 }
5825
5826 void
cleanup_module(void)5827 cleanup_module(void)
5828 {
5829 while (mdev != NULL) {
5830 mdev = unlink_modules(mdev);
5831 }
5832
5833 return;
5834 }
5835
5836 static struct net_device *
unlink_modules(struct net_device * p)5837 unlink_modules(struct net_device *p)
5838 {
5839 struct net_device *next = NULL;
5840
5841 if (p->priv) { /* Private areas allocated? */
5842 struct de4x5_private *lp = (struct de4x5_private *)p->priv;
5843
5844 next = lp->next_module;
5845 if (lp->rx_ring) {
5846 pci_free_consistent(lp->pdev, lp->dma_size, lp->rx_ring,
5847 lp->dma_rings);
5848 }
5849 release_region(p->base_addr, (lp->bus == PCI ?
5850 DE4X5_PCI_TOTAL_SIZE :
5851 DE4X5_EISA_TOTAL_SIZE));
5852 kfree(lp->cache.priv); /* Free the private area */
5853 }
5854 unregister_netdev(p);
5855 kfree(p); /* Free the device structure */
5856
5857 return next;
5858 }
5859
5860 static int
count_adapters(void)5861 count_adapters(void)
5862 {
5863 int i, j=0;
5864 u_short vendor;
5865 u_int class = DE4X5_CLASS_CODE;
5866 u_int device;
5867
5868 #ifdef CONFIG_EISA
5869 char name[DE4X5_STRLEN];
5870 u_long iobase = 0x1000;
5871
5872 for (i=1; i<MAX_EISA_SLOTS; i++, iobase+=EISA_SLOT_INC) {
5873 if (EISA_signature(name, EISA_ID)) j++;
5874 }
5875 #endif
5876 if (!pcibios_present()) return j;
5877
5878 for (i=0; (pdev=pci_find_class(class, pdev))!= NULL; i++) {
5879 vendor = pdev->vendor;
5880 device = pdev->device << 8;
5881 if (is_DC21040 || is_DC21041 || is_DC21140 || is_DC2114x) j++;
5882 }
5883
5884 return j;
5885 }
5886
5887 /*
5888 ** If at end of eth device list and can't use current entry, malloc
5889 ** one up. If memory could not be allocated, print an error message.
5890 */
5891 static struct net_device * __init
insert_device(struct net_device * dev,u_long iobase,int (* init)(struct net_device *))5892 insert_device(struct net_device *dev, u_long iobase, int (*init)(struct net_device *))
5893 {
5894 struct net_device *new;
5895
5896 new = (struct net_device *)kmalloc(sizeof(struct net_device), GFP_KERNEL);
5897 if (new == NULL) {
5898 printk("de4x5.c: Device not initialised, insufficient memory\n");
5899 return NULL;
5900 } else {
5901 memset((char *)new, 0, sizeof(struct net_device));
5902 new->base_addr = iobase; /* assign the io address */
5903 new->init = init; /* initialisation routine */
5904 }
5905
5906 return new;
5907 }
5908
5909 #endif /* MODULE */
5910
5911
5912 /*
5913 * Local variables:
5914 *
5915 * Delete -DMODVERSIONS below if you didn't define this in your kernel
5916 *
5917 * compile-command: "gcc -D__KERNEL__ -DMODULE -I/linux/include -Wall -Wstrict-prototypes -fomit-frame-pointer -fno-strength-reduce -malign-loops=2 -malign-jumps=2 -malign-functions=2 -O2 -m486 -DMODVERSIONS -include /linux/include/linux/modversions.h -c de4x5.c"
5918 * End:
5919 */
5920