1 /* 2 * macserial.h: Definitions for the Macintosh Z8530 serial driver. 3 * 4 * Adapted from drivers/sbus/char/sunserial.h by Paul Mackerras. 5 * 6 * Copyright (C) 1996 Paul Mackerras (Paul.Mackerras@cs.anu.edu.au) 7 * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu) 8 */ 9 #ifndef _MACSERIAL_H 10 #define _MACSERIAL_H 11 12 #define NUM_ZSREGS 16 13 14 struct serial_struct { 15 int type; 16 int line; 17 int port; 18 int irq; 19 int flags; 20 int xmit_fifo_size; 21 int custom_divisor; 22 int baud_base; 23 unsigned short close_delay; 24 char reserved_char[2]; 25 int hub6; 26 unsigned short closing_wait; /* time to wait before closing */ 27 unsigned short closing_wait2; /* no longer used... */ 28 int reserved[4]; 29 }; 30 31 /* 32 * For the close wait times, 0 means wait forever for serial port to 33 * flush its output. 65535 means don't wait at all. 34 */ 35 #define ZILOG_CLOSING_WAIT_INF 0 36 #define ZILOG_CLOSING_WAIT_NONE 65535 37 38 /* 39 * Definitions for ZILOG_struct (and serial_struct) flags field 40 */ 41 #define ZILOG_HUP_NOTIFY 0x0001 /* Notify getty on hangups and closes 42 * on the callout port */ 43 #define ZILOG_FOURPORT 0x0002 /* Set OU1, OUT2 per AST Fourport settings */ 44 #define ZILOG_SAK 0x0004 /* Secure Attention Key (Orange book) */ 45 #define ZILOG_SPLIT_TERMIOS 0x0008 /* Separate termios for dialin/callout */ 46 47 #define ZILOG_SPD_MASK 0x0030 48 #define ZILOG_SPD_HI 0x0010 /* Use 56000 instead of 38400 bps */ 49 50 #define ZILOG_SPD_VHI 0x0020 /* Use 115200 instead of 38400 bps */ 51 #define ZILOG_SPD_CUST 0x0030 /* Use user-specified divisor */ 52 53 #define ZILOG_SKIP_TEST 0x0040 /* Skip UART test during autoconfiguration */ 54 #define ZILOG_AUTO_IRQ 0x0080 /* Do automatic IRQ during autoconfiguration */ 55 #define ZILOG_SESSION_LOCKOUT 0x0100 /* Lock out cua opens based on session */ 56 #define ZILOG_PGRP_LOCKOUT 0x0200 /* Lock out cua opens based on pgrp */ 57 #define ZILOG_CALLOUT_NOHUP 0x0400 /* Don't do hangups for cua device */ 58 59 #define ZILOG_FLAGS 0x0FFF /* Possible legal ZILOG flags */ 60 #define ZILOG_USR_MASK 0x0430 /* Legal flags that non-privileged 61 * users can set or reset */ 62 63 /* Internal flags used only by kernel/chr_drv/serial.c */ 64 #define ZILOG_INITIALIZED 0x80000000 /* Serial port was initialized */ 65 #define ZILOG_CALLOUT_ACTIVE 0x40000000 /* Call out device is active */ 66 #define ZILOG_NORMAL_ACTIVE 0x20000000 /* Normal device is active */ 67 #define ZILOG_BOOT_AUTOCONF 0x10000000 /* Autoconfigure port on bootup */ 68 #define ZILOG_CLOSING 0x08000000 /* Serial port is closing */ 69 #define ZILOG_CTS_FLOW 0x04000000 /* Do CTS flow control */ 70 #define ZILOG_CHECK_CD 0x02000000 /* i.e., CLOCAL */ 71 #define ZILOG_SLEEPING 0x01000000 /* have shut it down for sleep */ 72 73 /* Software state per channel */ 74 75 #ifdef __KERNEL__ 76 /* 77 * This is our internal structure for each serial port's state. 78 * 79 * Many fields are paralleled by the structure used by the serial_struct 80 * structure. 81 * 82 * For definitions of the flags field, see tty.h 83 */ 84 85 struct mac_serial; 86 87 struct mac_zschannel { 88 volatile unsigned char* control; 89 volatile unsigned char* data; 90 spinlock_t lock; 91 /* Used for debugging */ 92 struct mac_serial* parent; 93 }; 94 95 struct mac_dma { 96 volatile struct dbdma_regs dma; 97 volatile unsigned short res_count; 98 volatile unsigned short command; 99 volatile unsigned int buf_addr; 100 }; 101 102 struct mac_serial { 103 struct mac_serial *zs_next; /* For IRQ servicing chain */ 104 struct mac_zschannel *zs_channel; /* Channel registers */ 105 struct mac_zschannel *zs_chan_a; /* A side registers */ 106 unsigned char read_reg_zero; 107 struct device_node* dev_node; 108 109 char soft_carrier; /* Use soft carrier on this channel */ 110 char break_abort; /* Is serial console in, so process brk/abrt */ 111 char kgdb_channel; /* Kgdb is running on this channel */ 112 char is_cons; /* Is this our console. */ 113 char is_internal_modem; /* is connected to an internal modem */ 114 char is_irda; /* is connected to an IrDA codec */ 115 int port_type; /* Port type for pmac_feature */ 116 unsigned char tx_active; /* character is being xmitted */ 117 unsigned char tx_stopped; /* output is suspended */ 118 unsigned char power_wait; /* waiting for power-up delay to expire */ 119 120 /* We need to know the current clock divisor 121 * to read the bps rate the chip has currently 122 * loaded. 123 */ 124 unsigned char clk_divisor; /* May be 1, 16, 32, or 64 */ 125 int zs_baud; 126 127 /* Current write register values */ 128 unsigned char curregs[NUM_ZSREGS]; 129 130 /* Values we need to set next opportunity */ 131 unsigned char pendregs[NUM_ZSREGS]; 132 133 char change_needed; 134 135 int magic; 136 int baud_base; 137 int port; 138 int irq; 139 int flags; /* defined in tty.h */ 140 int type; /* UART type */ 141 struct tty_struct *tty; 142 int read_status_mask; 143 int ignore_status_mask; 144 int timeout; 145 int xmit_fifo_size; 146 int custom_divisor; 147 int x_char; /* xon/xoff character */ 148 int close_delay; 149 unsigned short closing_wait; 150 unsigned short closing_wait2; 151 unsigned long event; 152 unsigned long last_active; 153 int line; 154 int count; /* # of fd on device */ 155 int blocked_open; /* # of blocked opens */ 156 long session; /* Session of opening process */ 157 long pgrp; /* pgrp of opening process */ 158 unsigned char *xmit_buf; 159 int xmit_head; 160 int xmit_tail; 161 int xmit_cnt; 162 struct tq_struct tqueue; 163 struct tq_struct tqueue_hangup; 164 struct termios normal_termios; 165 struct termios callout_termios; 166 wait_queue_head_t open_wait; 167 wait_queue_head_t close_wait; 168 169 volatile struct dbdma_regs *tx_dma; 170 int tx_dma_irq; 171 volatile struct dbdma_cmd *tx_cmds; 172 volatile struct mac_dma *rx; 173 int rx_dma_irq; 174 volatile struct dbdma_cmd **rx_cmds; 175 unsigned char **rx_char_buf; 176 unsigned char **rx_flag_buf; 177 #define RX_BUF_SIZE 256 178 int rx_nbuf; 179 int rx_done_bytes; 180 int rx_ubuf; 181 int rx_fbuf; 182 #define RX_NO_FBUF (-1) 183 int rx_cbuf; 184 spinlock_t rx_dma_lock; 185 int has_dma; 186 int dma_initted; 187 void *dma_priv; 188 struct timer_list poll_dma_timer; 189 #define RX_DMA_TIMER (jiffies + 10*HZ/1000) 190 191 struct timer_list powerup_timer; 192 }; 193 194 195 #define SERIAL_MAGIC 0x5301 196 197 /* 198 * The size of the serial xmit buffer is 1 page, or 4096 bytes 199 */ 200 #define SERIAL_XMIT_SIZE 4096 201 202 /* 203 * Events are used to schedule things to happen at timer-interrupt 204 * time, instead of at rs interrupt time. 205 */ 206 #define RS_EVENT_WRITE_WAKEUP 0 207 208 #endif /* __KERNEL__ */ 209 210 /* Conversion routines to/from brg time constants from/to bits 211 * per second. 212 */ 213 #define BRG_TO_BPS(brg, freq) ((freq) / 2 / ((brg) + 2)) 214 #define BPS_TO_BRG(bps, freq) ((((freq) + (bps)) / (2 * (bps))) - 2) 215 216 /* The Zilog register set */ 217 218 #define FLAG 0x7e 219 220 /* Write Register 0 */ 221 #define R0 0 /* Register selects */ 222 #define R1 1 223 #define R2 2 224 #define R3 3 225 #define R4 4 226 #define R5 5 227 #define R6 6 228 #define R7 7 229 #define R8 8 230 #define R9 9 231 #define R10 10 232 #define R11 11 233 #define R12 12 234 #define R13 13 235 #define R14 14 236 #define R15 15 237 238 #define NULLCODE 0 /* Null Code */ 239 #define POINT_HIGH 0x8 /* Select upper half of registers */ 240 #define RES_EXT_INT 0x10 /* Reset Ext. Status Interrupts */ 241 #define SEND_ABORT 0x18 /* HDLC Abort */ 242 #define RES_RxINT_FC 0x20 /* Reset RxINT on First Character */ 243 #define RES_Tx_P 0x28 /* Reset TxINT Pending */ 244 #define ERR_RES 0x30 /* Error Reset */ 245 #define RES_H_IUS 0x38 /* Reset highest IUS */ 246 247 #define RES_Rx_CRC 0x40 /* Reset Rx CRC Checker */ 248 #define RES_Tx_CRC 0x80 /* Reset Tx CRC Checker */ 249 #define RES_EOM_L 0xC0 /* Reset EOM latch */ 250 251 /* Write Register 1 */ 252 253 #define EXT_INT_ENAB 0x1 /* Ext Int Enable */ 254 #define TxINT_ENAB 0x2 /* Tx Int Enable */ 255 #define PAR_SPEC 0x4 /* Parity is special condition */ 256 257 #define RxINT_DISAB 0 /* Rx Int Disable */ 258 #define RxINT_FCERR 0x8 /* Rx Int on First Character Only or Error */ 259 #define INT_ALL_Rx 0x10 /* Int on all Rx Characters or error */ 260 #define INT_ERR_Rx 0x18 /* Int on error only */ 261 262 #define WT_RDY_RT 0x20 /* W/Req reflects recv if 1, xmit if 0 */ 263 #define WT_FN_RDYFN 0x40 /* W/Req pin is DMA request if 1, wait if 0 */ 264 #define WT_RDY_ENAB 0x80 /* Enable W/Req pin */ 265 266 /* Write Register #2 (Interrupt Vector) */ 267 268 /* Write Register 3 */ 269 270 #define RxENABLE 0x1 /* Rx Enable */ 271 #define SYNC_L_INH 0x2 /* Sync Character Load Inhibit */ 272 #define ADD_SM 0x4 /* Address Search Mode (SDLC) */ 273 #define RxCRC_ENAB 0x8 /* Rx CRC Enable */ 274 #define ENT_HM 0x10 /* Enter Hunt Mode */ 275 #define AUTO_ENAB 0x20 /* Auto Enables */ 276 #define Rx5 0x0 /* Rx 5 Bits/Character */ 277 #define Rx7 0x40 /* Rx 7 Bits/Character */ 278 #define Rx6 0x80 /* Rx 6 Bits/Character */ 279 #define Rx8 0xc0 /* Rx 8 Bits/Character */ 280 #define RxNBITS_MASK 0xc0 281 282 /* Write Register 4 */ 283 284 #define PAR_ENA 0x1 /* Parity Enable */ 285 #define PAR_EVEN 0x2 /* Parity Even/Odd* */ 286 287 #define SYNC_ENAB 0 /* Sync Modes Enable */ 288 #define SB1 0x4 /* 1 stop bit/char */ 289 #define SB15 0x8 /* 1.5 stop bits/char */ 290 #define SB2 0xc /* 2 stop bits/char */ 291 #define SB_MASK 0xc 292 293 #define MONSYNC 0 /* 8 Bit Sync character */ 294 #define BISYNC 0x10 /* 16 bit sync character */ 295 #define SDLC 0x20 /* SDLC Mode (01111110 Sync Flag) */ 296 #define EXTSYNC 0x30 /* External Sync Mode */ 297 298 #define X1CLK 0x0 /* x1 clock mode */ 299 #define X16CLK 0x40 /* x16 clock mode */ 300 #define X32CLK 0x80 /* x32 clock mode */ 301 #define X64CLK 0xC0 /* x64 clock mode */ 302 #define XCLK_MASK 0xC0 303 304 /* Write Register 5 */ 305 306 #define TxCRC_ENAB 0x1 /* Tx CRC Enable */ 307 #define RTS 0x2 /* RTS */ 308 #define SDLC_CRC 0x4 /* SDLC/CRC-16 */ 309 #define TxENAB 0x8 /* Tx Enable */ 310 #define SND_BRK 0x10 /* Send Break */ 311 #define Tx5 0x0 /* Tx 5 bits (or less)/character */ 312 #define Tx7 0x20 /* Tx 7 bits/character */ 313 #define Tx6 0x40 /* Tx 6 bits/character */ 314 #define Tx8 0x60 /* Tx 8 bits/character */ 315 #define TxNBITS_MASK 0x60 316 #define DTR 0x80 /* DTR */ 317 318 /* Write Register 6 (Sync bits 0-7/SDLC Address Field) */ 319 320 /* Write Register 7 (Sync bits 8-15/SDLC 01111110) */ 321 322 /* Write Register 7' (Some enhanced feature control) */ 323 #define ENEXREAD 0x40 /* Enable read of some write registers */ 324 325 /* Write Register 8 (transmit buffer) */ 326 327 /* Write Register 9 (Master interrupt control) */ 328 #define VIS 1 /* Vector Includes Status */ 329 #define NV 2 /* No Vector */ 330 #define DLC 4 /* Disable Lower Chain */ 331 #define MIE 8 /* Master Interrupt Enable */ 332 #define STATHI 0x10 /* Status high */ 333 #define NORESET 0 /* No reset on write to R9 */ 334 #define CHRB 0x40 /* Reset channel B */ 335 #define CHRA 0x80 /* Reset channel A */ 336 #define FHWRES 0xc0 /* Force hardware reset */ 337 338 /* Write Register 10 (misc control bits) */ 339 #define BIT6 1 /* 6 bit/8bit sync */ 340 #define LOOPMODE 2 /* SDLC Loop mode */ 341 #define ABUNDER 4 /* Abort/flag on SDLC xmit underrun */ 342 #define MARKIDLE 8 /* Mark/flag on idle */ 343 #define GAOP 0x10 /* Go active on poll */ 344 #define NRZ 0 /* NRZ mode */ 345 #define NRZI 0x20 /* NRZI mode */ 346 #define FM1 0x40 /* FM1 (transition = 1) */ 347 #define FM0 0x60 /* FM0 (transition = 0) */ 348 #define CRCPS 0x80 /* CRC Preset I/O */ 349 350 /* Write Register 11 (Clock Mode control) */ 351 #define TRxCXT 0 /* TRxC = Xtal output */ 352 #define TRxCTC 1 /* TRxC = Transmit clock */ 353 #define TRxCBR 2 /* TRxC = BR Generator Output */ 354 #define TRxCDP 3 /* TRxC = DPLL output */ 355 #define TRxCOI 4 /* TRxC O/I */ 356 #define TCRTxCP 0 /* Transmit clock = RTxC pin */ 357 #define TCTRxCP 8 /* Transmit clock = TRxC pin */ 358 #define TCBR 0x10 /* Transmit clock = BR Generator output */ 359 #define TCDPLL 0x18 /* Transmit clock = DPLL output */ 360 #define RCRTxCP 0 /* Receive clock = RTxC pin */ 361 #define RCTRxCP 0x20 /* Receive clock = TRxC pin */ 362 #define RCBR 0x40 /* Receive clock = BR Generator output */ 363 #define RCDPLL 0x60 /* Receive clock = DPLL output */ 364 #define RTxCX 0x80 /* RTxC Xtal/No Xtal */ 365 366 /* Write Register 12 (lower byte of baud rate generator time constant) */ 367 368 /* Write Register 13 (upper byte of baud rate generator time constant) */ 369 370 /* Write Register 14 (Misc control bits) */ 371 #define BRENABL 1 /* Baud rate generator enable */ 372 #define BRSRC 2 /* Baud rate generator source */ 373 #define DTRREQ 4 /* DTR/Request function */ 374 #define AUTOECHO 8 /* Auto Echo */ 375 #define LOOPBAK 0x10 /* Local loopback */ 376 #define SEARCH 0x20 /* Enter search mode */ 377 #define RMC 0x40 /* Reset missing clock */ 378 #define DISDPLL 0x60 /* Disable DPLL */ 379 #define SSBR 0x80 /* Set DPLL source = BR generator */ 380 #define SSRTxC 0xa0 /* Set DPLL source = RTxC */ 381 #define SFMM 0xc0 /* Set FM mode */ 382 #define SNRZI 0xe0 /* Set NRZI mode */ 383 384 /* Write Register 15 (external/status interrupt control) */ 385 #define EN85C30 1 /* Enable some 85c30-enhanced registers */ 386 #define ZCIE 2 /* Zero count IE */ 387 #define ENSTFIFO 4 /* Enable status FIFO (SDLC) */ 388 #define DCDIE 8 /* DCD IE */ 389 #define SYNCIE 0x10 /* Sync/hunt IE */ 390 #define CTSIE 0x20 /* CTS IE */ 391 #define TxUIE 0x40 /* Tx Underrun/EOM IE */ 392 #define BRKIE 0x80 /* Break/Abort IE */ 393 394 395 /* Read Register 0 */ 396 #define Rx_CH_AV 0x1 /* Rx Character Available */ 397 #define ZCOUNT 0x2 /* Zero count */ 398 #define Tx_BUF_EMP 0x4 /* Tx Buffer empty */ 399 #define DCD 0x8 /* DCD */ 400 #define SYNC_HUNT 0x10 /* Sync/hunt */ 401 #define CTS 0x20 /* CTS */ 402 #define TxEOM 0x40 /* Tx underrun */ 403 #define BRK_ABRT 0x80 /* Break/Abort */ 404 405 /* Read Register 1 */ 406 #define ALL_SNT 0x1 /* All sent */ 407 /* Residue Data for 8 Rx bits/char programmed */ 408 #define RES3 0x8 /* 0/3 */ 409 #define RES4 0x4 /* 0/4 */ 410 #define RES5 0xc /* 0/5 */ 411 #define RES6 0x2 /* 0/6 */ 412 #define RES7 0xa /* 0/7 */ 413 #define RES8 0x6 /* 0/8 */ 414 #define RES18 0xe /* 1/8 */ 415 #define RES28 0x0 /* 2/8 */ 416 /* Special Rx Condition Interrupts */ 417 #define PAR_ERR 0x10 /* Parity error */ 418 #define Rx_OVR 0x20 /* Rx Overrun Error */ 419 #define FRM_ERR 0x40 /* CRC/Framing Error */ 420 #define END_FR 0x80 /* End of Frame (SDLC) */ 421 422 /* Read Register 2 (channel b only) - Interrupt vector */ 423 #define CHB_Tx_EMPTY 0x00 424 #define CHB_EXT_STAT 0x02 425 #define CHB_Rx_AVAIL 0x04 426 #define CHB_SPECIAL 0x06 427 #define CHA_Tx_EMPTY 0x08 428 #define CHA_EXT_STAT 0x0a 429 #define CHA_Rx_AVAIL 0x0c 430 #define CHA_SPECIAL 0x0e 431 #define STATUS_MASK 0x06 432 433 /* Read Register 3 (interrupt pending register) ch a only */ 434 #define CHBEXT 0x1 /* Channel B Ext/Stat IP */ 435 #define CHBTxIP 0x2 /* Channel B Tx IP */ 436 #define CHBRxIP 0x4 /* Channel B Rx IP */ 437 #define CHAEXT 0x8 /* Channel A Ext/Stat IP */ 438 #define CHATxIP 0x10 /* Channel A Tx IP */ 439 #define CHARxIP 0x20 /* Channel A Rx IP */ 440 441 /* Read Register 8 (receive data register) */ 442 443 /* Read Register 10 (misc status bits) */ 444 #define ONLOOP 2 /* On loop */ 445 #define LOOPSEND 0x10 /* Loop sending */ 446 #define CLK2MIS 0x40 /* Two clocks missing */ 447 #define CLK1MIS 0x80 /* One clock missing */ 448 449 /* Read Register 12 (lower byte of baud rate generator constant) */ 450 451 /* Read Register 13 (upper byte of baud rate generator constant) */ 452 453 /* Read Register 15 (value of WR 15) */ 454 455 /* Misc macros */ 456 #define ZS_CLEARERR(channel) (write_zsreg(channel, 0, ERR_RES)) 457 #define ZS_CLEARFIFO(channel) do { volatile unsigned char garbage; \ 458 garbage = read_zsdata(channel); \ 459 garbage = read_zsdata(channel); \ 460 garbage = read_zsdata(channel); \ 461 } while(0) 462 463 #endif /* !(_MACSERIAL_H) */ 464