1 /* gerdes_amd7930.c,v 0.99 2001/10/02
2 *
3 * gerdes_amd7930.c Amd 79C30A and 79C32A specific routines
4 * (based on HiSax driver by Karsten Keil)
5 *
6 * Author Christoph Ersfeld <info@formula-n.de>
7 * Formula-n Europe AG (www.formula-n.com)
8 * previously Gerdes AG
9 *
10 *
11 * This file is (c) under GNU PUBLIC LICENSE
12 *
13 *
14 * Notes:
15 * Version 0.99 is the first release of this driver and there are
16 * certainly a few bugs.
17 *
18 * Please don't report any malfunction to me without sending
19 * (compressed) debug-logs.
20 * It would be nearly impossible to retrace it.
21 *
22 * Log D-channel-processing as follows:
23 *
24 * 1. Load hisax with card-specific parameters, this example ist for
25 * Formula-n enter:now ISDN PCI and compatible
26 * (f.e. Gerdes Power ISDN PCI)
27 *
28 * modprobe hisax type=41 protocol=2 id=gerdes
29 *
30 * if you chose an other value for id, you need to modify the
31 * code below, too.
32 *
33 * 2. set debug-level
34 *
35 * hisaxctrl gerdes 1 0x3ff
36 * hisaxctrl gerdes 11 0x4f
37 * cat /dev/isdnctrl >> ~/log &
38 *
39 * Please take also a look into /var/log/messages if there is
40 * anything importand concerning HISAX.
41 *
42 *
43 * Credits:
44 * Programming the driver for Formula-n enter:now ISDN PCI and
45 * neccessary this driver for the used Amd 7930 D-channel-controller
46 * was spnsored by Formula-n Europe AG.
47 * Thanks to Karsten Keil and Petr Novak, who gave me support in
48 * Hisax-specific questions.
49 * I want so say special thanks to Carl-Friedrich Braun, who had to
50 * answer a lot of questions about generally ISDN and about handling
51 * of the Amd-Chip.
52 *
53 */
54
55
56 #define __NO_VERSION__
57 #include "hisax.h"
58 #include "isdnl1.h"
59 #include "isac.h"
60 #include "amd7930_fn.h"
61 #include <linux/interrupt.h>
62 #include <linux/init.h>
63
64 static WORD initAMD[] __devinitdata = {
65 0x0100,
66
67 0x00A5, 3, 0x01, 0x40, 0x58, // LPR, LMR1, LMR2
68 0x0086, 1, 0x0B, // DMR1 (D-Buffer TH-Interrupts on)
69 0x0087, 1, 0xFF, // DMR2
70 0x0092, 1, 0x03, // EFCR (extended mode d-channel-fifo on)
71 0x0090, 4, 0xFE, 0xFF, 0x02, 0x0F, // FRAR4, SRAR4, DMR3, DMR4 (address recognition )
72 0x0084, 2, 0x80, 0x00, // DRLR
73 0x00C0, 1, 0x47, // PPCR1
74 0x00C8, 1, 0x01, // PPCR2
75
76 0x0102,
77 0x0107,
78 0x01A1, 1,
79 0x0121, 1,
80 0x0189, 2,
81
82 0x0045, 4, 0x61, 0x72, 0x00, 0x00, // MCR1, MCR2, MCR3, MCR4
83 0x0063, 2, 0x08, 0x08, // GX
84 0x0064, 2, 0x08, 0x08, // GR
85 0x0065, 2, 0x99, 0x00, // GER
86 0x0066, 2, 0x7C, 0x8B, // STG
87 0x0067, 2, 0x00, 0x00, // FTGR1, FTGR2
88 0x0068, 2, 0x20, 0x20, // ATGR1, ATGR2
89 0x0069, 1, 0x4F, // MMR1
90 0x006A, 1, 0x00, // MMR2
91 0x006C, 1, 0x40, // MMR3
92 0x0021, 1, 0x02, // INIT
93 0x00A3, 1, 0x40, // LMR1
94
95 0xFFFF};
96
97
98 static void Amd7930_new_ph(struct IsdnCardState *cs);
99
100
101 void /* macro wWordAMD */
WriteWordAmd7930(struct IsdnCardState * cs,BYTE reg,WORD val)102 WriteWordAmd7930(struct IsdnCardState *cs, BYTE reg, WORD val)
103 {
104 wByteAMD(cs, 0x00, reg);
105 wByteAMD(cs, 0x01, LOBYTE(val));
106 wByteAMD(cs, 0x01, HIBYTE(val));
107 }
108
109 WORD /* macro rWordAMD */
ReadWordAmd7930(struct IsdnCardState * cs,BYTE reg)110 ReadWordAmd7930(struct IsdnCardState *cs, BYTE reg)
111 {
112 WORD res;
113 /* direct access register */
114 if(reg < 8) {
115 res = rByteAMD(cs, reg);
116 res += 256*rByteAMD(cs, reg);
117 }
118 /* indirect access register */
119 else {
120 wByteAMD(cs, 0x00, reg);
121 res = rByteAMD(cs, 0x01);
122 res += 256*rByteAMD(cs, 0x01);
123 }
124 return (res);
125 }
126
127
128 static void
Amd7930_ph_command(struct IsdnCardState * cs,u_char command,char * s)129 Amd7930_ph_command(struct IsdnCardState *cs, u_char command, char *s)
130 {
131 if (cs->debug & L1_DEB_ISAC)
132 debugl1(cs, "AMD7930: %s: ph_command 0x%02X", s, command);
133
134 cs->dc.amd7930.lmr1 = command;
135 wByteAMD(cs, 0xA3, command);
136 }
137
138
139
140 static BYTE i430States[] = {
141 // to reset F3 F4 F5 F6 F7 F8 AR from
142 0x01, 0x02, 0x00, 0x00, 0x00, 0x07, 0x05, 0x00, // init
143 0x01, 0x02, 0x00, 0x00, 0x00, 0x07, 0x05, 0x00, // reset
144 0x01, 0x02, 0x00, 0x00, 0x00, 0x09, 0x05, 0x04, // F3
145 0x01, 0x02, 0x00, 0x00, 0x1B, 0x00, 0x00, 0x00, // F4
146 0x01, 0x02, 0x00, 0x00, 0x1B, 0x00, 0x00, 0x00, // F5
147 0x01, 0x03, 0x00, 0x00, 0x00, 0x06, 0x05, 0x00, // F6
148 0x11, 0x13, 0x00, 0x00, 0x1B, 0x00, 0x15, 0x00, // F7
149 0x01, 0x03, 0x00, 0x00, 0x00, 0x06, 0x00, 0x00, // F8
150 0x01, 0x03, 0x00, 0x00, 0x00, 0x09, 0x00, 0x0A}; // AR
151
152
153 /* Row init - reset F3 F4 F5 F6 F7 F8 AR */
154 static BYTE stateHelper[] = { 0x00, 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08 };
155
156
157
158
159 static void
Amd7930_get_state(struct IsdnCardState * cs)160 Amd7930_get_state(struct IsdnCardState *cs) {
161 BYTE lsr = rByteAMD(cs, 0xA1);
162 cs->dc.amd7930.ph_state = (lsr & 0x7) + 2;
163 Amd7930_new_ph(cs);
164 }
165
166
167
168 static void
Amd7930_new_ph(struct IsdnCardState * cs)169 Amd7930_new_ph(struct IsdnCardState *cs)
170 {
171 u_char index = stateHelper[cs->dc.amd7930.old_state]*8 + stateHelper[cs->dc.amd7930.ph_state]-1;
172 u_char message = i430States[index];
173
174 if (cs->debug & L1_DEB_ISAC)
175 debugl1(cs, "AMD7930: new_ph %d, old_ph %d, message %d, index %d",
176 cs->dc.amd7930.ph_state, cs->dc.amd7930.old_state, message & 0x0f, index);
177
178 cs->dc.amd7930.old_state = cs->dc.amd7930.ph_state;
179
180 /* abort transmit if nessesary */
181 if ((message & 0xf0) && (cs->tx_skb)) {
182 wByteAMD(cs, 0x21, 0xC2);
183 wByteAMD(cs, 0x21, 0x02);
184 }
185
186 switch (message & 0x0f) {
187
188 case (1):
189 l1_msg(cs, HW_RESET | INDICATION, NULL);
190 Amd7930_get_state(cs);
191 break;
192 case (2): /* init, Card starts in F3 */
193 l1_msg(cs, HW_DEACTIVATE | CONFIRM, NULL);
194 break;
195 case (3):
196 l1_msg(cs, HW_DEACTIVATE | INDICATION, NULL);
197 break;
198 case (4):
199 l1_msg(cs, HW_POWERUP | CONFIRM, NULL);
200 Amd7930_ph_command(cs, 0x50, "HW_ENABLE REQUEST");
201 break;
202 case (5):
203 l1_msg(cs, HW_RSYNC | INDICATION, NULL);
204 break;
205 case (6):
206 l1_msg(cs, HW_INFO4_P8 | INDICATION, NULL);
207 break;
208 case (7): /* init, Card starts in F7 */
209 l1_msg(cs, HW_RSYNC | INDICATION, NULL);
210 l1_msg(cs, HW_INFO4_P8 | INDICATION, NULL);
211 break;
212 case (8):
213 l1_msg(cs, HW_POWERUP | CONFIRM, NULL);
214 /* fall through */
215 case (9):
216 Amd7930_ph_command(cs, 0x40, "HW_ENABLE REQ cleared if set");
217 l1_msg(cs, HW_RSYNC | INDICATION, NULL);
218 l1_msg(cs, HW_INFO2 | INDICATION, NULL);
219 l1_msg(cs, HW_INFO4_P8 | INDICATION, NULL);
220 break;
221 case (10):
222 Amd7930_ph_command(cs, 0x40, "T3 expired, HW_ENABLE REQ cleared");
223 cs->dc.amd7930.old_state = 3;
224 break;
225 case (11):
226 l1_msg(cs, HW_INFO2 | INDICATION, NULL);
227 break;
228 default:
229 break;
230 }
231 }
232
233
234
235 static void
Amd7930_bh(struct IsdnCardState * cs)236 Amd7930_bh(struct IsdnCardState *cs)
237 {
238
239 struct PStack *stptr;
240
241 if (!cs)
242 return;
243 if (test_and_clear_bit(D_CLEARBUSY, &cs->event)) {
244 if (cs->debug)
245 debugl1(cs, "Amd7930: bh, D-Channel Busy cleared");
246 stptr = cs->stlist;
247 while (stptr != NULL) {
248 stptr->l1.l1l2(stptr, PH_PAUSE | CONFIRM, NULL);
249 stptr = stptr->next;
250 }
251 }
252 if (test_and_clear_bit(D_L1STATECHANGE, &cs->event)) {
253 if (cs->debug & L1_DEB_ISAC)
254 debugl1(cs, "AMD7930: bh, D_L1STATECHANGE");
255 Amd7930_new_ph(cs);
256 }
257
258 if (test_and_clear_bit(D_RCVBUFREADY, &cs->event)) {
259 if (cs->debug & L1_DEB_ISAC)
260 debugl1(cs, "AMD7930: bh, D_RCVBUFREADY");
261 DChannel_proc_rcv(cs);
262 }
263
264 if (test_and_clear_bit(D_XMTBUFREADY, &cs->event)) {
265 if (cs->debug & L1_DEB_ISAC)
266 debugl1(cs, "AMD7930: bh, D_XMTBUFREADY");
267 DChannel_proc_xmt(cs);
268 }
269 }
270
271
272 void
Amd7930_sched_event(struct IsdnCardState * cs,int event)273 Amd7930_sched_event(struct IsdnCardState *cs, int event) // ok
274 {
275
276 if (cs->debug & L1_DEB_ISAC) {
277 debugl1(cs, "AMD7930: sched_event 0x%X", event);
278 }
279
280 test_and_set_bit(event, &cs->event);
281 queue_task(&cs->tqueue, &tq_immediate);
282 mark_bh(IMMEDIATE_BH);
283 }
284
285 static void
Amd7930_empty_Dfifo(struct IsdnCardState * cs,int flag)286 Amd7930_empty_Dfifo(struct IsdnCardState *cs, int flag)
287 {
288
289 BYTE stat, der;
290 BYTE *ptr;
291 struct sk_buff *skb;
292
293
294 if ((cs->debug & L1_DEB_ISAC) && !(cs->debug & L1_DEB_ISAC_FIFO))
295 debugl1(cs, "Amd7930: empty_Dfifo");
296
297
298 ptr = cs->rcvbuf + cs->rcvidx;
299
300 /* AMD interrupts off */
301 AmdIrqOff(cs);
302
303 /* read D-Channel-Fifo*/
304 stat = rByteAMD(cs, 0x07); // DSR2
305
306 /* while Data in Fifo ... */
307 while ( (stat & 2) && ((ptr-cs->rcvbuf) < MAX_DFRAME_LEN_L1) ) {
308 *ptr = rByteAMD(cs, 0x04); // DCRB
309 ptr++;
310 stat = rByteAMD(cs, 0x07); // DSR2
311 cs->rcvidx = ptr - cs->rcvbuf;
312
313 /* Paket ready? */
314 if (stat & 1) {
315
316 der = rWordAMD(cs, 0x03);
317
318 /* no errors, packet ok */
319 if(!der && !flag) {
320 rWordAMD(cs, 0x89); // clear DRCR
321
322 if ((cs->rcvidx) > 0) {
323 if (!(skb = alloc_skb(cs->rcvidx, GFP_ATOMIC)))
324 printk(KERN_WARNING "HiSax: Amd7930: empty_Dfifo, D receive out of memory!\n");
325 else {
326 /* Debugging */
327 if (cs->debug & L1_DEB_ISAC_FIFO) {
328 char *t = cs->dlog;
329
330 t += sprintf(t, "Amd7930: empty_Dfifo cnt: %d |", cs->rcvidx);
331 QuickHex(t, cs->rcvbuf, cs->rcvidx);
332 debugl1(cs, cs->dlog);
333 }
334 /* moves recieved data in sk-buffer */
335 memcpy(skb_put(skb, cs->rcvidx), cs->rcvbuf, cs->rcvidx);
336 skb_queue_tail(&cs->rq, skb);
337 }
338 }
339
340 }
341 /* throw damaged packets away, reset recieve-buffer, indicate RX */
342 ptr = cs->rcvbuf;
343 cs->rcvidx = 0;
344 Amd7930_sched_event(cs, D_RCVBUFREADY);
345 }
346 }
347 /* Packet to long, overflow */
348 if(cs->rcvidx >= MAX_DFRAME_LEN_L1) {
349 if (cs->debug & L1_DEB_WARN)
350 debugl1(cs, "AMD7930: empty_Dfifo L2-Framelength overrun");
351 cs->rcvidx = 0;
352 return;
353 }
354 /* AMD interrupts on */
355 AmdIrqOn(cs);
356 }
357
358
359 static void
Amd7930_fill_Dfifo(struct IsdnCardState * cs)360 Amd7930_fill_Dfifo(struct IsdnCardState *cs)
361 {
362
363 WORD dtcrr, dtcrw, len, count;
364 BYTE txstat, dmr3;
365 BYTE *ptr, *deb_ptr;
366
367 if ((cs->debug & L1_DEB_ISAC) && !(cs->debug & L1_DEB_ISAC_FIFO))
368 debugl1(cs, "Amd7930: fill_Dfifo");
369
370 if ((!cs->tx_skb) || (cs->tx_skb->len <= 0))
371 return;
372
373 dtcrw = 0;
374 if(!cs->dc.amd7930.tx_xmtlen)
375 /* new Frame */
376 len = dtcrw = cs->tx_skb->len;
377 /* continue frame */
378 else len = cs->dc.amd7930.tx_xmtlen;
379
380
381 /* AMD interrupts off */
382 AmdIrqOff(cs);
383
384 deb_ptr = ptr = cs->tx_skb->data;
385
386 /* while free place in tx-fifo available and data in sk-buffer */
387 txstat = 0x10;
388 while((txstat & 0x10) && (cs->tx_cnt < len)) {
389 wByteAMD(cs, 0x04, *ptr);
390 ptr++;
391 cs->tx_cnt++;
392 txstat= rByteAMD(cs, 0x07);
393 }
394 count = ptr - cs->tx_skb->data;
395 skb_pull(cs->tx_skb, count);
396
397
398 dtcrr = rWordAMD(cs, 0x85); // DTCR
399 dmr3 = rByteAMD(cs, 0x8E);
400
401 if (cs->debug & L1_DEB_ISAC) {
402 debugl1(cs, "Amd7930: fill_Dfifo, DMR3: 0x%02X, DTCR read: 0x%04X write: 0x%02X 0x%02X", dmr3, dtcrr, LOBYTE(dtcrw), HIBYTE(dtcrw));
403 }
404
405 /* writeing of dtcrw starts transmit */
406 if(!cs->dc.amd7930.tx_xmtlen) {
407 wWordAMD(cs, 0x85, dtcrw);
408 cs->dc.amd7930.tx_xmtlen = dtcrw;
409 }
410
411 if (test_and_set_bit(FLG_DBUSY_TIMER, &cs->HW_Flags)) {
412 debugl1(cs, "Amd7930: fill_Dfifo dbusytimer running");
413 del_timer(&cs->dbusytimer);
414 }
415 init_timer(&cs->dbusytimer);
416 cs->dbusytimer.expires = jiffies + ((DBUSY_TIMER_VALUE * HZ) / 1000);
417 add_timer(&cs->dbusytimer);
418
419 if (cs->debug & L1_DEB_ISAC_FIFO) {
420 char *t = cs->dlog;
421
422 t += sprintf(t, "Amd7930: fill_Dfifo cnt: %d |", count);
423 QuickHex(t, deb_ptr, count);
424 debugl1(cs, cs->dlog);
425 }
426 /* AMD interrupts on */
427 AmdIrqOn(cs);
428 }
429
430
Amd7930_interrupt(struct IsdnCardState * cs,BYTE irflags)431 void Amd7930_interrupt(struct IsdnCardState *cs, BYTE irflags)
432 {
433 BYTE dsr1, dsr2, lsr;
434 WORD der;
435
436 while (irflags)
437 {
438
439 dsr1 = rByteAMD(cs, 0x02);
440 der = rWordAMD(cs, 0x03);
441 dsr2 = rByteAMD(cs, 0x07);
442 lsr = rByteAMD(cs, 0xA1);
443
444 if (cs->debug & L1_DEB_ISAC)
445 debugl1(cs, "Amd7930: interrupt: flags: 0x%02X, DSR1: 0x%02X, DSR2: 0x%02X, LSR: 0x%02X, DER=0x%04X", irflags, dsr1, dsr2, lsr, der);
446
447 /* D error -> read DER and DSR2 bit 2 */
448 if (der || (dsr2 & 4)) {
449
450 if (cs->debug & L1_DEB_WARN)
451 debugl1(cs, "Amd7930: interrupt: D error DER=0x%04X", der);
452
453 /* RX, TX abort if collision detected */
454 if (der & 2) {
455 wByteAMD(cs, 0x21, 0xC2);
456 wByteAMD(cs, 0x21, 0x02);
457 if (test_and_clear_bit(FLG_DBUSY_TIMER, &cs->HW_Flags))
458 del_timer(&cs->dbusytimer);
459 if (test_and_clear_bit(FLG_L1_DBUSY, &cs->HW_Flags))
460 Amd7930_sched_event(cs, D_CLEARBUSY);
461 /* restart frame */
462 if (cs->tx_skb) {
463 skb_push(cs->tx_skb, cs->tx_cnt);
464 cs->tx_cnt = 0;
465 cs->dc.amd7930.tx_xmtlen = 0;
466 Amd7930_fill_Dfifo(cs);
467 } else {
468 printk(KERN_WARNING "HiSax: Amd7930 D-Collision, no skb\n");
469 debugl1(cs, "Amd7930: interrupt: D-Collision, no skb");
470 }
471 }
472 /* remove damaged data from fifo */
473 Amd7930_empty_Dfifo(cs, 1);
474
475 if (test_and_clear_bit(FLG_DBUSY_TIMER, &cs->HW_Flags))
476 del_timer(&cs->dbusytimer);
477 if (test_and_clear_bit(FLG_L1_DBUSY, &cs->HW_Flags))
478 Amd7930_sched_event(cs, D_CLEARBUSY);
479 /* restart TX-Frame */
480 if (cs->tx_skb) {
481 skb_push(cs->tx_skb, cs->tx_cnt);
482 cs->tx_cnt = 0;
483 cs->dc.amd7930.tx_xmtlen = 0;
484 Amd7930_fill_Dfifo(cs);
485 }
486 }
487
488 /* D TX FIFO empty -> fill */
489 if (irflags & 1) {
490 if (cs->debug & L1_DEB_ISAC)
491 debugl1(cs, "Amd7930: interrupt: clear Timer and fill D-TX-FIFO if data");
492
493 /* AMD interrupts off */
494 AmdIrqOff(cs);
495
496 if (test_and_clear_bit(FLG_DBUSY_TIMER, &cs->HW_Flags))
497 del_timer(&cs->dbusytimer);
498 if (test_and_clear_bit(FLG_L1_DBUSY, &cs->HW_Flags))
499 Amd7930_sched_event(cs, D_CLEARBUSY);
500 if (cs->tx_skb) {
501 if (cs->tx_skb->len)
502 Amd7930_fill_Dfifo(cs);
503 }
504 /* AMD interrupts on */
505 AmdIrqOn(cs);
506 }
507
508
509 /* D RX FIFO full or tiny packet in Fifo -> empty */
510 if ((irflags & 2) || (dsr1 & 2)) {
511 if (cs->debug & L1_DEB_ISAC)
512 debugl1(cs, "Amd7930: interrupt: empty D-FIFO");
513 Amd7930_empty_Dfifo(cs, 0);
514 }
515
516
517 /* D-Frame transmit complete */
518 if (dsr1 & 64) {
519 if (cs->debug & L1_DEB_ISAC) {
520 debugl1(cs, "Amd7930: interrupt: transmit packet ready");
521 }
522 /* AMD interrupts off */
523 AmdIrqOff(cs);
524
525 if (test_and_clear_bit(FLG_DBUSY_TIMER, &cs->HW_Flags))
526 del_timer(&cs->dbusytimer);
527 if (test_and_clear_bit(FLG_L1_DBUSY, &cs->HW_Flags))
528 Amd7930_sched_event(cs, D_CLEARBUSY);
529
530 if (cs->tx_skb) {
531 if (cs->debug & L1_DEB_ISAC)
532 debugl1(cs, "Amd7930: interrupt: TX-Packet ready, freeing skb");
533 dev_kfree_skb_irq(cs->tx_skb);
534 cs->tx_cnt = 0;
535 cs->dc.amd7930.tx_xmtlen=0;
536 cs->tx_skb = NULL;
537 }
538 if ((cs->tx_skb = skb_dequeue(&cs->sq))) {
539 if (cs->debug & L1_DEB_ISAC)
540 debugl1(cs, "Amd7930: interrupt: TX-Packet ready, next packet dequeued");
541 cs->tx_cnt = 0;
542 cs->dc.amd7930.tx_xmtlen=0;
543 Amd7930_fill_Dfifo(cs);
544 }
545 else
546 Amd7930_sched_event(cs, D_XMTBUFREADY);
547 /* AMD interrupts on */
548 AmdIrqOn(cs);
549 }
550
551 /* LIU status interrupt -> read LSR, check statechanges */
552 if (lsr & 0x38) {
553 /* AMD interrupts off */
554 AmdIrqOff(cs);
555
556 if (cs->debug & L1_DEB_ISAC)
557 debugl1(cs, "Amd: interrupt: LSR=0x%02X, LIU is in state %d", lsr, ((lsr & 0x7) +2));
558
559 cs->dc.amd7930.ph_state = (lsr & 0x7) + 2;
560
561 Amd7930_sched_event(cs, D_L1STATECHANGE);
562 /* AMD interrupts on */
563 AmdIrqOn(cs);
564 }
565
566 /* reads Interrupt-Register again. If there is a new interrupt-flag: restart handler */
567 irflags = rByteAMD(cs, 0x00);
568 }
569
570 }
571
572 static void
Amd7930_l1hw(struct PStack * st,int pr,void * arg)573 Amd7930_l1hw(struct PStack *st, int pr, void *arg)
574 {
575 struct IsdnCardState *cs = (struct IsdnCardState *) st->l1.hardware;
576 struct sk_buff *skb = arg;
577
578 if (cs->debug & L1_DEB_ISAC)
579 debugl1(cs, "Amd7930: l1hw called, pr: 0x%04X", pr);
580
581 switch (pr) {
582 case (PH_DATA | REQUEST):
583 if (cs->debug & DEB_DLOG_HEX)
584 LogFrame(cs, skb->data, skb->len);
585 if (cs->debug & DEB_DLOG_VERBOSE)
586 dlogframe(cs, skb, 0);
587 if (cs->tx_skb) {
588 skb_queue_tail(&cs->sq, skb);
589 #ifdef L2FRAME_DEBUG /* psa */
590 if (cs->debug & L1_DEB_LAPD)
591 Logl2Frame(cs, skb, "Amd7930: l1hw: PH_DATA Queued", 0);
592 #endif
593 } else {
594 cs->tx_skb = skb;
595 cs->tx_cnt = 0;
596 cs->dc.amd7930.tx_xmtlen=0;
597 #ifdef L2FRAME_DEBUG /* psa */
598 if (cs->debug & L1_DEB_LAPD)
599 Logl2Frame(cs, skb, "Amd7930: l1hw: PH_DATA", 0);
600 #endif
601 Amd7930_fill_Dfifo(cs);
602 }
603 break;
604 case (PH_PULL | INDICATION):
605 if (cs->tx_skb) {
606 if (cs->debug & L1_DEB_WARN)
607 debugl1(cs, "Amd7930: l1hw: l2l1 tx_skb exist this shouldn't happen");
608 skb_queue_tail(&cs->sq, skb);
609 break;
610 }
611 if (cs->debug & DEB_DLOG_HEX)
612 LogFrame(cs, skb->data, skb->len);
613 if (cs->debug & DEB_DLOG_VERBOSE)
614 dlogframe(cs, skb, 0);
615 cs->tx_skb = skb;
616 cs->tx_cnt = 0;
617 cs->dc.amd7930.tx_xmtlen=0;
618 #ifdef L2FRAME_DEBUG /* psa */
619 if (cs->debug & L1_DEB_LAPD)
620 Logl2Frame(cs, skb, "Amd7930: l1hw: PH_DATA_PULLED", 0);
621 #endif
622 Amd7930_fill_Dfifo(cs);
623 break;
624 case (PH_PULL | REQUEST):
625 #ifdef L2FRAME_DEBUG /* psa */
626 if (cs->debug & L1_DEB_LAPD)
627 debugl1(cs, "Amd7930: l1hw: -> PH_REQUEST_PULL, skb: %s", (cs->tx_skb)? "yes":"no");
628 #endif
629 if (!cs->tx_skb) {
630 test_and_clear_bit(FLG_L1_PULL_REQ, &st->l1.Flags);
631 st->l1.l1l2(st, PH_PULL | CONFIRM, NULL);
632 } else
633 test_and_set_bit(FLG_L1_PULL_REQ, &st->l1.Flags);
634 break;
635 case (HW_RESET | REQUEST):
636
637 if ((cs->dc.amd7930.ph_state == 8))
638 /* b-channels off, PH-AR cleared
639 * change to F3 */
640 Amd7930_ph_command(cs, 0x20, "HW_RESET REQEST"); //LMR1 bit 5
641 else {
642 Amd7930_ph_command(cs, 0x40, "HW_RESET REQUEST");
643 cs->dc.amd7930.ph_state = 2;
644 Amd7930_new_ph(cs);
645 }
646 break;
647 case (HW_ENABLE | REQUEST):
648 cs->dc.amd7930.ph_state = 9;
649 Amd7930_new_ph(cs);
650 break;
651 case (HW_INFO3 | REQUEST):
652 // automatic
653 break;
654 case (HW_TESTLOOP | REQUEST):
655 /* not implemented yet */
656 break;
657 case (HW_DEACTIVATE | RESPONSE):
658 skb_queue_purge(&cs->rq);
659 skb_queue_purge(&cs->sq);
660 if (cs->tx_skb) {
661 dev_kfree_skb(cs->tx_skb);
662 cs->tx_skb = NULL;
663 }
664 if (test_and_clear_bit(FLG_DBUSY_TIMER, &cs->HW_Flags))
665 del_timer(&cs->dbusytimer);
666 if (test_and_clear_bit(FLG_L1_DBUSY, &cs->HW_Flags))
667 Amd7930_sched_event(cs, D_CLEARBUSY);
668 break;
669 default:
670 if (cs->debug & L1_DEB_WARN)
671 debugl1(cs, "Amd7930: l1hw: unknown %04x", pr);
672 break;
673 }
674 }
675
676 void
setstack_Amd7930(struct PStack * st,struct IsdnCardState * cs)677 setstack_Amd7930(struct PStack *st, struct IsdnCardState *cs)
678 {
679
680 if (cs->debug & L1_DEB_ISAC)
681 debugl1(cs, "Amd7930: setstack called");
682
683 st->l1.l1hw = Amd7930_l1hw;
684 }
685
686
687 void
DC_Close_Amd7930(struct IsdnCardState * cs)688 DC_Close_Amd7930(struct IsdnCardState *cs) {
689 if (cs->debug & L1_DEB_ISAC)
690 debugl1(cs, "Amd7930: DC_Close called");
691 }
692
693
694 static void
dbusy_timer_handler(struct IsdnCardState * cs)695 dbusy_timer_handler(struct IsdnCardState *cs)
696 {
697 struct PStack *stptr;
698 WORD dtcr, der;
699 BYTE dsr1, dsr2;
700
701
702 if (cs->debug & L1_DEB_ISAC)
703 debugl1(cs, "Amd7930: dbusy_timer expired!");
704
705 if (test_bit(FLG_DBUSY_TIMER, &cs->HW_Flags)) {
706 /* D Transmit Byte Count Register:
707 * Counts down packet's number of Bytes, 0 if packet ready */
708 dtcr = rWordAMD(cs, 0x85);
709 dsr1 = rByteAMD(cs, 0x02);
710 dsr2 = rByteAMD(cs, 0x07);
711 der = rWordAMD(cs, 0x03);
712
713 if (cs->debug & L1_DEB_ISAC)
714 debugl1(cs, "Amd7930: dbusy_timer_handler: DSR1=0x%02X, DSR2=0x%02X, DER=0x%04X, cs->tx_skb->len=%u, tx_stat=%u, dtcr=%u, cs->tx_cnt=%u", dsr1, dsr2, der, cs->tx_skb->len, cs->dc.amd7930.tx_xmtlen, dtcr, cs->tx_cnt);
715
716 if ((cs->dc.amd7930.tx_xmtlen - dtcr) < cs->tx_cnt) { /* D-Channel Busy */
717 test_and_set_bit(FLG_L1_DBUSY, &cs->HW_Flags);
718 stptr = cs->stlist;
719 while (stptr != NULL) {
720 stptr->l1.l1l2(stptr, PH_PAUSE | INDICATION, NULL);
721 stptr = stptr->next;
722 }
723
724 } else {
725 /* discard frame; reset transceiver */
726 test_and_clear_bit(FLG_DBUSY_TIMER, &cs->HW_Flags);
727 if (cs->tx_skb) {
728 dev_kfree_skb_any(cs->tx_skb);
729 cs->tx_cnt = 0;
730 cs->tx_skb = NULL;
731 cs->dc.amd7930.tx_xmtlen = 0;
732 } else {
733 printk(KERN_WARNING "HiSax: Amd7930: D-Channel Busy no skb\n");
734 debugl1(cs, "Amd7930: D-Channel Busy no skb");
735
736 }
737 /* Transmitter reset, abort transmit */
738 wByteAMD(cs, 0x21, 0x82);
739 wByteAMD(cs, 0x21, 0x02);
740 cs->irq_func(cs->irq, cs, NULL);
741
742 if (cs->debug & L1_DEB_ISAC)
743 debugl1(cs, "Amd7930: dbusy_timer_handler: Transmitter reset");
744 }
745 }
746 }
747
748
749
750 void __devinit
Amd7930_init(struct IsdnCardState * cs)751 Amd7930_init(struct IsdnCardState *cs)
752 {
753 WORD *ptr;
754 BYTE cmd, cnt;
755
756 if (cs->debug & L1_DEB_ISAC)
757 debugl1(cs, "Amd7930: initamd called");
758
759 cs->dc.amd7930.tx_xmtlen = 0;
760 cs->dc.amd7930.old_state = 0;
761 cs->dc.amd7930.lmr1 = 0x40;
762 cs->dc.amd7930.ph_command = Amd7930_ph_command;
763 cs->tqueue.routine = (void *) (void *) Amd7930_bh;
764 cs->setstack_d = setstack_Amd7930;
765 cs->DC_Close = DC_Close_Amd7930;
766 cs->dbusytimer.function = (void *) dbusy_timer_handler;
767 cs->dbusytimer.data = (long) cs;
768 init_timer(&cs->dbusytimer);
769
770 /* AMD Initialisation */
771 for (ptr = initAMD; *ptr != 0xFFFF; ) {
772 cmd = LOBYTE(*ptr);
773
774 /* read */
775 if (*ptr++ >= 0x100) {
776 if (cmd < 8)
777 /* setzt Register zur�ck */
778 rByteAMD(cs, cmd);
779 else {
780 wByteAMD(cs, 0x00, cmd);
781 for (cnt = *ptr++; cnt > 0; cnt--)
782 rByteAMD(cs, 0x01);
783 }
784 }
785 /* write */
786 else if (cmd < 8)
787 wByteAMD(cs, cmd, LOBYTE(*ptr++));
788
789 else {
790 wByteAMD(cs, 0x00, cmd);
791 for (cnt = *ptr++; cnt > 0; cnt--)
792 wByteAMD(cs, 0x01, LOBYTE(*ptr++));
793 }
794 }
795 }
796