1 /*
2 * linux/drivers/ide/pci/hpt34x.c Version 0.40 Sept 10, 2002
3 *
4 * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
5 * May be copied or modified under the terms of the GNU General Public License
6 *
7 *
8 * 00:12.0 Unknown mass storage controller:
9 * Triones Technologies, Inc.
10 * Unknown device 0003 (rev 01)
11 *
12 * hde: UDMA 2 (0x0000 0x0002) (0x0000 0x0010)
13 * hdf: UDMA 2 (0x0002 0x0012) (0x0010 0x0030)
14 * hde: DMA 2 (0x0000 0x0002) (0x0000 0x0010)
15 * hdf: DMA 2 (0x0002 0x0012) (0x0010 0x0030)
16 * hdg: DMA 1 (0x0012 0x0052) (0x0030 0x0070)
17 * hdh: DMA 1 (0x0052 0x0252) (0x0070 0x00f0)
18 *
19 * ide-pci.c reference
20 *
21 * Since there are two cards that report almost identically,
22 * the only discernable difference is the values reported in pcicmd.
23 * Booting-BIOS card or HPT363 :: pcicmd == 0x07
24 * Non-bootable card or HPT343 :: pcicmd == 0x05
25 */
26
27 #include <linux/config.h>
28 #include <linux/module.h>
29 #include <linux/types.h>
30 #include <linux/kernel.h>
31 #include <linux/delay.h>
32 #include <linux/timer.h>
33 #include <linux/mm.h>
34 #include <linux/ioport.h>
35 #include <linux/blkdev.h>
36 #include <linux/hdreg.h>
37 #include <linux/interrupt.h>
38 #include <linux/pci.h>
39 #include <linux/init.h>
40 #include <linux/ide.h>
41
42 #include <asm/io.h>
43 #include <asm/irq.h>
44
45 #include "ide_modes.h"
46 #include "hpt34x.h"
47
48 #if defined(DISPLAY_HPT34X_TIMINGS) && defined(CONFIG_PROC_FS)
49 #include <linux/stat.h>
50 #include <linux/proc_fs.h>
51
52 static u8 hpt34x_proc = 0;
53
54 #define HPT34X_MAX_DEVS 8
55 static struct pci_dev *hpt34x_devs[HPT34X_MAX_DEVS];
56 static int n_hpt34x_devs;
57
hpt34x_get_info(char * buffer,char ** addr,off_t offset,int count)58 static int hpt34x_get_info (char *buffer, char **addr, off_t offset, int count)
59 {
60 char *p = buffer;
61 int i, len;
62
63 p += sprintf(p, "\n "
64 "HPT34X Chipset.\n");
65 for (i = 0; i < n_hpt34x_devs; i++) {
66 struct pci_dev *dev = hpt34x_devs[i];
67 unsigned long bibma = pci_resource_start(dev, 4);
68 u8 c0 = 0, c1 = 0;
69
70 /*
71 * at that point bibma+0x2 et bibma+0xa are byte registers
72 * to investigate:
73 */
74 c0 = inb_p((u16)bibma + 0x02);
75 c1 = inb_p((u16)bibma + 0x0a);
76 p += sprintf(p, "\nController: %d\n", i);
77 p += sprintf(p, "--------------- Primary Channel "
78 "---------------- Secondary Channel "
79 "-------------\n");
80 p += sprintf(p, " %sabled "
81 " %sabled\n",
82 (c0&0x80) ? "dis" : " en",
83 (c1&0x80) ? "dis" : " en");
84 p += sprintf(p, "--------------- drive0 --------- drive1 "
85 "-------- drive0 ---------- drive1 ------\n");
86 p += sprintf(p, "DMA enabled: %s %s"
87 " %s %s\n",
88 (c0&0x20) ? "yes" : "no ",
89 (c0&0x40) ? "yes" : "no ",
90 (c1&0x20) ? "yes" : "no ",
91 (c1&0x40) ? "yes" : "no " );
92
93 p += sprintf(p, "UDMA\n");
94 p += sprintf(p, "DMA\n");
95 p += sprintf(p, "PIO\n");
96 }
97 p += sprintf(p, "\n");
98
99 /* p - buffer must be less than 4k! */
100 len = (p - buffer) - offset;
101 *addr = buffer + offset;
102
103 return len > count ? count : len;
104 }
105 #endif /* defined(DISPLAY_HPT34X_TIMINGS) && defined(CONFIG_PROC_FS) */
106
hpt34x_ratemask(ide_drive_t * drive)107 static u8 hpt34x_ratemask (ide_drive_t *drive)
108 {
109 return 1;
110 }
111
hpt34x_clear_chipset(ide_drive_t * drive)112 static void hpt34x_clear_chipset (ide_drive_t *drive)
113 {
114 struct pci_dev *dev = HWIF(drive)->pci_dev;
115 u32 reg1 = 0, tmp1 = 0, reg2 = 0, tmp2 = 0;
116
117 pci_read_config_dword(dev, 0x44, ®1);
118 pci_read_config_dword(dev, 0x48, ®2);
119 tmp1 = ((0x00 << (3*drive->dn)) | (reg1 & ~(7 << (3*drive->dn))));
120 tmp2 = (reg2 & ~(0x11 << drive->dn));
121 pci_write_config_dword(dev, 0x44, tmp1);
122 pci_write_config_dword(dev, 0x48, tmp2);
123 }
124
hpt34x_tune_chipset(ide_drive_t * drive,u8 xferspeed)125 static int hpt34x_tune_chipset (ide_drive_t *drive, u8 xferspeed)
126 {
127 struct pci_dev *dev = HWIF(drive)->pci_dev;
128 u8 speed = ide_rate_filter(hpt34x_ratemask(drive), xferspeed);
129 u32 reg1= 0, tmp1 = 0, reg2 = 0, tmp2 = 0;
130 u8 hi_speed, lo_speed;
131
132 SPLIT_BYTE(speed, hi_speed, lo_speed);
133
134 if (hi_speed & 7) {
135 hi_speed = (hi_speed & 4) ? 0x01 : 0x10;
136 } else {
137 lo_speed <<= 5;
138 lo_speed >>= 5;
139 }
140
141 pci_read_config_dword(dev, 0x44, ®1);
142 pci_read_config_dword(dev, 0x48, ®2);
143 tmp1 = ((lo_speed << (3*drive->dn)) | (reg1 & ~(7 << (3*drive->dn))));
144 tmp2 = ((hi_speed << drive->dn) | reg2);
145 pci_write_config_dword(dev, 0x44, tmp1);
146 pci_write_config_dword(dev, 0x48, tmp2);
147
148 #if HPT343_DEBUG_DRIVE_INFO
149 printk("%s: %s drive%d (0x%04x 0x%04x) (0x%04x 0x%04x)" \
150 " (0x%02x 0x%02x)\n",
151 drive->name, ide_xfer_verbose(speed),
152 drive->dn, reg1, tmp1, reg2, tmp2,
153 hi_speed, lo_speed);
154 #endif /* HPT343_DEBUG_DRIVE_INFO */
155
156 return(ide_config_drive_speed(drive, speed));
157 }
158
hpt34x_tune_drive(ide_drive_t * drive,u8 pio)159 static void hpt34x_tune_drive (ide_drive_t *drive, u8 pio)
160 {
161 pio = ide_get_best_pio_mode(drive, pio, 5, NULL);
162 hpt34x_clear_chipset(drive);
163 (void) hpt34x_tune_chipset(drive, (XFER_PIO_0 + pio));
164 }
165
166 /*
167 * This allows the configuration of ide_pci chipset registers
168 * for cards that learn about the drive's UDMA, DMA, PIO capabilities
169 * after the drive is reported by the OS. Initially for designed for
170 * HPT343 UDMA chipset by HighPoint|Triones Technologies, Inc.
171 */
172
config_chipset_for_dma(ide_drive_t * drive)173 static int config_chipset_for_dma (ide_drive_t *drive)
174 {
175 u8 speed = ide_dma_speed(drive, hpt34x_ratemask(drive));
176
177 if (!(speed))
178 return 0;
179
180 hpt34x_clear_chipset(drive);
181 (void) hpt34x_tune_chipset(drive, speed);
182 return ide_dma_enable(drive);
183 }
184
hpt34x_config_drive_xfer_rate(ide_drive_t * drive)185 static int hpt34x_config_drive_xfer_rate (ide_drive_t *drive)
186 {
187 ide_hwif_t *hwif = HWIF(drive);
188 struct hd_driveid *id = drive->id;
189
190 drive->init_speed = 0;
191
192 if ((id->capability & 1) && drive->autodma) {
193 /* Consult the list of known "bad" drives */
194 if (hwif->ide_dma_bad_drive(drive))
195 goto fast_ata_pio;
196 if (id->field_valid & 4) {
197 if (id->dma_ultra & hwif->ultra_mask) {
198 /* Force if Capable UltraDMA */
199 int dma = config_chipset_for_dma(drive);
200 if ((id->field_valid & 2) && dma)
201 goto try_dma_modes;
202 }
203 } else if (id->field_valid & 2) {
204 try_dma_modes:
205 if ((id->dma_mword & hwif->mwdma_mask) ||
206 (id->dma_1word & hwif->swdma_mask)) {
207 /* Force if Capable regular DMA modes */
208 if (!config_chipset_for_dma(drive))
209 goto no_dma_set;
210 }
211 } else if (hwif->ide_dma_good_drive(drive) &&
212 (id->eide_dma_time < 150)) {
213 /* Consult the list of known "good" drives */
214 if (!config_chipset_for_dma(drive))
215 goto no_dma_set;
216 } else {
217 goto fast_ata_pio;
218 }
219 #ifndef CONFIG_HPT34X_AUTODMA
220 return hwif->ide_dma_off_quietly(drive);
221 #else
222 return hwif->ide_dma_on(drive);
223 #endif
224 } else if ((id->capability & 8) || (id->field_valid & 2)) {
225 fast_ata_pio:
226 no_dma_set:
227 hpt34x_tune_drive(drive, 255);
228 return hwif->ide_dma_off_quietly(drive);
229 }
230 /* IORDY not supported */
231 return 0;
232 }
233
234 /*
235 * If the BIOS does not set the IO base addaress to XX00, 343 will fail.
236 */
237 #define HPT34X_PCI_INIT_REG 0x80
238
init_chipset_hpt34x(struct pci_dev * dev,const char * name)239 static unsigned int __init init_chipset_hpt34x (struct pci_dev *dev, const char *name)
240 {
241 int i = 0;
242 unsigned long hpt34xIoBase = pci_resource_start(dev, 4);
243 unsigned long hpt_addr[4] = { 0x20, 0x34, 0x28, 0x3c };
244 unsigned long hpt_addr_len[4] = { 7, 3, 7, 3 };
245 u16 cmd;
246 unsigned long flags;
247
248 local_irq_save(flags);
249
250 pci_write_config_byte(dev, HPT34X_PCI_INIT_REG, 0x00);
251 pci_read_config_word(dev, PCI_COMMAND, &cmd);
252
253 if (cmd & PCI_COMMAND_MEMORY) {
254 if (pci_resource_start(dev, PCI_ROM_RESOURCE)) {
255 pci_write_config_byte(dev, PCI_ROM_ADDRESS,
256 dev->resource[PCI_ROM_RESOURCE].start | PCI_ROM_ADDRESS_ENABLE);
257 printk(KERN_INFO "HPT345: ROM enabled at 0x%08lx\n",
258 dev->resource[PCI_ROM_RESOURCE].start);
259 }
260 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0xF0);
261 } else {
262 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x20);
263 }
264
265 /*
266 * Since 20-23 can be assigned and are R/W, we correct them.
267 */
268 pci_write_config_word(dev, PCI_COMMAND, cmd & ~PCI_COMMAND_IO);
269 for(i=0; i<4; i++) {
270 dev->resource[i].start = (hpt34xIoBase + hpt_addr[i]);
271 dev->resource[i].end = dev->resource[i].start + hpt_addr_len[i];
272 dev->resource[i].flags = IORESOURCE_IO;
273 pci_write_config_dword(dev,
274 (PCI_BASE_ADDRESS_0 + (i * 4)),
275 dev->resource[i].start);
276 }
277 pci_write_config_word(dev, PCI_COMMAND, cmd);
278
279 local_irq_restore(flags);
280
281 #if defined(DISPLAY_HPT34X_TIMINGS) && defined(CONFIG_PROC_FS)
282 hpt34x_devs[n_hpt34x_devs++] = dev;
283
284 if (!hpt34x_proc) {
285 hpt34x_proc = 1;
286 ide_pci_register_host_proc(&hpt34x_procs[0]);
287 }
288 #endif /* DISPLAY_HPT34X_TIMINGS && CONFIG_PROC_FS */
289
290 return dev->irq;
291 }
292
init_hwif_hpt34x(ide_hwif_t * hwif)293 static void __init init_hwif_hpt34x (ide_hwif_t *hwif)
294 {
295 u16 pcicmd = 0;
296
297 hwif->autodma = 0;
298
299 hwif->tuneproc = &hpt34x_tune_drive;
300 hwif->speedproc = &hpt34x_tune_chipset;
301 hwif->no_dsc = 1;
302 hwif->drives[0].autotune = 1;
303 hwif->drives[1].autotune = 1;
304
305 pci_read_config_word(hwif->pci_dev, PCI_COMMAND, &pcicmd);
306
307 if (!hwif->dma_base)
308 return;
309
310 hwif->ultra_mask = 0x07;
311 hwif->mwdma_mask = 0x07;
312 hwif->swdma_mask = 0x07;
313
314 hwif->ide_dma_check = &hpt34x_config_drive_xfer_rate;
315 if (!noautodma)
316 hwif->autodma = (pcicmd & PCI_COMMAND_MEMORY) ? 1 : 0;
317 hwif->drives[0].autodma = hwif->autodma;
318 hwif->drives[1].autodma = hwif->autodma;
319 }
320
init_dma_hpt34x(ide_hwif_t * hwif,unsigned long dmabase)321 static void __init init_dma_hpt34x (ide_hwif_t *hwif, unsigned long dmabase)
322 {
323 ide_setup_dma(hwif, dmabase, 8);
324 }
325
326 extern void ide_setup_pci_device(struct pci_dev *, ide_pci_device_t *);
327
hpt34x_init_one(struct pci_dev * dev,const struct pci_device_id * id)328 static int __devinit hpt34x_init_one(struct pci_dev *dev, const struct pci_device_id *id)
329 {
330 ide_pci_device_t *d = &hpt34x_chipsets[id->driver_data];
331 static char *chipset_names[] = {"HPT343", "HPT345"};
332 u16 pcicmd = 0;
333
334 pci_read_config_word(dev, PCI_COMMAND, &pcicmd);
335
336 d->name = chipset_names[(pcicmd & PCI_COMMAND_MEMORY) ? 1 : 0];
337 d->bootable = (pcicmd & PCI_COMMAND_MEMORY) ? OFF_BOARD : NEVER_BOARD;
338
339 ide_setup_pci_device(dev, d);
340 MOD_INC_USE_COUNT;
341 return 0;
342 }
343
344 static struct pci_device_id hpt34x_pci_tbl[] __devinitdata = {
345 { PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT343, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
346 { 0, },
347 };
348
349 static struct pci_driver driver = {
350 .name = "HPT34x IDE",
351 .id_table = hpt34x_pci_tbl,
352 .probe = hpt34x_init_one,
353 };
354
hpt34x_ide_init(void)355 static int hpt34x_ide_init(void)
356 {
357 return ide_pci_register_driver(&driver);
358 }
359
hpt34x_ide_exit(void)360 static void hpt34x_ide_exit(void)
361 {
362 ide_pci_unregister_driver(&driver);
363 }
364
365 module_init(hpt34x_ide_init);
366 module_exit(hpt34x_ide_exit);
367
368 MODULE_AUTHOR("Andre Hedrick");
369 MODULE_DESCRIPTION("PCI driver module for Highpoint 34x IDE");
370 MODULE_LICENSE("GPL");
371
372 EXPORT_NO_SYMBOLS;
373