1 /*
2 * eisa.c - provide support for EISA adapters in PA-RISC machines
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version
7 * 2 of the License, or (at your option) any later version.
8 *
9 * Copyright (c) 2001 Matthew Wilcox for Hewlett Packard
10 * Copyright (c) 2001 Daniel Engstrom <5116@telia.com>
11 *
12 * There are two distinct EISA adapters. Mongoose is found in machines
13 * before the 712; then the Wax ASIC is used. To complicate matters, the
14 * Wax ASIC also includes a PS/2 and RS-232 controller, but those are
15 * dealt with elsewhere; this file is concerned only with the EISA portions
16 * of Wax.
17 *
18 *
19 * HINT:
20 * -----
21 * To allow an ISA card to work properly in the EISA slot you need to
22 * set an edge trigger level. This may be done on the palo command line
23 * by adding the kernel parameter "eisa_irq_edge=n,n2,[...]]", with
24 * n and n2 as the irq levels you want to use.
25 *
26 * Example: "eisa_irq_edge=10,11" allows ISA cards to operate at
27 * irq levels 10 and 11.
28 */
29
30 #include <linux/init.h>
31 #include <linux/ioport.h>
32 #include <linux/irq.h>
33 #include <linux/kernel.h>
34 #include <linux/module.h>
35 #include <linux/pci.h>
36 #include <linux/sched.h>
37 #include <linux/spinlock.h>
38
39 #include <asm/byteorder.h>
40 #include <asm/gsc.h>
41 #include <asm/hardware.h>
42 #include <asm/processor.h>
43 #include <asm/delay.h>
44 #include <asm/eisa_bus.h>
45
46 #if 0
47 #define EISA_DBG(msg, arg... ) printk(KERN_DEBUG "eisa: " msg , ## arg )
48 #else
49 #define EISA_DBG(msg, arg... )
50 #endif
51
52 #define SNAKES_EEPROM_BASE_ADDR 0xF0810400
53 #define MIRAGE_EEPROM_BASE_ADDR 0xF00C0400
54
55 static spinlock_t eisa_irq_lock = SPIN_LOCK_UNLOCKED;
56
57 /* We can only have one EISA adapter in the system because neither
58 * implementation can be flexed.
59 */
60 static struct eisa_ba {
61 struct pci_hba_data hba;
62 unsigned long eeprom_addr;
63 } eisa_dev;
64
65 /* Port ops */
66
eisa_permute(unsigned short port)67 static inline unsigned long eisa_permute(unsigned short port)
68 {
69 if (port & 0x300) {
70 return 0xfc000000 | ((port & 0xfc00) >> 6)
71 | ((port & 0x3f8) << 9) | (port & 7);
72 } else {
73 return 0xfc000000 | port;
74 }
75 }
76
eisa_in8(unsigned short port)77 unsigned char eisa_in8(unsigned short port)
78 {
79 if (EISA_bus)
80 return gsc_readb(eisa_permute(port));
81 return 0xff;
82 }
83
eisa_in16(unsigned short port)84 unsigned short eisa_in16(unsigned short port)
85 {
86 if (EISA_bus)
87 return le16_to_cpu(gsc_readw(eisa_permute(port)));
88 return 0xffff;
89 }
90
eisa_in32(unsigned short port)91 unsigned int eisa_in32(unsigned short port)
92 {
93 if (EISA_bus)
94 return le32_to_cpu(gsc_readl(eisa_permute(port)));
95 return 0xffffffff;
96 }
97
eisa_out8(unsigned char data,unsigned short port)98 void eisa_out8(unsigned char data, unsigned short port)
99 {
100 if (EISA_bus)
101 gsc_writeb(data, eisa_permute(port));
102 }
103
eisa_out16(unsigned short data,unsigned short port)104 void eisa_out16(unsigned short data, unsigned short port)
105 {
106 if (EISA_bus)
107 gsc_writew(cpu_to_le16(data), eisa_permute(port));
108 }
109
eisa_out32(unsigned int data,unsigned short port)110 void eisa_out32(unsigned int data, unsigned short port)
111 {
112 if (EISA_bus)
113 gsc_writel(cpu_to_le32(data), eisa_permute(port));
114 }
115
116 /* Interrupt handling */
117
118 /* cached interrupt mask registers */
119 static int master_mask;
120 static int slave_mask;
121
122 /* the trig level can be set with the
123 * eisa_irq_edge=n,n,n commandline parameter
124 * We should really read this from the EEPROM
125 * in the furure.
126 */
127 /* irq 13,8,2,1,0 must be edge */
128 static unsigned int eisa_irq_level; /* default to edge triggered */
129
130
131 /* called by free irq */
eisa_disable_irq(void * irq_dev,int irq)132 static void eisa_disable_irq(void *irq_dev, int irq)
133 {
134 unsigned long flags;
135
136 EISA_DBG("disable irq %d\n", irq);
137 /* just mask for now */
138 spin_lock_irqsave(&eisa_irq_lock, flags);
139 if (irq & 8) {
140 slave_mask |= (1 << (irq&7));
141 eisa_out8(slave_mask, 0xa1);
142 } else {
143 master_mask |= (1 << (irq&7));
144 eisa_out8(master_mask, 0x21);
145 }
146 spin_unlock_irqrestore(&eisa_irq_lock, flags);
147 EISA_DBG("pic0 mask %02x\n", eisa_in8(0x21));
148 EISA_DBG("pic1 mask %02x\n", eisa_in8(0xa1));
149 }
150
151 /* called by request irq */
eisa_enable_irq(void * irq_dev,int irq)152 static void eisa_enable_irq(void *irq_dev, int irq)
153 {
154 unsigned long flags;
155 EISA_DBG("enable irq %d\n", irq);
156
157 spin_lock_irqsave(&eisa_irq_lock, flags);
158 if (irq & 8) {
159 slave_mask &= ~(1 << (irq&7));
160 eisa_out8(slave_mask, 0xa1);
161 } else {
162 master_mask &= ~(1 << (irq&7));
163 eisa_out8(master_mask, 0x21);
164 }
165 spin_unlock_irqrestore(&eisa_irq_lock, flags);
166 EISA_DBG("pic0 mask %02x\n", eisa_in8(0x21));
167 EISA_DBG("pic1 mask %02x\n", eisa_in8(0xa1));
168 }
169
eisa_mask_irq(void * irq_dev,int irq)170 static void eisa_mask_irq(void *irq_dev, int irq)
171 {
172 unsigned long flags;
173 EISA_DBG("mask irq %d\n", irq);
174
175 /* mask irq */
176 spin_lock_irqsave(&eisa_irq_lock, flags);
177 if (irq & 8) {
178 slave_mask |= (1 << (irq&7));
179 eisa_out8(slave_mask, 0xa1);
180 } else {
181 master_mask |= (1 << (irq&7));
182 eisa_out8(master_mask, 0x21);
183 }
184 spin_unlock_irqrestore(&eisa_irq_lock, flags);
185 }
186
eisa_unmask_irq(void * irq_dev,int irq)187 static void eisa_unmask_irq(void *irq_dev, int irq)
188 {
189 unsigned long flags;
190 EISA_DBG("unmask irq %d\n", irq);
191
192 /* unmask */
193 spin_lock_irqsave(&eisa_irq_lock, flags);
194 if (irq & 8) {
195 slave_mask &= ~(1 << (irq&7));
196 eisa_out8(slave_mask, 0xa1);
197 } else {
198 master_mask &= ~(1 << (irq&7));
199 eisa_out8(master_mask, 0x21);
200 }
201 spin_unlock_irqrestore(&eisa_irq_lock, flags);
202 }
203
204 static struct irqaction action[IRQ_PER_REGION];
205
206 /* EISA needs to be fixed at IRQ region #0 (EISA_IRQ_REGION) */
207 static struct irq_region eisa_irq_region = {
208 ops: { eisa_disable_irq, eisa_enable_irq, eisa_mask_irq, eisa_unmask_irq },
209 data: { name: "EISA", irqbase: 0 },
210 action: action,
211 };
212
eisa_irq(int _,void * intr_dev,struct pt_regs * regs)213 static void eisa_irq(int _, void *intr_dev, struct pt_regs *regs)
214 {
215 extern void do_irq(struct irqaction *a, int i, struct pt_regs *p);
216 int irq = gsc_readb(0xfc01f000); /* EISA supports 16 irqs */
217 unsigned long flags;
218
219 spin_lock_irqsave(&eisa_irq_lock, flags);
220 /* read IRR command */
221 eisa_out8(0x0a, 0x20);
222 eisa_out8(0x0a, 0xa0);
223
224 EISA_DBG("irq IAR %02x 8259-1 irr %02x 8259-2 irr %02x\n",
225 irq, eisa_in8(0x20), eisa_in8(0xa0));
226
227 /* read ISR command */
228 eisa_out8(0x0a, 0x20);
229 eisa_out8(0x0a, 0xa0);
230 EISA_DBG("irq 8259-1 isr %02x imr %02x 8259-2 isr %02x imr %02x\n",
231 eisa_in8(0x20), eisa_in8(0x21), eisa_in8(0xa0), eisa_in8(0xa1));
232
233 irq &= 0xf;
234
235 /* mask irq and write eoi */
236 if (irq & 8) {
237 slave_mask |= (1 << (irq&7));
238 eisa_out8(slave_mask, 0xa1);
239 eisa_out8(0x60 | (irq&7),0xa0);/* 'Specific EOI' to slave */
240 eisa_out8(0x62,0x20); /* 'Specific EOI' to master-IRQ2 */
241
242 } else {
243 master_mask |= (1 << (irq&7));
244 eisa_out8(master_mask, 0x21);
245 eisa_out8(0x60|irq,0x20); /* 'Specific EOI' to master */
246 }
247 spin_unlock_irqrestore(&eisa_irq_lock, flags);
248
249
250 do_irq(&eisa_irq_region.action[irq], EISA_IRQ_REGION + irq, regs);
251
252 spin_lock_irqsave(&eisa_irq_lock, flags);
253 /* unmask */
254 if (irq & 8) {
255 slave_mask &= ~(1 << (irq&7));
256 eisa_out8(slave_mask, 0xa1);
257 } else {
258 master_mask &= ~(1 << (irq&7));
259 eisa_out8(master_mask, 0x21);
260 }
261 spin_unlock_irqrestore(&eisa_irq_lock, flags);
262 }
263
dummy_irq2_handler(int _,void * dev,struct pt_regs * regs)264 static void dummy_irq2_handler(int _, void *dev, struct pt_regs *regs)
265 {
266 printk(KERN_ALERT "eisa: uhh, irq2?\n");
267 }
268
init_eisa_pic(void)269 static void init_eisa_pic(void)
270 {
271 unsigned long flags;
272
273 spin_lock_irqsave(&eisa_irq_lock, flags);
274
275 eisa_out8(0xff, 0x21); /* mask during init */
276 eisa_out8(0xff, 0xa1); /* mask during init */
277
278 /* master pic */
279 eisa_out8(0x11,0x20); /* ICW1 */
280 eisa_out8(0x00,0x21); /* ICW2 */
281 eisa_out8(0x04,0x21); /* ICW3 */
282 eisa_out8(0x01,0x21); /* ICW4 */
283 eisa_out8(0x40,0x20); /* OCW2 */
284
285 /* slave pic */
286 eisa_out8(0x11,0xa0); /* ICW1 */
287 eisa_out8(0x08,0xa1); /* ICW2 */
288 eisa_out8(0x02,0xa1); /* ICW3 */
289 eisa_out8(0x01,0xa1); /* ICW4 */
290 eisa_out8(0x40,0xa0); /* OCW2 */
291
292 udelay(100);
293
294 slave_mask = 0xff;
295 master_mask = 0xfb;
296 eisa_out8(slave_mask, 0xa1); /* OCW1 */
297 eisa_out8(master_mask, 0x21); /* OCW1 */
298
299 /* setup trig level */
300 EISA_DBG("EISA edge/level %04x\n", eisa_irq_level);
301
302 eisa_out8(eisa_irq_level&0xff, 0x4d0); /* Set all irq's to edge */
303 eisa_out8((eisa_irq_level >> 8) & 0xff, 0x4d1);
304
305 EISA_DBG("pic0 mask %02x\n", eisa_in8(0x21));
306 EISA_DBG("pic1 mask %02x\n", eisa_in8(0xa1));
307 EISA_DBG("pic0 edge/level %02x\n", eisa_in8(0x4d0));
308 EISA_DBG("pic1 edge/level %02x\n", eisa_in8(0x4d1));
309
310 spin_unlock_irqrestore(&eisa_irq_lock, flags);
311 }
312
313 /* Device initialisation */
314
315 #define is_mongoose(dev) (dev->id.sversion == 0x00076)
316
eisa_probe(struct parisc_device * dev)317 static int __devinit eisa_probe(struct parisc_device *dev)
318 {
319 int result;
320
321 char *name = is_mongoose(dev) ? "Mongoose" : "Wax";
322
323 printk(KERN_INFO "%s EISA Adapter found at 0x%08lx\n",
324 name, dev->hpa);
325
326 eisa_dev.hba.dev = dev;
327 eisa_dev.hba.iommu = ccio_get_iommu(dev);
328
329 eisa_dev.hba.lmmio_space.name = "EISA";
330 eisa_dev.hba.lmmio_space.start = (unsigned long) 0xfffffffffc000000;
331 eisa_dev.hba.lmmio_space.end = (unsigned long) 0xffffffffffbfffff;
332 eisa_dev.hba.lmmio_space.flags = IORESOURCE_MEM;
333 result = ccio_request_resource(dev, &eisa_dev.hba.lmmio_space);
334 if (result < 0) {
335 printk(KERN_ERR "EISA: failed to claim EISA Bus address space!\n");
336 return result;
337 }
338 eisa_dev.hba.io_space.name = "EISA";
339 eisa_dev.hba.io_space.start = 0;
340 eisa_dev.hba.io_space.end = 0xffff;
341 eisa_dev.hba.lmmio_space.flags = IORESOURCE_IO;
342 result = request_resource(&ioport_resource, &eisa_dev.hba.io_space);
343 if (result < 0) {
344 printk(KERN_ERR "EISA: failed to claim EISA Bus port space!\n");
345 return result;
346 }
347 pcibios_register_hba(&eisa_dev.hba);
348
349 result = request_irq(dev->irq, eisa_irq, SA_SHIRQ, "EISA", NULL);
350 if (result) {
351 printk(KERN_ERR "EISA: request_irq failed!\n");
352 return result;
353 }
354
355 /* Reserve IRQ2 */
356 action[2].handler = dummy_irq2_handler;
357 action[2].name = "cascade";
358
359 eisa_irq_region.data.dev = dev;
360 irq_region[0] = &eisa_irq_region;
361
362 EISA_bus = 1;
363 if (dev->num_addrs) {
364 /* newer firmware hand out the eeprom address */
365 eisa_dev.eeprom_addr = dev->addr[0];
366 } else {
367 /* old firmware, need to figure out the box */
368 if (is_mongoose(dev)) {
369 eisa_dev.eeprom_addr = SNAKES_EEPROM_BASE_ADDR;
370 } else {
371 eisa_dev.eeprom_addr = MIRAGE_EEPROM_BASE_ADDR;
372 }
373 }
374 eisa_eeprom_init(eisa_dev.eeprom_addr);
375 eisa_enumerator(eisa_dev.eeprom_addr, &eisa_dev.hba.io_space, &eisa_dev.hba.lmmio_space);
376 init_eisa_pic();
377
378 return 0;
379 }
380
381 static struct parisc_device_id __devinitdata eisa_tbl[] = {
382 { HPHW_BA, HVERSION_REV_ANY_ID, HVERSION_ANY_ID, 0x00076 }, /* Mongoose */
383 { HPHW_BA, HVERSION_REV_ANY_ID, HVERSION_ANY_ID, 0x00090 }, /* Wax EISA */
384 { 0, }
385 };
386
387 MODULE_DEVICE_TABLE(parisc, eisa_tbl);
388
389 static struct parisc_driver eisa_driver = {
390 name: "EISA Bus Adapter",
391 id_table: eisa_tbl,
392 probe: eisa_probe,
393 };
394
eisa_init(void)395 void __init eisa_init(void)
396 {
397 register_parisc_driver(&eisa_driver);
398 }
399
400
401 static unsigned int eisa_irq_configured;
eisa_make_irq_level(int num)402 void eisa_make_irq_level(int num)
403 {
404 if (eisa_irq_configured& (1<<num)) {
405 printk(KERN_WARNING
406 "IRQ %d polarity configured twice (last to level)\n",
407 num);
408 }
409 eisa_irq_level |= (1<<num); /* set the corresponding bit */
410 eisa_irq_configured |= (1<<num); /* set the corresponding bit */
411 }
412
eisa_make_irq_edge(int num)413 void eisa_make_irq_edge(int num)
414 {
415 if (eisa_irq_configured& (1<<num)) {
416 printk(KERN_WARNING
417 "IRQ %d polarity configured twice (last to edge)\n",
418 num);
419 }
420 eisa_irq_level &= ~(1<<num); /* clear the corresponding bit */
421 eisa_irq_configured |= (1<<num); /* set the corresponding bit */
422 }
423
eisa_irq_setup(char * str)424 static int __init eisa_irq_setup(char *str)
425 {
426 char *cur = str;
427 int val;
428
429 EISA_DBG("IRQ setup\n");
430 while (cur != NULL) {
431 char *pe;
432
433 val = (int) simple_strtoul(cur, &pe, 0);
434 if (val > 15 || val < 0) {
435 printk(KERN_ERR "eisa: EISA irq value are 0-15\n");
436 continue;
437 }
438 if (val == 2) {
439 val = 9;
440 }
441 eisa_make_irq_edge(val); /* clear the corresponding bit */
442 EISA_DBG("setting IRQ %d to edge-triggered mode\n", val);
443
444 if ((cur = strchr(cur, ','))) {
445 cur++;
446 } else {
447 break;
448 }
449 }
450 return 1;
451 }
452
453 __setup("eisa_irq_edge=", eisa_irq_setup);
454
455