1 /*
2 * $Id: synclinkmp.c,v 3.27 2005/02/15 21:29:09 paulkf Exp $
3 *
4 * Device driver for Microgate SyncLink Multiport
5 * high speed multiprotocol serial adapter.
6 *
7 * written by Paul Fulghum for Microgate Corporation
8 * paulkf@microgate.com
9 *
10 * Microgate and SyncLink are trademarks of Microgate Corporation
11 *
12 * Derived from serial.c written by Theodore Ts'o and Linus Torvalds
13 * This code is released under the GNU General Public License (GPL)
14 *
15 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
16 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
18 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
19 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
20 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
21 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
23 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
25 * OF THE POSSIBILITY OF SUCH DAMAGE.
26 */
27
28 #define VERSION(ver,rel,seq) (((ver)<<16) | ((rel)<<8) | (seq))
29 #if defined(__i386__)
30 # define BREAKPOINT() asm(" int $3");
31 #else
32 # define BREAKPOINT() { }
33 #endif
34
35 #define MAX_DEVICES 12
36
37 #include <linux/config.h>
38 #include <linux/module.h>
39 #include <linux/version.h>
40 #include <linux/errno.h>
41 #include <linux/signal.h>
42 #include <linux/sched.h>
43 #include <linux/timer.h>
44 #include <linux/interrupt.h>
45 #include <linux/pci.h>
46 #include <linux/tty.h>
47 #include <linux/tty_flip.h>
48 #include <linux/serial.h>
49 #include <linux/major.h>
50 #include <linux/string.h>
51 #include <linux/fcntl.h>
52 #include <linux/ptrace.h>
53 #include <linux/ioport.h>
54 #include <linux/mm.h>
55 #include <linux/slab.h>
56 #include <linux/netdevice.h>
57 #include <linux/vmalloc.h>
58 #include <linux/init.h>
59 #include <asm/serial.h>
60 #include <linux/delay.h>
61 #include <linux/ioctl.h>
62
63 #include <asm/system.h>
64 #include <asm/io.h>
65 #include <asm/irq.h>
66 #include <asm/dma.h>
67 #include <asm/bitops.h>
68 #include <asm/types.h>
69 #include <linux/termios.h>
70 #include <linux/tqueue.h>
71
72 #ifdef CONFIG_SYNCLINK_SYNCPPP_MODULE
73 #define CONFIG_SYNCLINK_SYNCPPP 1
74 #endif
75
76 #ifdef CONFIG_SYNCLINK_SYNCPPP
77 #include <net/syncppp.h>
78 #endif
79
80 #include <asm/segment.h>
81 #define GET_USER(error,value,addr) error = get_user(value,addr)
82 #define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0
83 #define PUT_USER(error,value,addr) error = put_user(value,addr)
84 #define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0
85
86 #include <asm/uaccess.h>
87
88 #include "linux/synclink.h"
89
90 static MGSL_PARAMS default_params = {
91 MGSL_MODE_HDLC, /* unsigned long mode */
92 0, /* unsigned char loopback; */
93 HDLC_FLAG_UNDERRUN_ABORT15, /* unsigned short flags; */
94 HDLC_ENCODING_NRZI_SPACE, /* unsigned char encoding; */
95 0, /* unsigned long clock_speed; */
96 0xff, /* unsigned char addr_filter; */
97 HDLC_CRC_16_CCITT, /* unsigned short crc_type; */
98 HDLC_PREAMBLE_LENGTH_8BITS, /* unsigned char preamble_length; */
99 HDLC_PREAMBLE_PATTERN_NONE, /* unsigned char preamble; */
100 9600, /* unsigned long data_rate; */
101 8, /* unsigned char data_bits; */
102 1, /* unsigned char stop_bits; */
103 ASYNC_PARITY_NONE /* unsigned char parity; */
104 };
105
106 /* size in bytes of DMA data buffers */
107 #define SCABUFSIZE 1024
108 #define SCA_MEM_SIZE 0x40000
109 #define SCA_BASE_SIZE 512
110 #define SCA_REG_SIZE 16
111 #define SCA_MAX_PORTS 4
112 #define SCAMAXDESC 128
113
114 #define BUFFERLISTSIZE 4096
115
116 /* SCA-I style DMA buffer descriptor */
117 typedef struct _SCADESC
118 {
119 u16 next; /* lower l6 bits of next descriptor addr */
120 u16 buf_ptr; /* lower 16 bits of buffer addr */
121 u8 buf_base; /* upper 8 bits of buffer addr */
122 u8 pad1;
123 u16 length; /* length of buffer */
124 u8 status; /* status of buffer */
125 u8 pad2;
126 } SCADESC, *PSCADESC;
127
128 typedef struct _SCADESC_EX
129 {
130 /* device driver bookkeeping section */
131 char *virt_addr; /* virtual address of data buffer */
132 u16 phys_entry; /* lower 16-bits of physical address of this descriptor */
133 } SCADESC_EX, *PSCADESC_EX;
134
135 /* The queue of BH actions to be performed */
136
137 #define BH_RECEIVE 1
138 #define BH_TRANSMIT 2
139 #define BH_STATUS 4
140
141 #define IO_PIN_SHUTDOWN_LIMIT 100
142
143 #define RELEVANT_IFLAG(iflag) (iflag & (IGNBRK|BRKINT|IGNPAR|PARMRK|INPCK))
144
145 struct _input_signal_events {
146 int ri_up;
147 int ri_down;
148 int dsr_up;
149 int dsr_down;
150 int dcd_up;
151 int dcd_down;
152 int cts_up;
153 int cts_down;
154 };
155
156 /*
157 * Device instance data structure
158 */
159 typedef struct _synclinkmp_info {
160 void *if_ptr; /* General purpose pointer (used by SPPP) */
161 int magic;
162 int flags;
163 int count; /* count of opens */
164 int line;
165 unsigned short close_delay;
166 unsigned short closing_wait; /* time to wait before closing */
167
168 struct mgsl_icount icount;
169
170 struct termios normal_termios;
171 struct termios callout_termios;
172
173 struct tty_struct *tty;
174 int timeout;
175 int x_char; /* xon/xoff character */
176 int blocked_open; /* # of blocked opens */
177 long session; /* Session of opening process */
178 long pgrp; /* pgrp of opening process */
179 u16 read_status_mask1; /* break detection (SR1 indications) */
180 u16 read_status_mask2; /* parity/framing/overun (SR2 indications) */
181 unsigned char ignore_status_mask1; /* break detection (SR1 indications) */
182 unsigned char ignore_status_mask2; /* parity/framing/overun (SR2 indications) */
183 unsigned char *tx_buf;
184 int tx_put;
185 int tx_get;
186 int tx_count;
187
188 wait_queue_head_t open_wait;
189 wait_queue_head_t close_wait;
190
191 wait_queue_head_t status_event_wait_q;
192 wait_queue_head_t event_wait_q;
193 struct timer_list tx_timer; /* HDLC transmit timeout timer */
194 struct _synclinkmp_info *next_device; /* device list link */
195 struct timer_list status_timer; /* input signal status check timer */
196
197 spinlock_t lock; /* spinlock for synchronizing with ISR */
198 struct tq_struct task; /* task structure for scheduling bh */
199
200 u32 max_frame_size; /* as set by device config */
201
202 u32 pending_bh;
203
204 int bh_running; /* Protection from multiple */
205 int isr_overflow;
206 int bh_requested;
207
208 int dcd_chkcount; /* check counts to prevent */
209 int cts_chkcount; /* too many IRQs if a signal */
210 int dsr_chkcount; /* is floating */
211 int ri_chkcount;
212
213 char *buffer_list; /* virtual address of Rx & Tx buffer lists */
214 unsigned long buffer_list_phys;
215
216 unsigned int rx_buf_count; /* count of total allocated Rx buffers */
217 SCADESC *rx_buf_list; /* list of receive buffer entries */
218 SCADESC_EX rx_buf_list_ex[SCAMAXDESC]; /* list of receive buffer entries */
219 unsigned int current_rx_buf;
220
221 unsigned int tx_buf_count; /* count of total allocated Tx buffers */
222 SCADESC *tx_buf_list; /* list of transmit buffer entries */
223 SCADESC_EX tx_buf_list_ex[SCAMAXDESC]; /* list of transmit buffer entries */
224 unsigned int last_tx_buf;
225
226 unsigned char *tmp_rx_buf;
227 unsigned int tmp_rx_buf_count;
228
229 int rx_enabled;
230 int rx_overflow;
231
232 int tx_enabled;
233 int tx_active;
234 u32 idle_mode;
235
236 unsigned char ie0_value;
237 unsigned char ie1_value;
238 unsigned char ie2_value;
239 unsigned char ctrlreg_value;
240 unsigned char old_signals;
241
242 char device_name[25]; /* device instance name */
243
244 int port_count;
245 int adapter_num;
246 int port_num;
247
248 struct _synclinkmp_info *port_array[SCA_MAX_PORTS];
249
250 unsigned int bus_type; /* expansion bus type (ISA,EISA,PCI) */
251
252 unsigned int irq_level; /* interrupt level */
253 unsigned long irq_flags;
254 int irq_requested; /* nonzero if IRQ requested */
255
256 MGSL_PARAMS params; /* communications parameters */
257
258 unsigned char serial_signals; /* current serial signal states */
259
260 int irq_occurred; /* for diagnostics use */
261 unsigned int init_error; /* Initialization startup error */
262
263 u32 last_mem_alloc;
264 unsigned char* memory_base; /* shared memory address (PCI only) */
265 u32 phys_memory_base;
266 int shared_mem_requested;
267
268 unsigned char* sca_base; /* HD64570 SCA Memory address */
269 u32 phys_sca_base;
270 u32 sca_offset;
271 int sca_base_requested;
272
273 unsigned char* lcr_base; /* local config registers (PCI only) */
274 u32 phys_lcr_base;
275 u32 lcr_offset;
276 int lcr_mem_requested;
277
278 unsigned char* statctrl_base; /* status/control register memory */
279 u32 phys_statctrl_base;
280 u32 statctrl_offset;
281 int sca_statctrl_requested;
282
283 u32 misc_ctrl_value;
284 char flag_buf[MAX_ASYNC_BUFFER_SIZE];
285 char char_buf[MAX_ASYNC_BUFFER_SIZE];
286 BOOLEAN drop_rts_on_tx_done;
287
288 struct _input_signal_events input_signal_events;
289
290 /* SPPP/Cisco HDLC device parts */
291 int netcount;
292 int dosyncppp;
293 spinlock_t netlock;
294 #ifdef CONFIG_SYNCLINK_SYNCPPP
295 struct ppp_device pppdev;
296 char netname[10];
297 struct net_device *netdev;
298 struct net_device_stats netstats;
299 struct net_device netdevice;
300 #endif
301 } SLMP_INFO;
302
303 #define MGSL_MAGIC 0x5401
304
305 /*
306 * define serial signal status change macros
307 */
308 #define MISCSTATUS_DCD_LATCHED (SerialSignal_DCD<<8) /* indicates change in DCD */
309 #define MISCSTATUS_RI_LATCHED (SerialSignal_RI<<8) /* indicates change in RI */
310 #define MISCSTATUS_CTS_LATCHED (SerialSignal_CTS<<8) /* indicates change in CTS */
311 #define MISCSTATUS_DSR_LATCHED (SerialSignal_DSR<<8) /* change in DSR */
312
313 /* Common Register macros */
314 #define LPR 0x00
315 #define PABR0 0x02
316 #define PABR1 0x03
317 #define WCRL 0x04
318 #define WCRM 0x05
319 #define WCRH 0x06
320 #define DPCR 0x08
321 #define DMER 0x09
322 #define ISR0 0x10
323 #define ISR1 0x11
324 #define ISR2 0x12
325 #define IER0 0x14
326 #define IER1 0x15
327 #define IER2 0x16
328 #define ITCR 0x18
329 #define INTVR 0x1a
330 #define IMVR 0x1c
331
332 /* MSCI Register macros */
333 #define TRB 0x20
334 #define TRBL 0x20
335 #define TRBH 0x21
336 #define SR0 0x22
337 #define SR1 0x23
338 #define SR2 0x24
339 #define SR3 0x25
340 #define FST 0x26
341 #define IE0 0x28
342 #define IE1 0x29
343 #define IE2 0x2a
344 #define FIE 0x2b
345 #define CMD 0x2c
346 #define MD0 0x2e
347 #define MD1 0x2f
348 #define MD2 0x30
349 #define CTL 0x31
350 #define SA0 0x32
351 #define SA1 0x33
352 #define IDL 0x34
353 #define TMC 0x35
354 #define RXS 0x36
355 #define TXS 0x37
356 #define TRC0 0x38
357 #define TRC1 0x39
358 #define RRC 0x3a
359 #define CST0 0x3c
360 #define CST1 0x3d
361
362 /* Timer Register Macros */
363 #define TCNT 0x60
364 #define TCNTL 0x60
365 #define TCNTH 0x61
366 #define TCONR 0x62
367 #define TCONRL 0x62
368 #define TCONRH 0x63
369 #define TMCS 0x64
370 #define TEPR 0x65
371
372 /* DMA Controller Register macros */
373 #define DAR 0x80
374 #define DARL 0x80
375 #define DARH 0x81
376 #define DARB 0x82
377 #define BAR 0x80
378 #define BARL 0x80
379 #define BARH 0x81
380 #define BARB 0x82
381 #define SAR 0x84
382 #define SARL 0x84
383 #define SARH 0x85
384 #define SARB 0x86
385 #define CPB 0x86
386 #define CDA 0x88
387 #define CDAL 0x88
388 #define CDAH 0x89
389 #define EDA 0x8a
390 #define EDAL 0x8a
391 #define EDAH 0x8b
392 #define BFL 0x8c
393 #define BFLL 0x8c
394 #define BFLH 0x8d
395 #define BCR 0x8e
396 #define BCRL 0x8e
397 #define BCRH 0x8f
398 #define DSR 0x90
399 #define DMR 0x91
400 #define FCT 0x93
401 #define DIR 0x94
402 #define DCMD 0x95
403
404 /* combine with timer or DMA register address */
405 #define TIMER0 0x00
406 #define TIMER1 0x08
407 #define TIMER2 0x10
408 #define TIMER3 0x18
409 #define RXDMA 0x00
410 #define TXDMA 0x20
411
412 /* SCA Command Codes */
413 #define NOOP 0x00
414 #define TXRESET 0x01
415 #define TXENABLE 0x02
416 #define TXDISABLE 0x03
417 #define TXCRCINIT 0x04
418 #define TXCRCEXCL 0x05
419 #define TXEOM 0x06
420 #define TXABORT 0x07
421 #define MPON 0x08
422 #define TXBUFCLR 0x09
423 #define RXRESET 0x11
424 #define RXENABLE 0x12
425 #define RXDISABLE 0x13
426 #define RXCRCINIT 0x14
427 #define RXREJECT 0x15
428 #define SEARCHMP 0x16
429 #define RXCRCEXCL 0x17
430 #define RXCRCCALC 0x18
431 #define CHRESET 0x21
432 #define HUNT 0x31
433
434 /* DMA command codes */
435 #define SWABORT 0x01
436 #define FEICLEAR 0x02
437
438 /* IE0 */
439 #define TXINTE BIT7
440 #define RXINTE BIT6
441 #define TXRDYE BIT1
442 #define RXRDYE BIT0
443
444 /* IE1 & SR1 */
445 #define UDRN BIT7
446 #define IDLE BIT6
447 #define SYNCD BIT4
448 #define FLGD BIT4
449 #define CCTS BIT3
450 #define CDCD BIT2
451 #define BRKD BIT1
452 #define ABTD BIT1
453 #define GAPD BIT1
454 #define BRKE BIT0
455 #define IDLD BIT0
456
457 /* IE2 & SR2 */
458 #define EOM BIT7
459 #define PMP BIT6
460 #define SHRT BIT6
461 #define PE BIT5
462 #define ABT BIT5
463 #define FRME BIT4
464 #define RBIT BIT4
465 #define OVRN BIT3
466 #define CRCE BIT2
467
468
469 #define jiffies_from_ms(a) ((((a) * HZ)/1000)+1)
470
471 /*
472 * Global linked list of SyncLink devices
473 */
474 static SLMP_INFO *synclinkmp_device_list = NULL;
475 static int synclinkmp_adapter_count = -1;
476 static int synclinkmp_device_count = 0;
477
478 /*
479 * Set this param to non-zero to load eax with the
480 * .text section address and breakpoint on module load.
481 * This is useful for use with gdb and add-symbol-file command.
482 */
483 static int break_on_load=0;
484
485 /*
486 * Driver major number, defaults to zero to get auto
487 * assigned major number. May be forced as module parameter.
488 */
489 static int ttymajor=0;
490 static int cuamajor=0;
491
492 /*
493 * Array of user specified options for ISA adapters.
494 */
495 static int debug_level = 0;
496 static int maxframe[MAX_DEVICES] = {0,};
497 static int dosyncppp[MAX_DEVICES] = {0,};
498
499 MODULE_PARM(break_on_load,"i");
500 MODULE_PARM(ttymajor,"i");
501 MODULE_PARM(cuamajor,"i");
502 MODULE_PARM(debug_level,"i");
503 MODULE_PARM(maxframe,"1-" __MODULE_STRING(MAX_DEVICES) "i");
504 MODULE_PARM(dosyncppp,"1-" __MODULE_STRING(MAX_DEVICES) "i");
505
506 static char *driver_name = "SyncLink MultiPort driver";
507 static char *driver_version = "$Revision: 3.27 $";
508
509 static int __devinit synclinkmp_init_one(struct pci_dev *dev,const struct pci_device_id *ent);
510 static void __devexit synclinkmp_remove_one(struct pci_dev *dev);
511
512 static struct pci_device_id synclinkmp_pci_tbl[] __devinitdata = {
513 { PCI_VENDOR_ID_MICROGATE, PCI_DEVICE_ID_MICROGATE_SCA, PCI_ANY_ID, PCI_ANY_ID, },
514 { 0, }, /* terminate list */
515 };
516 MODULE_DEVICE_TABLE(pci, synclinkmp_pci_tbl);
517
518 #ifdef MODULE_LICENSE
519 MODULE_LICENSE("GPL");
520 #endif
521
522 static struct pci_driver synclinkmp_pci_driver = {
523 name: "synclinkmp",
524 id_table: synclinkmp_pci_tbl,
525 probe: synclinkmp_init_one,
526 remove: __devexit_p(synclinkmp_remove_one),
527 };
528
529
530 static struct tty_driver serial_driver, callout_driver;
531 static int serial_refcount;
532
533 /* number of characters left in xmit buffer before we ask for more */
534 #define WAKEUP_CHARS 256
535
536 static struct tty_struct *serial_table[MAX_DEVICES];
537 static struct termios *serial_termios[MAX_DEVICES];
538 static struct termios *serial_termios_locked[MAX_DEVICES];
539
540 #ifndef MIN
541 #define MIN(a,b) ((a) < (b) ? (a) : (b))
542 #endif
543
544
545 /* tty callbacks */
546
547 static int open(struct tty_struct *tty, struct file * filp);
548 static void close(struct tty_struct *tty, struct file * filp);
549 static void hangup(struct tty_struct *tty);
550 static void set_termios(struct tty_struct *tty, struct termios *old_termios);
551
552 static int write(struct tty_struct *tty, int from_user, const unsigned char *buf, int count);
553 static void put_char(struct tty_struct *tty, unsigned char ch);
554 static void send_xchar(struct tty_struct *tty, char ch);
555 static void wait_until_sent(struct tty_struct *tty, int timeout);
556 static int write_room(struct tty_struct *tty);
557 static void flush_chars(struct tty_struct *tty);
558 static void flush_buffer(struct tty_struct *tty);
559 static void tx_hold(struct tty_struct *tty);
560 static void tx_release(struct tty_struct *tty);
561
562 static int ioctl(struct tty_struct *tty, struct file *file, unsigned int cmd, unsigned long arg);
563 static int read_proc(char *page, char **start, off_t off, int count,int *eof, void *data);
564 static int chars_in_buffer(struct tty_struct *tty);
565 static void throttle(struct tty_struct * tty);
566 static void unthrottle(struct tty_struct * tty);
567 static void set_break(struct tty_struct *tty, int break_state);
568
569 /* sppp support and callbacks */
570
571 #ifdef CONFIG_SYNCLINK_SYNCPPP
572 static void sppp_init(SLMP_INFO *info);
573 static void sppp_delete(SLMP_INFO *info);
574 static void sppp_rx_done(SLMP_INFO *info, char *buf, int size);
575 static void sppp_tx_done(SLMP_INFO *info);
576
577 static int sppp_cb_open(struct net_device *d);
578 static int sppp_cb_close(struct net_device *d);
579 static int sppp_cb_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd);
580 static int sppp_cb_tx(struct sk_buff *skb, struct net_device *dev);
581 static void sppp_cb_tx_timeout(struct net_device *dev);
582 static struct net_device_stats *sppp_cb_net_stats(struct net_device *dev);
583 #endif
584
585 /* ioctl handlers */
586
587 static int get_stats(SLMP_INFO *info, struct mgsl_icount *user_icount);
588 static int get_params(SLMP_INFO *info, MGSL_PARAMS *params);
589 static int set_params(SLMP_INFO *info, MGSL_PARAMS *params);
590 static int get_txidle(SLMP_INFO *info, int*idle_mode);
591 static int set_txidle(SLMP_INFO *info, int idle_mode);
592 static int tx_enable(SLMP_INFO *info, int enable);
593 static int tx_abort(SLMP_INFO *info);
594 static int rx_enable(SLMP_INFO *info, int enable);
595 static int map_status(int signals);
596 static int modem_input_wait(SLMP_INFO *info,int arg);
597 static int wait_mgsl_event(SLMP_INFO *info, int *mask_ptr);
598 static int get_modem_info(SLMP_INFO *info, unsigned int *value);
599 static int set_modem_info(SLMP_INFO *info, unsigned int cmd,unsigned int *value);
600 static void set_break(struct tty_struct *tty, int break_state);
601
602 static void add_device(SLMP_INFO *info);
603 static void device_init(int adapter_num, struct pci_dev *pdev);
604 static int claim_resources(SLMP_INFO *info);
605 static void release_resources(SLMP_INFO *info);
606
607 static int startup(SLMP_INFO *info);
608 static int block_til_ready(struct tty_struct *tty, struct file * filp,SLMP_INFO *info);
609 static void shutdown(SLMP_INFO *info);
610 static void program_hw(SLMP_INFO *info);
611 static void change_params(SLMP_INFO *info);
612
613 static int init_adapter(SLMP_INFO *info);
614 static int register_test(SLMP_INFO *info);
615 static int irq_test(SLMP_INFO *info);
616 static int loopback_test(SLMP_INFO *info);
617 static int adapter_test(SLMP_INFO *info);
618 static int memory_test(SLMP_INFO *info);
619
620 static void reset_adapter(SLMP_INFO *info);
621 static void reset_port(SLMP_INFO *info);
622 static void async_mode(SLMP_INFO *info);
623 static void hdlc_mode(SLMP_INFO *info);
624
625 static void rx_stop(SLMP_INFO *info);
626 static void rx_start(SLMP_INFO *info);
627 static void rx_reset_buffers(SLMP_INFO *info);
628 static void rx_free_frame_buffers(SLMP_INFO *info, unsigned int first, unsigned int last);
629 static int rx_get_frame(SLMP_INFO *info);
630
631 static void tx_start(SLMP_INFO *info);
632 static void tx_stop(SLMP_INFO *info);
633 static void tx_load_fifo(SLMP_INFO *info);
634 static void tx_set_idle(SLMP_INFO *info);
635 static void tx_load_dma_buffer(SLMP_INFO *info, const char *buf, unsigned int count);
636
637 static void get_signals(SLMP_INFO *info);
638 static void set_signals(SLMP_INFO *info);
639 static void enable_loopback(SLMP_INFO *info, int enable);
640 static void set_rate(SLMP_INFO *info, u32 data_rate);
641
642 static int bh_action(SLMP_INFO *info);
643 static void bh_handler(void* Context);
644 static void bh_receive(SLMP_INFO *info);
645 static void bh_transmit(SLMP_INFO *info);
646 static void bh_status(SLMP_INFO *info);
647 static void isr_timer(SLMP_INFO *info);
648 static void isr_rxint(SLMP_INFO *info);
649 static void isr_rxrdy(SLMP_INFO *info);
650 static void isr_txint(SLMP_INFO *info);
651 static void isr_txrdy(SLMP_INFO *info);
652 static void isr_rxdmaok(SLMP_INFO *info);
653 static void isr_rxdmaerror(SLMP_INFO *info);
654 static void isr_txdmaok(SLMP_INFO *info);
655 static void isr_txdmaerror(SLMP_INFO *info);
656 static void isr_io_pin(SLMP_INFO *info, u16 status);
657 static void synclinkmp_interrupt(int irq, void *dev_id, struct pt_regs * regs);
658
659 static int alloc_dma_bufs(SLMP_INFO *info);
660 static void free_dma_bufs(SLMP_INFO *info);
661 static int alloc_buf_list(SLMP_INFO *info);
662 static int alloc_frame_bufs(SLMP_INFO *info, SCADESC *list, SCADESC_EX *list_ex,int count);
663 static int alloc_tmp_rx_buf(SLMP_INFO *info);
664 static void free_tmp_rx_buf(SLMP_INFO *info);
665
666 static void load_pci_memory(SLMP_INFO *info, char* dest, const char* src, unsigned short count);
667 static void trace_block(SLMP_INFO *info, const char* data, int count, int xmit);
668 static void tx_timeout(unsigned long context);
669 static void status_timeout(unsigned long context);
670
671 static unsigned char read_reg(SLMP_INFO *info, unsigned char addr);
672 static void write_reg(SLMP_INFO *info, unsigned char addr, unsigned char val);
673 static u16 read_reg16(SLMP_INFO *info, unsigned char addr);
674 static void write_reg16(SLMP_INFO *info, unsigned char addr, u16 val);
675 static unsigned char read_status_reg(SLMP_INFO * info);
676 static void write_control_reg(SLMP_INFO * info);
677
678
679 static unsigned char rx_active_fifo_level = 16; // rx request FIFO activation level in bytes
680 static unsigned char tx_active_fifo_level = 16; // tx request FIFO activation level in bytes
681 static unsigned char tx_negate_fifo_level = 32; // tx request FIFO negation level in bytes
682
683 static u32 misc_ctrl_value = 0x007e4040;
684 static u32 lcr1_brdr_value = 0x00800029;
685
686 static u32 read_ahead_count = 8;
687
688 /* DPCR, DMA Priority Control
689 *
690 * 07..05 Not used, must be 0
691 * 04 BRC, bus release condition: 0=all transfers complete
692 * 1=release after 1 xfer on all channels
693 * 03 CCC, channel change condition: 0=every cycle
694 * 1=after each channel completes all xfers
695 * 02..00 PR<2..0>, priority 100=round robin
696 *
697 * 00000100 = 0x00
698 */
699 static unsigned char dma_priority = 0x04;
700
701 // Number of bytes that can be written to shared RAM
702 // in a single write operation
703 static u32 sca_pci_load_interval = 64;
704
705 /*
706 * 1st function defined in .text section. Calling this function in
707 * init_module() followed by a breakpoint allows a remote debugger
708 * (gdb) to get the .text address for the add-symbol-file command.
709 * This allows remote debugging of dynamically loadable modules.
710 */
711 static void* synclinkmp_get_text_ptr(void);
synclinkmp_get_text_ptr()712 static void* synclinkmp_get_text_ptr() {return synclinkmp_get_text_ptr;}
713
sanity_check(SLMP_INFO * info,kdev_t device,const char * routine)714 static inline int sanity_check(SLMP_INFO *info,
715 kdev_t device, const char *routine)
716 {
717 #ifdef SANITY_CHECK
718 static const char *badmagic =
719 "Warning: bad magic number for synclinkmp_struct (%s) in %s\n";
720 static const char *badinfo =
721 "Warning: null synclinkmp_struct for (%s) in %s\n";
722
723 if (!info) {
724 printk(badinfo, kdevname(device), routine);
725 return 1;
726 }
727 if (info->magic != MGSL_MAGIC) {
728 printk(badmagic, kdevname(device), routine);
729 return 1;
730 }
731 #else
732 if (!info)
733 return 1;
734 #endif
735 return 0;
736 }
737
738 /**
739 * line discipline callback wrappers
740 *
741 * The wrappers maintain line discipline references
742 * while calling into the line discipline.
743 *
744 * ldisc_receive_buf - pass receive data to line discipline
745 */
746
ldisc_receive_buf(struct tty_struct * tty,const __u8 * data,char * flags,int count)747 static void ldisc_receive_buf(struct tty_struct *tty,
748 const __u8 *data, char *flags, int count)
749 {
750 struct tty_ldisc *ld;
751 if (!tty)
752 return;
753 ld = tty_ldisc_ref(tty);
754 if (ld) {
755 if (ld->receive_buf)
756 ld->receive_buf(tty, data, flags, count);
757 tty_ldisc_deref(ld);
758 }
759 }
760
761 /* tty callbacks */
762
763 /* Called when a port is opened. Init and enable port.
764 */
open(struct tty_struct * tty,struct file * filp)765 static int open(struct tty_struct *tty, struct file *filp)
766 {
767 SLMP_INFO *info;
768 int retval, line;
769 unsigned long flags;
770
771 line = MINOR(tty->device) - tty->driver.minor_start;
772 if ((line < 0) || (line >= synclinkmp_device_count)) {
773 printk("%s(%d): open with illegal line #%d.\n",
774 __FILE__,__LINE__,line);
775 return -ENODEV;
776 }
777
778 info = synclinkmp_device_list;
779 while(info && info->line != line)
780 info = info->next_device;
781 if (sanity_check(info, tty->device, "open"))
782 return -ENODEV;
783 if ( info->init_error ) {
784 printk("%s(%d):%s device is not allocated, init error=%d\n",
785 __FILE__,__LINE__,info->device_name,info->init_error);
786 return -ENODEV;
787 }
788
789 tty->driver_data = info;
790 info->tty = tty;
791
792 if (debug_level >= DEBUG_LEVEL_INFO)
793 printk("%s(%d):%s open(), old ref count = %d\n",
794 __FILE__,__LINE__,tty->driver.name, info->count);
795
796 MOD_INC_USE_COUNT;
797
798 /* If port is closing, signal caller to try again */
799 if (tty_hung_up_p(filp) || info->flags & ASYNC_CLOSING){
800 if (info->flags & ASYNC_CLOSING)
801 interruptible_sleep_on(&info->close_wait);
802 retval = ((info->flags & ASYNC_HUP_NOTIFY) ?
803 -EAGAIN : -ERESTARTSYS);
804 goto cleanup;
805 }
806
807 info->tty->low_latency = (info->flags & ASYNC_LOW_LATENCY) ? 1 : 0;
808
809 spin_lock_irqsave(&info->netlock, flags);
810 if (info->netcount) {
811 retval = -EBUSY;
812 spin_unlock_irqrestore(&info->netlock, flags);
813 goto cleanup;
814 }
815 info->count++;
816 spin_unlock_irqrestore(&info->netlock, flags);
817
818 if (info->count == 1) {
819 /* 1st open on this device, init hardware */
820 retval = startup(info);
821 if (retval < 0)
822 goto cleanup;
823 }
824
825 retval = block_til_ready(tty, filp, info);
826 if (retval) {
827 if (debug_level >= DEBUG_LEVEL_INFO)
828 printk("%s(%d):%s block_til_ready() returned %d\n",
829 __FILE__,__LINE__, info->device_name, retval);
830 goto cleanup;
831 }
832
833 if ((info->count == 1) &&
834 info->flags & ASYNC_SPLIT_TERMIOS) {
835 if (tty->driver.subtype == SERIAL_TYPE_NORMAL)
836 *tty->termios = info->normal_termios;
837 else
838 *tty->termios = info->callout_termios;
839 change_params(info);
840 }
841
842 info->session = current->session;
843 info->pgrp = current->pgrp;
844
845 if (debug_level >= DEBUG_LEVEL_INFO)
846 printk("%s(%d):%s open() success\n",
847 __FILE__,__LINE__, info->device_name);
848 retval = 0;
849
850 cleanup:
851 if (retval) {
852 if (tty->count == 1)
853 info->tty = 0; /* tty layer will release tty struct */
854 if(MOD_IN_USE)
855 MOD_DEC_USE_COUNT;
856 if(info->count)
857 info->count--;
858 }
859
860 return retval;
861 }
862
863 /* Called when port is closed. Wait for remaining data to be
864 * sent. Disable port and free resources.
865 */
close(struct tty_struct * tty,struct file * filp)866 static void close(struct tty_struct *tty, struct file *filp)
867 {
868 SLMP_INFO * info = (SLMP_INFO *)tty->driver_data;
869
870 if (sanity_check(info, tty->device, "close"))
871 return;
872
873 if (debug_level >= DEBUG_LEVEL_INFO)
874 printk("%s(%d):%s close() entry, count=%d\n",
875 __FILE__,__LINE__, info->device_name, info->count);
876
877 if (!info->count)
878 return;
879
880 if (tty_hung_up_p(filp))
881 goto cleanup;
882
883 if ((tty->count == 1) && (info->count != 1)) {
884 /*
885 * tty->count is 1 and the tty structure will be freed.
886 * info->count should be one in this case.
887 * if it's not, correct it so that the port is shutdown.
888 */
889 printk("%s(%d):%s close: bad refcount; tty->count is 1, "
890 "info->count is %d\n",
891 __FILE__,__LINE__, info->device_name, info->count);
892 info->count = 1;
893 }
894
895 info->count--;
896
897 /* if at least one open remaining, leave hardware active */
898 if (info->count)
899 goto cleanup;
900
901 info->flags |= ASYNC_CLOSING;
902
903 /* Save the termios structure, since this port may have
904 * separate termios for callout and dialin.
905 */
906 if (info->flags & ASYNC_NORMAL_ACTIVE)
907 info->normal_termios = *tty->termios;
908 if (info->flags & ASYNC_CALLOUT_ACTIVE)
909 info->callout_termios = *tty->termios;
910
911 /* set tty->closing to notify line discipline to
912 * only process XON/XOFF characters. Only the N_TTY
913 * discipline appears to use this (ppp does not).
914 */
915 tty->closing = 1;
916
917 /* wait for transmit data to clear all layers */
918
919 if (info->closing_wait != ASYNC_CLOSING_WAIT_NONE) {
920 if (debug_level >= DEBUG_LEVEL_INFO)
921 printk("%s(%d):%s close() calling tty_wait_until_sent\n",
922 __FILE__,__LINE__, info->device_name );
923 tty_wait_until_sent(tty, info->closing_wait);
924 }
925
926 if (info->flags & ASYNC_INITIALIZED)
927 wait_until_sent(tty, info->timeout);
928
929 if (tty->driver.flush_buffer)
930 tty->driver.flush_buffer(tty);
931
932 tty_ldisc_flush(tty);
933
934 shutdown(info);
935
936 tty->closing = 0;
937 info->tty = 0;
938
939 if (info->blocked_open) {
940 if (info->close_delay) {
941 set_current_state(TASK_INTERRUPTIBLE);
942 schedule_timeout(info->close_delay);
943 }
944 wake_up_interruptible(&info->open_wait);
945 }
946
947 info->flags &= ~(ASYNC_NORMAL_ACTIVE|ASYNC_CALLOUT_ACTIVE|
948 ASYNC_CLOSING);
949
950 wake_up_interruptible(&info->close_wait);
951
952 cleanup:
953 if (debug_level >= DEBUG_LEVEL_INFO)
954 printk("%s(%d):%s close() exit, count=%d\n", __FILE__,__LINE__,
955 tty->driver.name, info->count);
956 if(MOD_IN_USE)
957 MOD_DEC_USE_COUNT;
958 }
959
960 /* Called by tty_hangup() when a hangup is signaled.
961 * This is the same as closing all open descriptors for the port.
962 */
hangup(struct tty_struct * tty)963 static void hangup(struct tty_struct *tty)
964 {
965 SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
966
967 if (debug_level >= DEBUG_LEVEL_INFO)
968 printk("%s(%d):%s hangup()\n",
969 __FILE__,__LINE__, info->device_name );
970
971 if (sanity_check(info, tty->device, "hangup"))
972 return;
973
974 flush_buffer(tty);
975 shutdown(info);
976
977 info->count = 0;
978 info->flags &= ~(ASYNC_NORMAL_ACTIVE|ASYNC_CALLOUT_ACTIVE);
979 info->tty = 0;
980
981 wake_up_interruptible(&info->open_wait);
982 }
983
984 /* Set new termios settings
985 */
set_termios(struct tty_struct * tty,struct termios * old_termios)986 static void set_termios(struct tty_struct *tty, struct termios *old_termios)
987 {
988 SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
989 unsigned long flags;
990
991 if (debug_level >= DEBUG_LEVEL_INFO)
992 printk("%s(%d):%s set_termios()\n", __FILE__,__LINE__,
993 tty->driver.name );
994
995 /* just return if nothing has changed */
996 if ((tty->termios->c_cflag == old_termios->c_cflag)
997 && (RELEVANT_IFLAG(tty->termios->c_iflag)
998 == RELEVANT_IFLAG(old_termios->c_iflag)))
999 return;
1000
1001 change_params(info);
1002
1003 /* Handle transition to B0 status */
1004 if (old_termios->c_cflag & CBAUD &&
1005 !(tty->termios->c_cflag & CBAUD)) {
1006 info->serial_signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
1007 spin_lock_irqsave(&info->lock,flags);
1008 set_signals(info);
1009 spin_unlock_irqrestore(&info->lock,flags);
1010 }
1011
1012 /* Handle transition away from B0 status */
1013 if (!(old_termios->c_cflag & CBAUD) &&
1014 tty->termios->c_cflag & CBAUD) {
1015 info->serial_signals |= SerialSignal_DTR;
1016 if (!(tty->termios->c_cflag & CRTSCTS) ||
1017 !test_bit(TTY_THROTTLED, &tty->flags)) {
1018 info->serial_signals |= SerialSignal_RTS;
1019 }
1020 spin_lock_irqsave(&info->lock,flags);
1021 set_signals(info);
1022 spin_unlock_irqrestore(&info->lock,flags);
1023 }
1024
1025 /* Handle turning off CRTSCTS */
1026 if (old_termios->c_cflag & CRTSCTS &&
1027 !(tty->termios->c_cflag & CRTSCTS)) {
1028 tty->hw_stopped = 0;
1029 tx_release(tty);
1030 }
1031 }
1032
1033 /* Send a block of data
1034 *
1035 * Arguments:
1036 *
1037 * tty pointer to tty information structure
1038 * from_user flag: 1 = from user process
1039 * buf pointer to buffer containing send data
1040 * count size of send data in bytes
1041 *
1042 * Return Value: number of characters written
1043 */
write(struct tty_struct * tty,int from_user,const unsigned char * buf,int count)1044 static int write(struct tty_struct *tty, int from_user,
1045 const unsigned char *buf, int count)
1046 {
1047 int c, ret = 0, err;
1048 SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1049 unsigned long flags;
1050
1051 if (debug_level >= DEBUG_LEVEL_INFO)
1052 printk("%s(%d):%s write() count=%d\n",
1053 __FILE__,__LINE__,info->device_name,count);
1054
1055 if (sanity_check(info, tty->device, "write"))
1056 goto cleanup;
1057
1058 if (!tty || !info->tx_buf)
1059 goto cleanup;
1060
1061 if (info->params.mode == MGSL_MODE_HDLC) {
1062 if (count > info->max_frame_size) {
1063 ret = -EIO;
1064 goto cleanup;
1065 }
1066 if (info->tx_active)
1067 goto cleanup;
1068 if (info->tx_count) {
1069 /* send accumulated data from send_char() calls */
1070 /* as frame and wait before accepting more data. */
1071 tx_load_dma_buffer(info, info->tx_buf, info->tx_count);
1072 goto start;
1073 }
1074 if (!from_user) {
1075 ret = info->tx_count = count;
1076 tx_load_dma_buffer(info, buf, count);
1077 goto start;
1078 }
1079 }
1080
1081 for (;;) {
1082 c = MIN(count,
1083 MIN(info->max_frame_size - info->tx_count - 1,
1084 info->max_frame_size - info->tx_put));
1085 if (c <= 0)
1086 break;
1087
1088 if (from_user) {
1089 COPY_FROM_USER(err, info->tx_buf + info->tx_put, buf, c);
1090 if (err) {
1091 if (!ret)
1092 ret = -EFAULT;
1093 break;
1094 }
1095 } else
1096 memcpy(info->tx_buf + info->tx_put, buf, c);
1097
1098 spin_lock_irqsave(&info->lock,flags);
1099 info->tx_put += c;
1100 if (info->tx_put >= info->max_frame_size)
1101 info->tx_put -= info->max_frame_size;
1102 info->tx_count += c;
1103 spin_unlock_irqrestore(&info->lock,flags);
1104
1105 buf += c;
1106 count -= c;
1107 ret += c;
1108 }
1109
1110 if (info->params.mode == MGSL_MODE_HDLC) {
1111 if (count) {
1112 ret = info->tx_count = 0;
1113 goto cleanup;
1114 }
1115 tx_load_dma_buffer(info, info->tx_buf, info->tx_count);
1116 }
1117 start:
1118 if (info->tx_count && !tty->stopped && !tty->hw_stopped) {
1119 spin_lock_irqsave(&info->lock,flags);
1120 if (!info->tx_active)
1121 tx_start(info);
1122 spin_unlock_irqrestore(&info->lock,flags);
1123 }
1124
1125 cleanup:
1126 if (debug_level >= DEBUG_LEVEL_INFO)
1127 printk( "%s(%d):%s write() returning=%d\n",
1128 __FILE__,__LINE__,info->device_name,ret);
1129 return ret;
1130 }
1131
1132 /* Add a character to the transmit buffer.
1133 */
put_char(struct tty_struct * tty,unsigned char ch)1134 static void put_char(struct tty_struct *tty, unsigned char ch)
1135 {
1136 SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1137 unsigned long flags;
1138
1139 if ( debug_level >= DEBUG_LEVEL_INFO ) {
1140 printk( "%s(%d):%s put_char(%d)\n",
1141 __FILE__,__LINE__,info->device_name,ch);
1142 }
1143
1144 if (sanity_check(info, tty->device, "put_char"))
1145 return;
1146
1147 if (!tty || !info->tx_buf)
1148 return;
1149
1150 spin_lock_irqsave(&info->lock,flags);
1151
1152 if ( (info->params.mode != MGSL_MODE_HDLC) ||
1153 !info->tx_active ) {
1154
1155 if (info->tx_count < info->max_frame_size - 1) {
1156 info->tx_buf[info->tx_put++] = ch;
1157 if (info->tx_put >= info->max_frame_size)
1158 info->tx_put -= info->max_frame_size;
1159 info->tx_count++;
1160 }
1161 }
1162
1163 spin_unlock_irqrestore(&info->lock,flags);
1164 }
1165
1166 /* Send a high-priority XON/XOFF character
1167 */
send_xchar(struct tty_struct * tty,char ch)1168 static void send_xchar(struct tty_struct *tty, char ch)
1169 {
1170 SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1171 unsigned long flags;
1172
1173 if (debug_level >= DEBUG_LEVEL_INFO)
1174 printk("%s(%d):%s send_xchar(%d)\n",
1175 __FILE__,__LINE__, info->device_name, ch );
1176
1177 if (sanity_check(info, tty->device, "send_xchar"))
1178 return;
1179
1180 info->x_char = ch;
1181 if (ch) {
1182 /* Make sure transmit interrupts are on */
1183 spin_lock_irqsave(&info->lock,flags);
1184 if (!info->tx_enabled)
1185 tx_start(info);
1186 spin_unlock_irqrestore(&info->lock,flags);
1187 }
1188 }
1189
1190 /* Wait until the transmitter is empty.
1191 */
wait_until_sent(struct tty_struct * tty,int timeout)1192 static void wait_until_sent(struct tty_struct *tty, int timeout)
1193 {
1194 SLMP_INFO * info = (SLMP_INFO *)tty->driver_data;
1195 unsigned long orig_jiffies, char_time;
1196
1197 if (!info )
1198 return;
1199
1200 if (debug_level >= DEBUG_LEVEL_INFO)
1201 printk("%s(%d):%s wait_until_sent() entry\n",
1202 __FILE__,__LINE__, info->device_name );
1203
1204 if (sanity_check(info, tty->device, "wait_until_sent"))
1205 return;
1206
1207 if (!(info->flags & ASYNC_INITIALIZED))
1208 goto exit;
1209
1210 orig_jiffies = jiffies;
1211
1212 /* Set check interval to 1/5 of estimated time to
1213 * send a character, and make it at least 1. The check
1214 * interval should also be less than the timeout.
1215 * Note: use tight timings here to satisfy the NIST-PCTS.
1216 */
1217
1218 if ( info->params.data_rate ) {
1219 char_time = info->timeout/(32 * 5);
1220 if (!char_time)
1221 char_time++;
1222 } else
1223 char_time = 1;
1224
1225 if (timeout)
1226 char_time = MIN(char_time, timeout);
1227
1228 if ( info->params.mode == MGSL_MODE_HDLC ) {
1229 while (info->tx_active) {
1230 set_current_state(TASK_INTERRUPTIBLE);
1231 schedule_timeout(char_time);
1232 if (signal_pending(current))
1233 break;
1234 if (timeout && time_after(jiffies, orig_jiffies + timeout))
1235 break;
1236 }
1237 } else {
1238 //TODO: determine if there is something similar to USC16C32
1239 // TXSTATUS_ALL_SENT status
1240 while ( info->tx_active && info->tx_enabled) {
1241 set_current_state(TASK_INTERRUPTIBLE);
1242 schedule_timeout(char_time);
1243 if (signal_pending(current))
1244 break;
1245 if (timeout && time_after(jiffies, orig_jiffies + timeout))
1246 break;
1247 }
1248 }
1249
1250 exit:
1251 if (debug_level >= DEBUG_LEVEL_INFO)
1252 printk("%s(%d):%s wait_until_sent() exit\n",
1253 __FILE__,__LINE__, info->device_name );
1254 }
1255
1256 /* Return the count of free bytes in transmit buffer
1257 */
write_room(struct tty_struct * tty)1258 static int write_room(struct tty_struct *tty)
1259 {
1260 SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1261 int ret;
1262
1263 if (sanity_check(info, tty->device, "write_room"))
1264 return 0;
1265
1266 if (info->params.mode == MGSL_MODE_HDLC) {
1267 ret = (info->tx_active) ? 0 : HDLC_MAX_FRAME_SIZE;
1268 } else {
1269 ret = info->max_frame_size - info->tx_count - 1;
1270 if (ret < 0)
1271 ret = 0;
1272 }
1273
1274 if (debug_level >= DEBUG_LEVEL_INFO)
1275 printk("%s(%d):%s write_room()=%d\n",
1276 __FILE__, __LINE__, info->device_name, ret);
1277
1278 return ret;
1279 }
1280
1281 /* enable transmitter and send remaining buffered characters
1282 */
flush_chars(struct tty_struct * tty)1283 static void flush_chars(struct tty_struct *tty)
1284 {
1285 SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1286 unsigned long flags;
1287
1288 if ( debug_level >= DEBUG_LEVEL_INFO )
1289 printk( "%s(%d):%s flush_chars() entry tx_count=%d\n",
1290 __FILE__,__LINE__,info->device_name,info->tx_count);
1291
1292 if (sanity_check(info, tty->device, "flush_chars"))
1293 return;
1294
1295 if (info->tx_count <= 0 || tty->stopped || tty->hw_stopped ||
1296 !info->tx_buf)
1297 return;
1298
1299 if ( debug_level >= DEBUG_LEVEL_INFO )
1300 printk( "%s(%d):%s flush_chars() entry, starting transmitter\n",
1301 __FILE__,__LINE__,info->device_name );
1302
1303 spin_lock_irqsave(&info->lock,flags);
1304
1305 if (!info->tx_active) {
1306 if ( (info->params.mode == MGSL_MODE_HDLC) &&
1307 info->tx_count ) {
1308 /* operating in synchronous (frame oriented) mode */
1309 /* copy data from circular tx_buf to */
1310 /* transmit DMA buffer. */
1311 tx_load_dma_buffer(info,
1312 info->tx_buf,info->tx_count);
1313 }
1314 tx_start(info);
1315 }
1316
1317 spin_unlock_irqrestore(&info->lock,flags);
1318 }
1319
1320 /* Discard all data in the send buffer
1321 */
flush_buffer(struct tty_struct * tty)1322 static void flush_buffer(struct tty_struct *tty)
1323 {
1324 SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1325 unsigned long flags;
1326
1327 if (debug_level >= DEBUG_LEVEL_INFO)
1328 printk("%s(%d):%s flush_buffer() entry\n",
1329 __FILE__,__LINE__, info->device_name );
1330
1331 if (sanity_check(info, tty->device, "flush_buffer"))
1332 return;
1333
1334 spin_lock_irqsave(&info->lock,flags);
1335 info->tx_count = info->tx_put = info->tx_get = 0;
1336 del_timer(&info->tx_timer);
1337 spin_unlock_irqrestore(&info->lock,flags);
1338
1339 wake_up_interruptible(&tty->write_wait);
1340 tty_wakeup(tty);
1341 }
1342
1343 /* throttle (stop) transmitter
1344 */
tx_hold(struct tty_struct * tty)1345 static void tx_hold(struct tty_struct *tty)
1346 {
1347 SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1348 unsigned long flags;
1349
1350 if (sanity_check(info, tty->device, "tx_hold"))
1351 return;
1352
1353 if ( debug_level >= DEBUG_LEVEL_INFO )
1354 printk("%s(%d):%s tx_hold()\n",
1355 __FILE__,__LINE__,info->device_name);
1356
1357 spin_lock_irqsave(&info->lock,flags);
1358 if (info->tx_enabled)
1359 tx_stop(info);
1360 spin_unlock_irqrestore(&info->lock,flags);
1361 }
1362
1363 /* release (start) transmitter
1364 */
tx_release(struct tty_struct * tty)1365 static void tx_release(struct tty_struct *tty)
1366 {
1367 SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1368 unsigned long flags;
1369
1370 if (sanity_check(info, tty->device, "tx_release"))
1371 return;
1372
1373 if ( debug_level >= DEBUG_LEVEL_INFO )
1374 printk("%s(%d):%s tx_release()\n",
1375 __FILE__,__LINE__,info->device_name);
1376
1377 spin_lock_irqsave(&info->lock,flags);
1378 if (!info->tx_enabled)
1379 tx_start(info);
1380 spin_unlock_irqrestore(&info->lock,flags);
1381 }
1382
1383 /* Service an IOCTL request
1384 *
1385 * Arguments:
1386 *
1387 * tty pointer to tty instance data
1388 * file pointer to associated file object for device
1389 * cmd IOCTL command code
1390 * arg command argument/context
1391 *
1392 * Return Value: 0 if success, otherwise error code
1393 */
ioctl(struct tty_struct * tty,struct file * file,unsigned int cmd,unsigned long arg)1394 static int ioctl(struct tty_struct *tty, struct file *file,
1395 unsigned int cmd, unsigned long arg)
1396 {
1397 SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1398 int error;
1399 struct mgsl_icount cnow; /* kernel counter temps */
1400 struct serial_icounter_struct *p_cuser; /* user space */
1401 unsigned long flags;
1402
1403 if (debug_level >= DEBUG_LEVEL_INFO)
1404 printk("%s(%d):%s ioctl() cmd=%08X\n", __FILE__,__LINE__,
1405 info->device_name, cmd );
1406
1407 if (sanity_check(info, tty->device, "ioctl"))
1408 return -ENODEV;
1409
1410 if ((cmd != TIOCGSERIAL) && (cmd != TIOCSSERIAL) &&
1411 (cmd != TIOCMIWAIT) && (cmd != TIOCGICOUNT)) {
1412 if (tty->flags & (1 << TTY_IO_ERROR))
1413 return -EIO;
1414 }
1415
1416 switch (cmd) {
1417 case TIOCMGET:
1418 return get_modem_info(info, (unsigned int *) arg);
1419 case TIOCMBIS:
1420 case TIOCMBIC:
1421 case TIOCMSET:
1422 return set_modem_info(info, cmd, (unsigned int *) arg);
1423 case MGSL_IOCGPARAMS:
1424 return get_params(info,(MGSL_PARAMS *)arg);
1425 case MGSL_IOCSPARAMS:
1426 return set_params(info,(MGSL_PARAMS *)arg);
1427 case MGSL_IOCGTXIDLE:
1428 return get_txidle(info,(int*)arg);
1429 case MGSL_IOCSTXIDLE:
1430 return set_txidle(info,(int)arg);
1431 case MGSL_IOCTXENABLE:
1432 return tx_enable(info,(int)arg);
1433 case MGSL_IOCRXENABLE:
1434 return rx_enable(info,(int)arg);
1435 case MGSL_IOCTXABORT:
1436 return tx_abort(info);
1437 case MGSL_IOCGSTATS:
1438 return get_stats(info,(struct mgsl_icount*)arg);
1439 case MGSL_IOCWAITEVENT:
1440 return wait_mgsl_event(info,(int*)arg);
1441 case MGSL_IOCLOOPTXDONE:
1442 return 0; // TODO: Not supported, need to document
1443 case MGSL_IOCCLRMODCOUNT:
1444 while(MOD_IN_USE)
1445 MOD_DEC_USE_COUNT;
1446 return 0;
1447 /* Wait for modem input (DCD,RI,DSR,CTS) change
1448 * as specified by mask in arg (TIOCM_RNG/DSR/CD/CTS)
1449 */
1450 case TIOCMIWAIT:
1451 return modem_input_wait(info,(int)arg);
1452
1453 /*
1454 * Get counter of input serial line interrupts (DCD,RI,DSR,CTS)
1455 * Return: write counters to the user passed counter struct
1456 * NB: both 1->0 and 0->1 transitions are counted except for
1457 * RI where only 0->1 is counted.
1458 */
1459 case TIOCGICOUNT:
1460 spin_lock_irqsave(&info->lock,flags);
1461 cnow = info->icount;
1462 spin_unlock_irqrestore(&info->lock,flags);
1463 p_cuser = (struct serial_icounter_struct *) arg;
1464 PUT_USER(error,cnow.cts, &p_cuser->cts);
1465 if (error) return error;
1466 PUT_USER(error,cnow.dsr, &p_cuser->dsr);
1467 if (error) return error;
1468 PUT_USER(error,cnow.rng, &p_cuser->rng);
1469 if (error) return error;
1470 PUT_USER(error,cnow.dcd, &p_cuser->dcd);
1471 if (error) return error;
1472 PUT_USER(error,cnow.rx, &p_cuser->rx);
1473 if (error) return error;
1474 PUT_USER(error,cnow.tx, &p_cuser->tx);
1475 if (error) return error;
1476 PUT_USER(error,cnow.frame, &p_cuser->frame);
1477 if (error) return error;
1478 PUT_USER(error,cnow.overrun, &p_cuser->overrun);
1479 if (error) return error;
1480 PUT_USER(error,cnow.parity, &p_cuser->parity);
1481 if (error) return error;
1482 PUT_USER(error,cnow.brk, &p_cuser->brk);
1483 if (error) return error;
1484 PUT_USER(error,cnow.buf_overrun, &p_cuser->buf_overrun);
1485 if (error) return error;
1486 return 0;
1487 default:
1488 return -ENOIOCTLCMD;
1489 }
1490 return 0;
1491 }
1492
1493 /*
1494 * /proc fs routines....
1495 */
1496
line_info(char * buf,SLMP_INFO * info)1497 static inline int line_info(char *buf, SLMP_INFO *info)
1498 {
1499 char stat_buf[30];
1500 int ret;
1501 unsigned long flags;
1502
1503 ret = sprintf(buf, "%s: SCABase=%08x Mem=%08X StatusControl=%08x LCR=%08X\n"
1504 "\tIRQ=%d MaxFrameSize=%u\n",
1505 info->device_name,
1506 info->phys_sca_base,
1507 info->phys_memory_base,
1508 info->phys_statctrl_base,
1509 info->phys_lcr_base,
1510 info->irq_level,
1511 info->max_frame_size );
1512
1513 /* output current serial signal states */
1514 spin_lock_irqsave(&info->lock,flags);
1515 get_signals(info);
1516 spin_unlock_irqrestore(&info->lock,flags);
1517
1518 stat_buf[0] = 0;
1519 stat_buf[1] = 0;
1520 if (info->serial_signals & SerialSignal_RTS)
1521 strcat(stat_buf, "|RTS");
1522 if (info->serial_signals & SerialSignal_CTS)
1523 strcat(stat_buf, "|CTS");
1524 if (info->serial_signals & SerialSignal_DTR)
1525 strcat(stat_buf, "|DTR");
1526 if (info->serial_signals & SerialSignal_DSR)
1527 strcat(stat_buf, "|DSR");
1528 if (info->serial_signals & SerialSignal_DCD)
1529 strcat(stat_buf, "|CD");
1530 if (info->serial_signals & SerialSignal_RI)
1531 strcat(stat_buf, "|RI");
1532
1533 if (info->params.mode == MGSL_MODE_HDLC) {
1534 ret += sprintf(buf+ret, "\tHDLC txok:%d rxok:%d",
1535 info->icount.txok, info->icount.rxok);
1536 if (info->icount.txunder)
1537 ret += sprintf(buf+ret, " txunder:%d", info->icount.txunder);
1538 if (info->icount.txabort)
1539 ret += sprintf(buf+ret, " txabort:%d", info->icount.txabort);
1540 if (info->icount.rxshort)
1541 ret += sprintf(buf+ret, " rxshort:%d", info->icount.rxshort);
1542 if (info->icount.rxlong)
1543 ret += sprintf(buf+ret, " rxlong:%d", info->icount.rxlong);
1544 if (info->icount.rxover)
1545 ret += sprintf(buf+ret, " rxover:%d", info->icount.rxover);
1546 if (info->icount.rxcrc)
1547 ret += sprintf(buf+ret, " rxlong:%d", info->icount.rxcrc);
1548 } else {
1549 ret += sprintf(buf+ret, "\tASYNC tx:%d rx:%d",
1550 info->icount.tx, info->icount.rx);
1551 if (info->icount.frame)
1552 ret += sprintf(buf+ret, " fe:%d", info->icount.frame);
1553 if (info->icount.parity)
1554 ret += sprintf(buf+ret, " pe:%d", info->icount.parity);
1555 if (info->icount.brk)
1556 ret += sprintf(buf+ret, " brk:%d", info->icount.brk);
1557 if (info->icount.overrun)
1558 ret += sprintf(buf+ret, " oe:%d", info->icount.overrun);
1559 }
1560
1561 /* Append serial signal status to end */
1562 ret += sprintf(buf+ret, " %s\n", stat_buf+1);
1563
1564 ret += sprintf(buf+ret, "\ttxactive=%d bh_req=%d bh_run=%d pending_bh=%x\n",
1565 info->tx_active,info->bh_requested,info->bh_running,
1566 info->pending_bh);
1567
1568 return ret;
1569 }
1570
1571 /* Called to print information about devices
1572 */
read_proc(char * page,char ** start,off_t off,int count,int * eof,void * data)1573 int read_proc(char *page, char **start, off_t off, int count,
1574 int *eof, void *data)
1575 {
1576 int len = 0, l;
1577 off_t begin = 0;
1578 SLMP_INFO *info;
1579
1580 len += sprintf(page, "synclinkmp driver:%s\n", driver_version);
1581
1582 info = synclinkmp_device_list;
1583 while( info ) {
1584 l = line_info(page + len, info);
1585 len += l;
1586 if (len+begin > off+count)
1587 goto done;
1588 if (len+begin < off) {
1589 begin += len;
1590 len = 0;
1591 }
1592 info = info->next_device;
1593 }
1594
1595 *eof = 1;
1596 done:
1597 if (off >= len+begin)
1598 return 0;
1599 *start = page + (off-begin);
1600 return ((count < begin+len-off) ? count : begin+len-off);
1601 }
1602
1603 /* Return the count of bytes in transmit buffer
1604 */
chars_in_buffer(struct tty_struct * tty)1605 static int chars_in_buffer(struct tty_struct *tty)
1606 {
1607 SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1608
1609 if (sanity_check(info, tty->device, "chars_in_buffer"))
1610 return 0;
1611
1612 if (debug_level >= DEBUG_LEVEL_INFO)
1613 printk("%s(%d):%s chars_in_buffer()=%d\n",
1614 __FILE__, __LINE__, info->device_name, info->tx_count);
1615
1616 return info->tx_count;
1617 }
1618
1619 /* Signal remote device to throttle send data (our receive data)
1620 */
throttle(struct tty_struct * tty)1621 static void throttle(struct tty_struct * tty)
1622 {
1623 SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1624 unsigned long flags;
1625
1626 if (debug_level >= DEBUG_LEVEL_INFO)
1627 printk("%s(%d):%s throttle() entry\n",
1628 __FILE__,__LINE__, info->device_name );
1629
1630 if (sanity_check(info, tty->device, "throttle"))
1631 return;
1632
1633 if (I_IXOFF(tty))
1634 send_xchar(tty, STOP_CHAR(tty));
1635
1636 if (tty->termios->c_cflag & CRTSCTS) {
1637 spin_lock_irqsave(&info->lock,flags);
1638 info->serial_signals &= ~SerialSignal_RTS;
1639 set_signals(info);
1640 spin_unlock_irqrestore(&info->lock,flags);
1641 }
1642 }
1643
1644 /* Signal remote device to stop throttling send data (our receive data)
1645 */
unthrottle(struct tty_struct * tty)1646 static void unthrottle(struct tty_struct * tty)
1647 {
1648 SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1649 unsigned long flags;
1650
1651 if (debug_level >= DEBUG_LEVEL_INFO)
1652 printk("%s(%d):%s unthrottle() entry\n",
1653 __FILE__,__LINE__, info->device_name );
1654
1655 if (sanity_check(info, tty->device, "unthrottle"))
1656 return;
1657
1658 if (I_IXOFF(tty)) {
1659 if (info->x_char)
1660 info->x_char = 0;
1661 else
1662 send_xchar(tty, START_CHAR(tty));
1663 }
1664
1665 if (tty->termios->c_cflag & CRTSCTS) {
1666 spin_lock_irqsave(&info->lock,flags);
1667 info->serial_signals |= SerialSignal_RTS;
1668 set_signals(info);
1669 spin_unlock_irqrestore(&info->lock,flags);
1670 }
1671 }
1672
1673 /* set or clear transmit break condition
1674 * break_state -1=set break condition, 0=clear
1675 */
set_break(struct tty_struct * tty,int break_state)1676 static void set_break(struct tty_struct *tty, int break_state)
1677 {
1678 unsigned char RegValue;
1679 SLMP_INFO * info = (SLMP_INFO *)tty->driver_data;
1680 unsigned long flags;
1681
1682 if (debug_level >= DEBUG_LEVEL_INFO)
1683 printk("%s(%d):%s set_break(%d)\n",
1684 __FILE__,__LINE__, info->device_name, break_state);
1685
1686 if (sanity_check(info, tty->device, "set_break"))
1687 return;
1688
1689 spin_lock_irqsave(&info->lock,flags);
1690 RegValue = read_reg(info, CTL);
1691 if (break_state == -1)
1692 RegValue |= BIT3;
1693 else
1694 RegValue &= ~BIT3;
1695 write_reg(info, CTL, RegValue);
1696 spin_unlock_irqrestore(&info->lock,flags);
1697 }
1698
1699 #ifdef CONFIG_SYNCLINK_SYNCPPP
1700
1701 /* syncppp support and callbacks */
1702
sppp_init(SLMP_INFO * info)1703 static void sppp_init(SLMP_INFO *info)
1704 {
1705 struct net_device *d;
1706
1707 sprintf(info->netname,"mgslm%dp%d",info->adapter_num,info->port_num);
1708
1709 info->if_ptr = &info->pppdev;
1710 info->netdev = info->pppdev.dev = &info->netdevice;
1711
1712 sppp_attach(&info->pppdev);
1713
1714 d = info->netdev;
1715 strcpy(d->name,info->netname);
1716 d->base_addr = 0;
1717 d->irq = info->irq_level;
1718 d->dma = 0;
1719 d->priv = info;
1720 d->init = NULL;
1721 d->open = sppp_cb_open;
1722 d->stop = sppp_cb_close;
1723 d->hard_start_xmit = sppp_cb_tx;
1724 d->do_ioctl = sppp_cb_ioctl;
1725 d->get_stats = sppp_cb_net_stats;
1726 d->tx_timeout = sppp_cb_tx_timeout;
1727 d->watchdog_timeo = 10*HZ;
1728
1729 #if LINUX_VERSION_CODE < VERSION(2,4,4)
1730 dev_init_buffers(d);
1731 #endif
1732
1733 if (register_netdev(d) == -1) {
1734 printk(KERN_WARNING "%s: register_netdev failed.\n", d->name);
1735 sppp_detach(info->netdev);
1736 return;
1737 }
1738
1739 if (debug_level >= DEBUG_LEVEL_INFO)
1740 printk("sppp_init(%s)\n",info->netname);
1741 }
1742
sppp_delete(SLMP_INFO * info)1743 static void sppp_delete(SLMP_INFO *info)
1744 {
1745 if (debug_level >= DEBUG_LEVEL_INFO)
1746 printk("sppp_delete(%s)\n",info->netname);
1747 sppp_detach(info->netdev);
1748 unregister_netdev(info->netdev);
1749 }
1750
sppp_cb_open(struct net_device * d)1751 static int sppp_cb_open(struct net_device *d)
1752 {
1753 SLMP_INFO *info = d->priv;
1754 int err, flags;
1755
1756 if (debug_level >= DEBUG_LEVEL_INFO)
1757 printk("sppp_cb_open(%s)\n",info->netname);
1758
1759 spin_lock_irqsave(&info->netlock, flags);
1760 if (info->count != 0 || info->netcount != 0) {
1761 printk(KERN_WARNING "%s: sppp_cb_open returning busy\n", info->netname);
1762 spin_unlock_irqrestore(&info->netlock, flags);
1763 return -EBUSY;
1764 }
1765 info->netcount=1;
1766 MOD_INC_USE_COUNT;
1767 spin_unlock_irqrestore(&info->netlock, flags);
1768
1769 /* claim resources and init adapter */
1770 if ((err = startup(info)) != 0)
1771 goto open_fail;
1772
1773 /* allow syncppp module to do open processing */
1774 if ((err = sppp_open(d)) != 0) {
1775 shutdown(info);
1776 goto open_fail;
1777 }
1778
1779 info->serial_signals |= SerialSignal_RTS + SerialSignal_DTR;
1780 program_hw(info);
1781
1782 d->trans_start = jiffies;
1783 netif_start_queue(d);
1784 return 0;
1785
1786 open_fail:
1787 spin_lock_irqsave(&info->netlock, flags);
1788 info->netcount=0;
1789 MOD_DEC_USE_COUNT;
1790 spin_unlock_irqrestore(&info->netlock, flags);
1791 return err;
1792 }
1793
sppp_cb_tx_timeout(struct net_device * dev)1794 static void sppp_cb_tx_timeout(struct net_device *dev)
1795 {
1796 SLMP_INFO *info = dev->priv;
1797 int flags;
1798
1799 if (debug_level >= DEBUG_LEVEL_INFO)
1800 printk("sppp_tx_timeout(%s)\n",info->netname);
1801
1802 info->netstats.tx_errors++;
1803 info->netstats.tx_aborted_errors++;
1804
1805 spin_lock_irqsave(&info->lock,flags);
1806 tx_stop(info);
1807 spin_unlock_irqrestore(&info->lock,flags);
1808
1809 netif_wake_queue(dev);
1810 }
1811
sppp_cb_tx(struct sk_buff * skb,struct net_device * dev)1812 static int sppp_cb_tx(struct sk_buff *skb, struct net_device *dev)
1813 {
1814 SLMP_INFO *info = dev->priv;
1815 unsigned long flags;
1816
1817 if (debug_level >= DEBUG_LEVEL_INFO)
1818 printk("sppp_tx(%s)\n",info->netname);
1819
1820 netif_stop_queue(dev);
1821
1822 info->tx_count = skb->len;
1823 tx_load_dma_buffer(info, skb->data, skb->len);
1824 info->netstats.tx_packets++;
1825 info->netstats.tx_bytes += skb->len;
1826 dev_kfree_skb(skb);
1827
1828 dev->trans_start = jiffies;
1829
1830 spin_lock_irqsave(&info->lock,flags);
1831 if (!info->tx_active)
1832 tx_start(info);
1833 spin_unlock_irqrestore(&info->lock,flags);
1834
1835 return 0;
1836 }
1837
sppp_cb_close(struct net_device * d)1838 static int sppp_cb_close(struct net_device *d)
1839 {
1840 SLMP_INFO *info = d->priv;
1841 unsigned long flags;
1842
1843 if (debug_level >= DEBUG_LEVEL_INFO)
1844 printk("sppp_cb_close(%s)\n",info->netname);
1845
1846 /* shutdown adapter and release resources */
1847 shutdown(info);
1848
1849 /* allow syncppp to do close processing */
1850 sppp_close(d);
1851 netif_stop_queue(d);
1852
1853 spin_lock_irqsave(&info->netlock, flags);
1854 info->netcount=0;
1855 MOD_DEC_USE_COUNT;
1856 spin_unlock_irqrestore(&info->netlock, flags);
1857 return 0;
1858 }
1859
sppp_rx_done(SLMP_INFO * info,char * buf,int size)1860 static void sppp_rx_done(SLMP_INFO *info, char *buf, int size)
1861 {
1862 struct sk_buff *skb = dev_alloc_skb(size);
1863 if (debug_level >= DEBUG_LEVEL_INFO)
1864 printk("sppp_rx_done(%s)\n",info->netname);
1865 if (skb == NULL) {
1866 printk(KERN_NOTICE "%s: cant alloc skb, dropping packet\n",
1867 info->netname);
1868 info->netstats.rx_dropped++;
1869 return;
1870 }
1871
1872 memcpy(skb_put(skb, size),buf,size);
1873
1874 skb->protocol = htons(ETH_P_WAN_PPP);
1875 skb->dev = info->netdev;
1876 skb->mac.raw = skb->data;
1877 info->netstats.rx_packets++;
1878 info->netstats.rx_bytes += size;
1879 netif_rx(skb);
1880 info->netdev->trans_start = jiffies;
1881 }
1882
sppp_tx_done(SLMP_INFO * info)1883 static void sppp_tx_done(SLMP_INFO *info)
1884 {
1885 if (netif_queue_stopped(info->netdev))
1886 netif_wake_queue(info->netdev);
1887 }
1888
sppp_cb_net_stats(struct net_device * dev)1889 static struct net_device_stats *sppp_cb_net_stats(struct net_device *dev)
1890 {
1891 SLMP_INFO *info = dev->priv;
1892 if (debug_level >= DEBUG_LEVEL_INFO)
1893 printk("net_stats(%s)\n",info->netname);
1894 return &info->netstats;
1895 }
1896
sppp_cb_ioctl(struct net_device * dev,struct ifreq * ifr,int cmd)1897 static int sppp_cb_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1898 {
1899 SLMP_INFO *info = (SLMP_INFO *)dev->priv;
1900 if (debug_level >= DEBUG_LEVEL_INFO)
1901 printk("%s(%d):ioctl %s cmd=%08X\n", __FILE__,__LINE__,
1902 info->netname, cmd );
1903 return sppp_do_ioctl(dev, ifr, cmd);
1904 }
1905
1906 #endif /* ifdef CONFIG_SYNCLINK_SYNCPPP */
1907
1908
1909 /* Return next bottom half action to perform.
1910 * Return Value: BH action code or 0 if nothing to do.
1911 */
bh_action(SLMP_INFO * info)1912 int bh_action(SLMP_INFO *info)
1913 {
1914 unsigned long flags;
1915 int rc = 0;
1916
1917 spin_lock_irqsave(&info->lock,flags);
1918
1919 if (info->pending_bh & BH_RECEIVE) {
1920 info->pending_bh &= ~BH_RECEIVE;
1921 rc = BH_RECEIVE;
1922 } else if (info->pending_bh & BH_TRANSMIT) {
1923 info->pending_bh &= ~BH_TRANSMIT;
1924 rc = BH_TRANSMIT;
1925 } else if (info->pending_bh & BH_STATUS) {
1926 info->pending_bh &= ~BH_STATUS;
1927 rc = BH_STATUS;
1928 }
1929
1930 if (!rc) {
1931 /* Mark BH routine as complete */
1932 info->bh_running = 0;
1933 info->bh_requested = 0;
1934 }
1935
1936 spin_unlock_irqrestore(&info->lock,flags);
1937
1938 return rc;
1939 }
1940
1941 /* Perform bottom half processing of work items queued by ISR.
1942 */
bh_handler(void * Context)1943 void bh_handler(void* Context)
1944 {
1945 SLMP_INFO *info = (SLMP_INFO*)Context;
1946 int action;
1947
1948 if (!info)
1949 return;
1950
1951 if ( debug_level >= DEBUG_LEVEL_BH )
1952 printk( "%s(%d):%s bh_handler() entry\n",
1953 __FILE__,__LINE__,info->device_name);
1954
1955 info->bh_running = 1;
1956
1957 while((action = bh_action(info)) != 0) {
1958
1959 /* Process work item */
1960 if ( debug_level >= DEBUG_LEVEL_BH )
1961 printk( "%s(%d):%s bh_handler() work item action=%d\n",
1962 __FILE__,__LINE__,info->device_name, action);
1963
1964 switch (action) {
1965
1966 case BH_RECEIVE:
1967 bh_receive(info);
1968 break;
1969 case BH_TRANSMIT:
1970 bh_transmit(info);
1971 break;
1972 case BH_STATUS:
1973 bh_status(info);
1974 break;
1975 default:
1976 /* unknown work item ID */
1977 printk("%s(%d):%s Unknown work item ID=%08X!\n",
1978 __FILE__,__LINE__,info->device_name,action);
1979 break;
1980 }
1981 }
1982
1983 if ( debug_level >= DEBUG_LEVEL_BH )
1984 printk( "%s(%d):%s bh_handler() exit\n",
1985 __FILE__,__LINE__,info->device_name);
1986 }
1987
bh_receive(SLMP_INFO * info)1988 void bh_receive(SLMP_INFO *info)
1989 {
1990 if ( debug_level >= DEBUG_LEVEL_BH )
1991 printk( "%s(%d):%s bh_receive()\n",
1992 __FILE__,__LINE__,info->device_name);
1993
1994 while( rx_get_frame(info) );
1995 }
1996
bh_transmit(SLMP_INFO * info)1997 void bh_transmit(SLMP_INFO *info)
1998 {
1999 struct tty_struct *tty = info->tty;
2000
2001 if ( debug_level >= DEBUG_LEVEL_BH )
2002 printk( "%s(%d):%s bh_transmit() entry\n",
2003 __FILE__,__LINE__,info->device_name);
2004
2005 if (tty) {
2006 tty_wakeup(tty);
2007 wake_up_interruptible(&tty->write_wait);
2008 }
2009 }
2010
bh_status(SLMP_INFO * info)2011 void bh_status(SLMP_INFO *info)
2012 {
2013 if ( debug_level >= DEBUG_LEVEL_BH )
2014 printk( "%s(%d):%s bh_status() entry\n",
2015 __FILE__,__LINE__,info->device_name);
2016
2017 info->ri_chkcount = 0;
2018 info->dsr_chkcount = 0;
2019 info->dcd_chkcount = 0;
2020 info->cts_chkcount = 0;
2021 }
2022
isr_timer(SLMP_INFO * info)2023 void isr_timer(SLMP_INFO * info)
2024 {
2025 unsigned char timer = (info->port_num & 1) ? TIMER2 : TIMER0;
2026
2027 /* IER2<7..4> = timer<3..0> interrupt enables (0=disabled) */
2028 write_reg(info, IER2, 0);
2029
2030 /* TMCS, Timer Control/Status Register
2031 *
2032 * 07 CMF, Compare match flag (read only) 1=match
2033 * 06 ECMI, CMF Interrupt Enable: 0=disabled
2034 * 05 Reserved, must be 0
2035 * 04 TME, Timer Enable
2036 * 03..00 Reserved, must be 0
2037 *
2038 * 0000 0000
2039 */
2040 write_reg(info, (unsigned char)(timer + TMCS), 0);
2041
2042 info->irq_occurred = TRUE;
2043
2044 if ( debug_level >= DEBUG_LEVEL_ISR )
2045 printk("%s(%d):%s isr_timer()\n",
2046 __FILE__,__LINE__,info->device_name);
2047 }
2048
isr_rxint(SLMP_INFO * info)2049 void isr_rxint(SLMP_INFO * info)
2050 {
2051 struct tty_struct *tty = info->tty;
2052 struct mgsl_icount *icount = &info->icount;
2053 unsigned char status = read_reg(info, SR1) & info->ie1_value & (FLGD + IDLD + CDCD + BRKD);
2054 unsigned char status2 = read_reg(info, SR2) & info->ie2_value & OVRN;
2055
2056 /* clear status bits */
2057 if (status)
2058 write_reg(info, SR1, status);
2059
2060 if (status2)
2061 write_reg(info, SR2, status2);
2062
2063 if ( debug_level >= DEBUG_LEVEL_ISR )
2064 printk("%s(%d):%s isr_rxint status=%02X %02x\n",
2065 __FILE__,__LINE__,info->device_name,status,status2);
2066
2067 if (info->params.mode == MGSL_MODE_ASYNC) {
2068 if (status & BRKD) {
2069 icount->brk++;
2070
2071 /* process break detection if tty control
2072 * is not set to ignore it
2073 */
2074 if ( tty ) {
2075 if (!(status & info->ignore_status_mask1)) {
2076 if (info->read_status_mask1 & BRKD) {
2077 *tty->flip.flag_buf_ptr = TTY_BREAK;
2078 if (info->flags & ASYNC_SAK)
2079 do_SAK(tty);
2080 }
2081 }
2082 }
2083 }
2084 }
2085 else {
2086 if (status & (FLGD|IDLD)) {
2087 if (status & FLGD)
2088 info->icount.exithunt++;
2089 else if (status & IDLD)
2090 info->icount.rxidle++;
2091 wake_up_interruptible(&info->event_wait_q);
2092 }
2093 }
2094
2095 if (status & CDCD) {
2096 /* simulate a common modem status change interrupt
2097 * for our handler
2098 */
2099 get_signals( info );
2100 isr_io_pin(info,
2101 MISCSTATUS_DCD_LATCHED|(info->serial_signals&SerialSignal_DCD));
2102 }
2103 }
2104
2105 /*
2106 * handle async rx data interrupts
2107 */
isr_rxrdy(SLMP_INFO * info)2108 void isr_rxrdy(SLMP_INFO * info)
2109 {
2110 u16 status;
2111 unsigned char DataByte;
2112 struct tty_struct *tty = info->tty;
2113 struct mgsl_icount *icount = &info->icount;
2114
2115 if ( debug_level >= DEBUG_LEVEL_ISR )
2116 printk("%s(%d):%s isr_rxrdy\n",
2117 __FILE__,__LINE__,info->device_name);
2118
2119 while((status = read_reg(info,CST0)) & BIT0)
2120 {
2121 DataByte = read_reg(info,TRB);
2122
2123 if ( tty ) {
2124 if (tty->flip.count >= TTY_FLIPBUF_SIZE)
2125 continue;
2126
2127 *tty->flip.char_buf_ptr = DataByte;
2128 *tty->flip.flag_buf_ptr = 0;
2129 }
2130
2131 icount->rx++;
2132
2133 if ( status & (PE + FRME + OVRN) ) {
2134 printk("%s(%d):%s rxerr=%04X\n",
2135 __FILE__,__LINE__,info->device_name,status);
2136
2137 /* update error statistics */
2138 if (status & PE)
2139 icount->parity++;
2140 else if (status & FRME)
2141 icount->frame++;
2142 else if (status & OVRN)
2143 icount->overrun++;
2144
2145 /* discard char if tty control flags say so */
2146 if (status & info->ignore_status_mask2)
2147 continue;
2148
2149 status &= info->read_status_mask2;
2150
2151 if ( tty ) {
2152 if (status & PE)
2153 *tty->flip.flag_buf_ptr = TTY_PARITY;
2154 else if (status & FRME)
2155 *tty->flip.flag_buf_ptr = TTY_FRAME;
2156 if (status & OVRN) {
2157 /* Overrun is special, since it's
2158 * reported immediately, and doesn't
2159 * affect the current character
2160 */
2161 if (tty->flip.count < TTY_FLIPBUF_SIZE) {
2162 tty->flip.count++;
2163 tty->flip.flag_buf_ptr++;
2164 tty->flip.char_buf_ptr++;
2165 *tty->flip.flag_buf_ptr = TTY_OVERRUN;
2166 }
2167 }
2168 }
2169 } /* end of if (error) */
2170
2171 if ( tty ) {
2172 tty->flip.flag_buf_ptr++;
2173 tty->flip.char_buf_ptr++;
2174 tty->flip.count++;
2175 }
2176 }
2177
2178 if ( debug_level >= DEBUG_LEVEL_ISR ) {
2179 printk("%s(%d):%s isr_rxrdy() flip count=%d\n",
2180 __FILE__,__LINE__,info->device_name,
2181 tty ? tty->flip.count : 0);
2182 printk("%s(%d):%s rx=%d brk=%d parity=%d frame=%d overrun=%d\n",
2183 __FILE__,__LINE__,info->device_name,
2184 icount->rx,icount->brk,icount->parity,
2185 icount->frame,icount->overrun);
2186 }
2187
2188 if ( tty && tty->flip.count )
2189 tty_flip_buffer_push(tty);
2190 }
2191
isr_txeom(SLMP_INFO * info,unsigned char status)2192 void isr_txeom(SLMP_INFO * info, unsigned char status)
2193 {
2194 if ( debug_level >= DEBUG_LEVEL_ISR )
2195 printk("%s(%d):%s isr_txeom status=%02x\n",
2196 __FILE__,__LINE__,info->device_name,status);
2197
2198 write_reg(info, TXDMA + DIR, 0x00); /* disable Tx DMA IRQs */
2199 write_reg(info, TXDMA + DSR, 0xc0); /* clear IRQs and disable DMA */
2200 write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
2201
2202 if (status & UDRN) {
2203 write_reg(info, CMD, TXRESET);
2204 write_reg(info, CMD, TXENABLE);
2205 } else
2206 write_reg(info, CMD, TXBUFCLR);
2207
2208 /* disable and clear tx interrupts */
2209 info->ie0_value &= ~TXRDYE;
2210 info->ie1_value &= ~(IDLE + UDRN);
2211 write_reg16(info, IE0, (unsigned short)((info->ie1_value << 8) + info->ie0_value));
2212 write_reg(info, SR1, (unsigned char)(UDRN + IDLE));
2213
2214 if ( info->tx_active ) {
2215 if (info->params.mode != MGSL_MODE_ASYNC) {
2216 if (status & UDRN)
2217 info->icount.txunder++;
2218 else if (status & IDLE)
2219 info->icount.txok++;
2220 }
2221
2222 info->tx_active = 0;
2223 info->tx_count = info->tx_put = info->tx_get = 0;
2224
2225 del_timer(&info->tx_timer);
2226
2227 if (info->params.mode != MGSL_MODE_ASYNC && info->drop_rts_on_tx_done ) {
2228 info->serial_signals &= ~SerialSignal_RTS;
2229 info->drop_rts_on_tx_done = 0;
2230 set_signals(info);
2231 }
2232
2233 #ifdef CONFIG_SYNCLINK_SYNCPPP
2234 if (info->netcount)
2235 sppp_tx_done(info);
2236 else
2237 #endif
2238 {
2239 if (info->tty && (info->tty->stopped || info->tty->hw_stopped)) {
2240 tx_stop(info);
2241 return;
2242 }
2243 info->pending_bh |= BH_TRANSMIT;
2244 }
2245 }
2246 }
2247
2248
2249 /*
2250 * handle tx status interrupts
2251 */
isr_txint(SLMP_INFO * info)2252 void isr_txint(SLMP_INFO * info)
2253 {
2254 unsigned char status = read_reg(info, SR1) & info->ie1_value & (UDRN + IDLE + CCTS);
2255
2256 /* clear status bits */
2257 write_reg(info, SR1, status);
2258
2259 if ( debug_level >= DEBUG_LEVEL_ISR )
2260 printk("%s(%d):%s isr_txint status=%02x\n",
2261 __FILE__,__LINE__,info->device_name,status);
2262
2263 if (status & (UDRN + IDLE))
2264 isr_txeom(info, status);
2265
2266 if (status & CCTS) {
2267 /* simulate a common modem status change interrupt
2268 * for our handler
2269 */
2270 get_signals( info );
2271 isr_io_pin(info,
2272 MISCSTATUS_CTS_LATCHED|(info->serial_signals&SerialSignal_CTS));
2273
2274 }
2275 }
2276
2277 /*
2278 * handle async tx data interrupts
2279 */
isr_txrdy(SLMP_INFO * info)2280 void isr_txrdy(SLMP_INFO * info)
2281 {
2282 if ( debug_level >= DEBUG_LEVEL_ISR )
2283 printk("%s(%d):%s isr_txrdy() tx_count=%d\n",
2284 __FILE__,__LINE__,info->device_name,info->tx_count);
2285
2286 if (info->params.mode != MGSL_MODE_ASYNC) {
2287 /* disable TXRDY IRQ, enable IDLE IRQ */
2288 info->ie0_value &= ~TXRDYE;
2289 info->ie1_value |= IDLE;
2290 write_reg16(info, IE0, (unsigned short)((info->ie1_value << 8) + info->ie0_value));
2291 return;
2292 }
2293
2294 if (info->tty && (info->tty->stopped || info->tty->hw_stopped)) {
2295 tx_stop(info);
2296 return;
2297 }
2298
2299 if ( info->tx_count )
2300 tx_load_fifo( info );
2301 else {
2302 info->tx_active = 0;
2303 info->ie0_value &= ~TXRDYE;
2304 write_reg(info, IE0, info->ie0_value);
2305 }
2306
2307 if (info->tx_count < WAKEUP_CHARS)
2308 info->pending_bh |= BH_TRANSMIT;
2309 }
2310
isr_rxdmaok(SLMP_INFO * info)2311 void isr_rxdmaok(SLMP_INFO * info)
2312 {
2313 /* BIT7 = EOT (end of transfer)
2314 * BIT6 = EOM (end of message/frame)
2315 */
2316 unsigned char status = read_reg(info,RXDMA + DSR) & 0xc0;
2317
2318 /* clear IRQ (BIT0 must be 1 to prevent clearing DE bit) */
2319 write_reg(info, RXDMA + DSR, (unsigned char)(status | 1));
2320
2321 if ( debug_level >= DEBUG_LEVEL_ISR )
2322 printk("%s(%d):%s isr_rxdmaok(), status=%02x\n",
2323 __FILE__,__LINE__,info->device_name,status);
2324
2325 info->pending_bh |= BH_RECEIVE;
2326 }
2327
isr_rxdmaerror(SLMP_INFO * info)2328 void isr_rxdmaerror(SLMP_INFO * info)
2329 {
2330 /* BIT5 = BOF (buffer overflow)
2331 * BIT4 = COF (counter overflow)
2332 */
2333 unsigned char status = read_reg(info,RXDMA + DSR) & 0x30;
2334
2335 /* clear IRQ (BIT0 must be 1 to prevent clearing DE bit) */
2336 write_reg(info, RXDMA + DSR, (unsigned char)(status | 1));
2337
2338 if ( debug_level >= DEBUG_LEVEL_ISR )
2339 printk("%s(%d):%s isr_rxdmaerror(), status=%02x\n",
2340 __FILE__,__LINE__,info->device_name,status);
2341
2342 info->rx_overflow = TRUE;
2343 info->pending_bh |= BH_RECEIVE;
2344 }
2345
isr_txdmaok(SLMP_INFO * info)2346 void isr_txdmaok(SLMP_INFO * info)
2347 {
2348 unsigned char status_reg1 = read_reg(info, SR1);
2349
2350 write_reg(info, TXDMA + DIR, 0x00); /* disable Tx DMA IRQs */
2351 write_reg(info, TXDMA + DSR, 0xc0); /* clear IRQs and disable DMA */
2352 write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
2353
2354 if ( debug_level >= DEBUG_LEVEL_ISR )
2355 printk("%s(%d):%s isr_txdmaok(), status=%02x\n",
2356 __FILE__,__LINE__,info->device_name,status_reg1);
2357
2358 /* program TXRDY as FIFO empty flag, enable TXRDY IRQ */
2359 write_reg16(info, TRC0, 0);
2360 info->ie0_value |= TXRDYE;
2361 write_reg(info, IE0, info->ie0_value);
2362 }
2363
isr_txdmaerror(SLMP_INFO * info)2364 void isr_txdmaerror(SLMP_INFO * info)
2365 {
2366 /* BIT5 = BOF (buffer overflow)
2367 * BIT4 = COF (counter overflow)
2368 */
2369 unsigned char status = read_reg(info,TXDMA + DSR) & 0x30;
2370
2371 /* clear IRQ (BIT0 must be 1 to prevent clearing DE bit) */
2372 write_reg(info, TXDMA + DSR, (unsigned char)(status | 1));
2373
2374 if ( debug_level >= DEBUG_LEVEL_ISR )
2375 printk("%s(%d):%s isr_txdmaerror(), status=%02x\n",
2376 __FILE__,__LINE__,info->device_name,status);
2377 }
2378
2379 /* handle input serial signal changes
2380 */
isr_io_pin(SLMP_INFO * info,u16 status)2381 void isr_io_pin( SLMP_INFO *info, u16 status )
2382 {
2383 struct mgsl_icount *icount;
2384
2385 if ( debug_level >= DEBUG_LEVEL_ISR )
2386 printk("%s(%d):isr_io_pin status=%04X\n",
2387 __FILE__,__LINE__,status);
2388
2389 if (status & (MISCSTATUS_CTS_LATCHED | MISCSTATUS_DCD_LATCHED |
2390 MISCSTATUS_DSR_LATCHED | MISCSTATUS_RI_LATCHED) ) {
2391 icount = &info->icount;
2392 /* update input line counters */
2393 if (status & MISCSTATUS_RI_LATCHED) {
2394 icount->rng++;
2395 if ( status & SerialSignal_RI )
2396 info->input_signal_events.ri_up++;
2397 else
2398 info->input_signal_events.ri_down++;
2399 }
2400 if (status & MISCSTATUS_DSR_LATCHED) {
2401 icount->dsr++;
2402 if ( status & SerialSignal_DSR )
2403 info->input_signal_events.dsr_up++;
2404 else
2405 info->input_signal_events.dsr_down++;
2406 }
2407 if (status & MISCSTATUS_DCD_LATCHED) {
2408 if ((info->dcd_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT) {
2409 info->ie1_value &= ~CDCD;
2410 write_reg(info, IE1, info->ie1_value);
2411 }
2412 icount->dcd++;
2413 if (status & SerialSignal_DCD) {
2414 info->input_signal_events.dcd_up++;
2415 #ifdef CONFIG_SYNCLINK_SYNCPPP
2416 if (info->netcount)
2417 sppp_reopen(info->netdev);
2418 #endif
2419 } else
2420 info->input_signal_events.dcd_down++;
2421 }
2422 if (status & MISCSTATUS_CTS_LATCHED)
2423 {
2424 if ((info->cts_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT) {
2425 info->ie1_value &= ~CCTS;
2426 write_reg(info, IE1, info->ie1_value);
2427 }
2428 icount->cts++;
2429 if ( status & SerialSignal_CTS )
2430 info->input_signal_events.cts_up++;
2431 else
2432 info->input_signal_events.cts_down++;
2433 }
2434 wake_up_interruptible(&info->status_event_wait_q);
2435 wake_up_interruptible(&info->event_wait_q);
2436
2437 if ( (info->flags & ASYNC_CHECK_CD) &&
2438 (status & MISCSTATUS_DCD_LATCHED) ) {
2439 if ( debug_level >= DEBUG_LEVEL_ISR )
2440 printk("%s CD now %s...", info->device_name,
2441 (status & SerialSignal_DCD) ? "on" : "off");
2442 if (status & SerialSignal_DCD)
2443 wake_up_interruptible(&info->open_wait);
2444 else if (!((info->flags & ASYNC_CALLOUT_ACTIVE) &&
2445 (info->flags & ASYNC_CALLOUT_NOHUP))) {
2446 if ( debug_level >= DEBUG_LEVEL_ISR )
2447 printk("doing serial hangup...");
2448 if (info->tty)
2449 tty_hangup(info->tty);
2450 }
2451 }
2452
2453 if ( (info->flags & ASYNC_CTS_FLOW) &&
2454 (status & MISCSTATUS_CTS_LATCHED) ) {
2455 if ( info->tty ) {
2456 if (info->tty->hw_stopped) {
2457 if (status & SerialSignal_CTS) {
2458 if ( debug_level >= DEBUG_LEVEL_ISR )
2459 printk("CTS tx start...");
2460 info->tty->hw_stopped = 0;
2461 tx_start(info);
2462 info->pending_bh |= BH_TRANSMIT;
2463 return;
2464 }
2465 } else {
2466 if (!(status & SerialSignal_CTS)) {
2467 if ( debug_level >= DEBUG_LEVEL_ISR )
2468 printk("CTS tx stop...");
2469 info->tty->hw_stopped = 1;
2470 tx_stop(info);
2471 }
2472 }
2473 }
2474 }
2475 }
2476
2477 info->pending_bh |= BH_STATUS;
2478 }
2479
2480 /* Interrupt service routine entry point.
2481 *
2482 * Arguments:
2483 * irq interrupt number that caused interrupt
2484 * dev_id device ID supplied during interrupt registration
2485 * regs interrupted processor context
2486 */
synclinkmp_interrupt(int irq,void * dev_id,struct pt_regs * regs)2487 static void synclinkmp_interrupt(int irq, void *dev_id, struct pt_regs * regs)
2488 {
2489 SLMP_INFO * info;
2490 unsigned char status, status0, status1=0;
2491 unsigned char dmastatus, dmastatus0, dmastatus1=0;
2492 unsigned char timerstatus0, timerstatus1=0;
2493 unsigned char shift;
2494 unsigned int i;
2495 unsigned short tmp;
2496
2497 if ( debug_level >= DEBUG_LEVEL_ISR )
2498 printk("%s(%d): synclinkmp_interrupt(%d)entry.\n",
2499 __FILE__,__LINE__,irq);
2500
2501 info = (SLMP_INFO *)dev_id;
2502 if (!info)
2503 return;
2504
2505 spin_lock(&info->lock);
2506
2507 for(;;) {
2508
2509 /* get status for SCA0 (ports 0-1) */
2510 tmp = read_reg16(info, ISR0); /* get ISR0 and ISR1 in one read */
2511 status0 = (unsigned char)tmp;
2512 dmastatus0 = (unsigned char)(tmp>>8);
2513 timerstatus0 = read_reg(info, ISR2);
2514
2515 if ( debug_level >= DEBUG_LEVEL_ISR )
2516 printk("%s(%d):%s status0=%02x, dmastatus0=%02x, timerstatus0=%02x\n",
2517 __FILE__,__LINE__,info->device_name,
2518 status0,dmastatus0,timerstatus0);
2519
2520 if (info->port_count == 4) {
2521 /* get status for SCA1 (ports 2-3) */
2522 tmp = read_reg16(info->port_array[2], ISR0);
2523 status1 = (unsigned char)tmp;
2524 dmastatus1 = (unsigned char)(tmp>>8);
2525 timerstatus1 = read_reg(info->port_array[2], ISR2);
2526
2527 if ( debug_level >= DEBUG_LEVEL_ISR )
2528 printk("%s(%d):%s status1=%02x, dmastatus1=%02x, timerstatus1=%02x\n",
2529 __FILE__,__LINE__,info->device_name,
2530 status1,dmastatus1,timerstatus1);
2531 }
2532
2533 if (!status0 && !dmastatus0 && !timerstatus0 &&
2534 !status1 && !dmastatus1 && !timerstatus1)
2535 break;
2536
2537 for(i=0; i < info->port_count ; i++) {
2538 if (info->port_array[i] == NULL)
2539 continue;
2540 if (i < 2) {
2541 status = status0;
2542 dmastatus = dmastatus0;
2543 } else {
2544 status = status1;
2545 dmastatus = dmastatus1;
2546 }
2547
2548 shift = i & 1 ? 4 :0;
2549
2550 if (status & BIT0 << shift)
2551 isr_rxrdy(info->port_array[i]);
2552 if (status & BIT1 << shift)
2553 isr_txrdy(info->port_array[i]);
2554 if (status & BIT2 << shift)
2555 isr_rxint(info->port_array[i]);
2556 if (status & BIT3 << shift)
2557 isr_txint(info->port_array[i]);
2558
2559 if (dmastatus & BIT0 << shift)
2560 isr_rxdmaerror(info->port_array[i]);
2561 if (dmastatus & BIT1 << shift)
2562 isr_rxdmaok(info->port_array[i]);
2563 if (dmastatus & BIT2 << shift)
2564 isr_txdmaerror(info->port_array[i]);
2565 if (dmastatus & BIT3 << shift)
2566 isr_txdmaok(info->port_array[i]);
2567 }
2568
2569 if (timerstatus0 & (BIT5 | BIT4))
2570 isr_timer(info->port_array[0]);
2571 if (timerstatus0 & (BIT7 | BIT6))
2572 isr_timer(info->port_array[1]);
2573 if (timerstatus1 & (BIT5 | BIT4))
2574 isr_timer(info->port_array[2]);
2575 if (timerstatus1 & (BIT7 | BIT6))
2576 isr_timer(info->port_array[3]);
2577 }
2578
2579 for(i=0; i < info->port_count ; i++) {
2580 SLMP_INFO * port = info->port_array[i];
2581
2582 /* Request bottom half processing if there's something
2583 * for it to do and the bh is not already running.
2584 *
2585 * Note: startup adapter diags require interrupts.
2586 * do not request bottom half processing if the
2587 * device is not open in a normal mode.
2588 */
2589 if ( port && (port->count || port->netcount) &&
2590 port->pending_bh && !port->bh_running &&
2591 !port->bh_requested ) {
2592 if ( debug_level >= DEBUG_LEVEL_ISR )
2593 printk("%s(%d):%s queueing bh task.\n",
2594 __FILE__,__LINE__,port->device_name);
2595 queue_task(&port->task, &tq_immediate);
2596 mark_bh(IMMEDIATE_BH);
2597 port->bh_requested = 1;
2598 }
2599 }
2600
2601 spin_unlock(&info->lock);
2602
2603 if ( debug_level >= DEBUG_LEVEL_ISR )
2604 printk("%s(%d):synclinkmp_interrupt(%d)exit.\n",
2605 __FILE__,__LINE__,irq);
2606 }
2607
2608 /* Initialize and start device.
2609 */
startup(SLMP_INFO * info)2610 static int startup(SLMP_INFO * info)
2611 {
2612 if ( debug_level >= DEBUG_LEVEL_INFO )
2613 printk("%s(%d):%s tx_releaseup()\n",__FILE__,__LINE__,info->device_name);
2614
2615 if (info->flags & ASYNC_INITIALIZED)
2616 return 0;
2617
2618 if (!info->tx_buf) {
2619 info->tx_buf = (unsigned char *)kmalloc(info->max_frame_size, GFP_KERNEL);
2620 if (!info->tx_buf) {
2621 printk(KERN_ERR"%s(%d):%s can't allocate transmit buffer\n",
2622 __FILE__,__LINE__,info->device_name);
2623 return -ENOMEM;
2624 }
2625 }
2626
2627 info->pending_bh = 0;
2628
2629 init_timer(&info->tx_timer);
2630 info->tx_timer.data = (unsigned long)info;
2631 info->tx_timer.function = tx_timeout;
2632
2633 /* program hardware for current parameters */
2634 reset_port(info);
2635
2636 change_params(info);
2637
2638 init_timer(&info->status_timer);
2639 info->status_timer.data = (unsigned long)info;
2640 info->status_timer.function = status_timeout;
2641 info->status_timer.expires = jiffies + jiffies_from_ms(10);
2642 add_timer(&info->status_timer);
2643
2644 if (info->tty)
2645 clear_bit(TTY_IO_ERROR, &info->tty->flags);
2646
2647 info->flags |= ASYNC_INITIALIZED;
2648
2649 return 0;
2650 }
2651
2652 /* Called by close() and hangup() to shutdown hardware
2653 */
shutdown(SLMP_INFO * info)2654 static void shutdown(SLMP_INFO * info)
2655 {
2656 unsigned long flags;
2657
2658 if (!(info->flags & ASYNC_INITIALIZED))
2659 return;
2660
2661 if (debug_level >= DEBUG_LEVEL_INFO)
2662 printk("%s(%d):%s synclinkmp_shutdown()\n",
2663 __FILE__,__LINE__, info->device_name );
2664
2665 /* clear status wait queue because status changes */
2666 /* can't happen after shutting down the hardware */
2667 wake_up_interruptible(&info->status_event_wait_q);
2668 wake_up_interruptible(&info->event_wait_q);
2669
2670 del_timer(&info->tx_timer);
2671 del_timer(&info->status_timer);
2672
2673 if (info->tx_buf) {
2674 free_page((unsigned long) info->tx_buf);
2675 info->tx_buf = 0;
2676 }
2677
2678 spin_lock_irqsave(&info->lock,flags);
2679
2680 reset_port(info);
2681
2682 if (!info->tty || info->tty->termios->c_cflag & HUPCL) {
2683 info->serial_signals &= ~(SerialSignal_DTR + SerialSignal_RTS);
2684 set_signals(info);
2685 }
2686
2687 spin_unlock_irqrestore(&info->lock,flags);
2688
2689 if (info->tty)
2690 set_bit(TTY_IO_ERROR, &info->tty->flags);
2691
2692 info->flags &= ~ASYNC_INITIALIZED;
2693 }
2694
program_hw(SLMP_INFO * info)2695 static void program_hw(SLMP_INFO *info)
2696 {
2697 unsigned long flags;
2698
2699 spin_lock_irqsave(&info->lock,flags);
2700
2701 rx_stop(info);
2702 tx_stop(info);
2703
2704 info->tx_count = info->tx_put = info->tx_get = 0;
2705
2706 if (info->params.mode == MGSL_MODE_HDLC || info->netcount)
2707 hdlc_mode(info);
2708 else
2709 async_mode(info);
2710
2711 set_signals(info);
2712
2713 info->dcd_chkcount = 0;
2714 info->cts_chkcount = 0;
2715 info->ri_chkcount = 0;
2716 info->dsr_chkcount = 0;
2717
2718 info->ie1_value |= (CDCD|CCTS);
2719 write_reg(info, IE1, info->ie1_value);
2720
2721 get_signals(info);
2722
2723 if (info->netcount || (info->tty && info->tty->termios->c_cflag & CREAD) )
2724 rx_start(info);
2725
2726 spin_unlock_irqrestore(&info->lock,flags);
2727 }
2728
2729 /* Reconfigure adapter based on new parameters
2730 */
change_params(SLMP_INFO * info)2731 static void change_params(SLMP_INFO *info)
2732 {
2733 unsigned cflag;
2734 int bits_per_char;
2735
2736 if (!info->tty || !info->tty->termios)
2737 return;
2738
2739 if (debug_level >= DEBUG_LEVEL_INFO)
2740 printk("%s(%d):%s change_params()\n",
2741 __FILE__,__LINE__, info->device_name );
2742
2743 cflag = info->tty->termios->c_cflag;
2744
2745 /* if B0 rate (hangup) specified then negate DTR and RTS */
2746 /* otherwise assert DTR and RTS */
2747 if (cflag & CBAUD)
2748 info->serial_signals |= SerialSignal_RTS + SerialSignal_DTR;
2749 else
2750 info->serial_signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
2751
2752 /* byte size and parity */
2753
2754 switch (cflag & CSIZE) {
2755 case CS5: info->params.data_bits = 5; break;
2756 case CS6: info->params.data_bits = 6; break;
2757 case CS7: info->params.data_bits = 7; break;
2758 case CS8: info->params.data_bits = 8; break;
2759 /* Never happens, but GCC is too dumb to figure it out */
2760 default: info->params.data_bits = 7; break;
2761 }
2762
2763 if (cflag & CSTOPB)
2764 info->params.stop_bits = 2;
2765 else
2766 info->params.stop_bits = 1;
2767
2768 info->params.parity = ASYNC_PARITY_NONE;
2769 if (cflag & PARENB) {
2770 if (cflag & PARODD)
2771 info->params.parity = ASYNC_PARITY_ODD;
2772 else
2773 info->params.parity = ASYNC_PARITY_EVEN;
2774 #ifdef CMSPAR
2775 if (cflag & CMSPAR)
2776 info->params.parity = ASYNC_PARITY_SPACE;
2777 #endif
2778 }
2779
2780 /* calculate number of jiffies to transmit a full
2781 * FIFO (32 bytes) at specified data rate
2782 */
2783 bits_per_char = info->params.data_bits +
2784 info->params.stop_bits + 1;
2785
2786 /* if port data rate is set to 460800 or less then
2787 * allow tty settings to override, otherwise keep the
2788 * current data rate.
2789 */
2790 if (info->params.data_rate <= 460800) {
2791 info->params.data_rate = tty_get_baud_rate(info->tty);
2792 }
2793
2794 if ( info->params.data_rate ) {
2795 info->timeout = (32*HZ*bits_per_char) /
2796 info->params.data_rate;
2797 }
2798 info->timeout += HZ/50; /* Add .02 seconds of slop */
2799
2800 if (cflag & CRTSCTS)
2801 info->flags |= ASYNC_CTS_FLOW;
2802 else
2803 info->flags &= ~ASYNC_CTS_FLOW;
2804
2805 if (cflag & CLOCAL)
2806 info->flags &= ~ASYNC_CHECK_CD;
2807 else
2808 info->flags |= ASYNC_CHECK_CD;
2809
2810 /* process tty input control flags */
2811
2812 info->read_status_mask2 = OVRN;
2813 if (I_INPCK(info->tty))
2814 info->read_status_mask2 |= PE | FRME;
2815 if (I_BRKINT(info->tty) || I_PARMRK(info->tty))
2816 info->read_status_mask1 |= BRKD;
2817 if (I_IGNPAR(info->tty))
2818 info->ignore_status_mask2 |= PE | FRME;
2819 if (I_IGNBRK(info->tty)) {
2820 info->ignore_status_mask1 |= BRKD;
2821 /* If ignoring parity and break indicators, ignore
2822 * overruns too. (For real raw support).
2823 */
2824 if (I_IGNPAR(info->tty))
2825 info->ignore_status_mask2 |= OVRN;
2826 }
2827
2828 program_hw(info);
2829 }
2830
get_stats(SLMP_INFO * info,struct mgsl_icount * user_icount)2831 static int get_stats(SLMP_INFO * info, struct mgsl_icount *user_icount)
2832 {
2833 int err;
2834
2835 if (debug_level >= DEBUG_LEVEL_INFO)
2836 printk("%s(%d):%s get_params()\n",
2837 __FILE__,__LINE__, info->device_name);
2838
2839 COPY_TO_USER(err,user_icount, &info->icount, sizeof(struct mgsl_icount));
2840 if (err) {
2841 if ( debug_level >= DEBUG_LEVEL_INFO )
2842 printk( "%s(%d):%s get_stats() user buffer copy failed\n",
2843 __FILE__,__LINE__,info->device_name);
2844 return -EFAULT;
2845 }
2846
2847 return 0;
2848 }
2849
get_params(SLMP_INFO * info,MGSL_PARAMS * user_params)2850 static int get_params(SLMP_INFO * info, MGSL_PARAMS *user_params)
2851 {
2852 int err;
2853 if (debug_level >= DEBUG_LEVEL_INFO)
2854 printk("%s(%d):%s get_params()\n",
2855 __FILE__,__LINE__, info->device_name);
2856
2857 COPY_TO_USER(err,user_params, &info->params, sizeof(MGSL_PARAMS));
2858 if (err) {
2859 if ( debug_level >= DEBUG_LEVEL_INFO )
2860 printk( "%s(%d):%s get_params() user buffer copy failed\n",
2861 __FILE__,__LINE__,info->device_name);
2862 return -EFAULT;
2863 }
2864
2865 return 0;
2866 }
2867
set_params(SLMP_INFO * info,MGSL_PARAMS * new_params)2868 static int set_params(SLMP_INFO * info, MGSL_PARAMS *new_params)
2869 {
2870 unsigned long flags;
2871 MGSL_PARAMS tmp_params;
2872 int err;
2873
2874 if (debug_level >= DEBUG_LEVEL_INFO)
2875 printk("%s(%d):%s set_params\n",
2876 __FILE__,__LINE__,info->device_name );
2877 COPY_FROM_USER(err,&tmp_params, new_params, sizeof(MGSL_PARAMS));
2878 if (err) {
2879 if ( debug_level >= DEBUG_LEVEL_INFO )
2880 printk( "%s(%d):%s set_params() user buffer copy failed\n",
2881 __FILE__,__LINE__,info->device_name);
2882 return -EFAULT;
2883 }
2884
2885 spin_lock_irqsave(&info->lock,flags);
2886 memcpy(&info->params,&tmp_params,sizeof(MGSL_PARAMS));
2887 spin_unlock_irqrestore(&info->lock,flags);
2888
2889 change_params(info);
2890
2891 return 0;
2892 }
2893
get_txidle(SLMP_INFO * info,int * idle_mode)2894 static int get_txidle(SLMP_INFO * info, int*idle_mode)
2895 {
2896 int err;
2897
2898 if (debug_level >= DEBUG_LEVEL_INFO)
2899 printk("%s(%d):%s get_txidle()=%d\n",
2900 __FILE__,__LINE__, info->device_name, info->idle_mode);
2901
2902 COPY_TO_USER(err,idle_mode, &info->idle_mode, sizeof(int));
2903 if (err) {
2904 if ( debug_level >= DEBUG_LEVEL_INFO )
2905 printk( "%s(%d):%s get_txidle() user buffer copy failed\n",
2906 __FILE__,__LINE__,info->device_name);
2907 return -EFAULT;
2908 }
2909
2910 return 0;
2911 }
2912
set_txidle(SLMP_INFO * info,int idle_mode)2913 static int set_txidle(SLMP_INFO * info, int idle_mode)
2914 {
2915 unsigned long flags;
2916
2917 if (debug_level >= DEBUG_LEVEL_INFO)
2918 printk("%s(%d):%s set_txidle(%d)\n",
2919 __FILE__,__LINE__,info->device_name, idle_mode );
2920
2921 spin_lock_irqsave(&info->lock,flags);
2922 info->idle_mode = idle_mode;
2923 tx_set_idle( info );
2924 spin_unlock_irqrestore(&info->lock,flags);
2925 return 0;
2926 }
2927
tx_enable(SLMP_INFO * info,int enable)2928 static int tx_enable(SLMP_INFO * info, int enable)
2929 {
2930 unsigned long flags;
2931
2932 if (debug_level >= DEBUG_LEVEL_INFO)
2933 printk("%s(%d):%s tx_enable(%d)\n",
2934 __FILE__,__LINE__,info->device_name, enable);
2935
2936 spin_lock_irqsave(&info->lock,flags);
2937 if ( enable ) {
2938 if ( !info->tx_enabled ) {
2939 tx_start(info);
2940 }
2941 } else {
2942 if ( info->tx_enabled )
2943 tx_stop(info);
2944 }
2945 spin_unlock_irqrestore(&info->lock,flags);
2946 return 0;
2947 }
2948
2949 /* abort send HDLC frame
2950 */
tx_abort(SLMP_INFO * info)2951 static int tx_abort(SLMP_INFO * info)
2952 {
2953 unsigned long flags;
2954
2955 if (debug_level >= DEBUG_LEVEL_INFO)
2956 printk("%s(%d):%s tx_abort()\n",
2957 __FILE__,__LINE__,info->device_name);
2958
2959 spin_lock_irqsave(&info->lock,flags);
2960 if ( info->tx_active && info->params.mode == MGSL_MODE_HDLC ) {
2961 info->ie1_value &= ~UDRN;
2962 info->ie1_value |= IDLE;
2963 write_reg(info, IE1, info->ie1_value); /* disable tx status interrupts */
2964 write_reg(info, SR1, (unsigned char)(IDLE + UDRN)); /* clear pending */
2965
2966 write_reg(info, TXDMA + DSR, 0); /* disable DMA channel */
2967 write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
2968
2969 write_reg(info, CMD, TXABORT);
2970 }
2971 spin_unlock_irqrestore(&info->lock,flags);
2972 return 0;
2973 }
2974
rx_enable(SLMP_INFO * info,int enable)2975 static int rx_enable(SLMP_INFO * info, int enable)
2976 {
2977 unsigned long flags;
2978
2979 if (debug_level >= DEBUG_LEVEL_INFO)
2980 printk("%s(%d):%s rx_enable(%d)\n",
2981 __FILE__,__LINE__,info->device_name,enable);
2982
2983 spin_lock_irqsave(&info->lock,flags);
2984 if ( enable ) {
2985 if ( !info->rx_enabled )
2986 rx_start(info);
2987 } else {
2988 if ( info->rx_enabled )
2989 rx_stop(info);
2990 }
2991 spin_unlock_irqrestore(&info->lock,flags);
2992 return 0;
2993 }
2994
map_status(int signals)2995 static int map_status(int signals)
2996 {
2997 /* Map status bits to API event bits */
2998
2999 return ((signals & SerialSignal_DSR) ? MgslEvent_DsrActive : MgslEvent_DsrInactive) +
3000 ((signals & SerialSignal_CTS) ? MgslEvent_CtsActive : MgslEvent_CtsInactive) +
3001 ((signals & SerialSignal_DCD) ? MgslEvent_DcdActive : MgslEvent_DcdInactive) +
3002 ((signals & SerialSignal_RI) ? MgslEvent_RiActive : MgslEvent_RiInactive);
3003 }
3004
3005 /* wait for specified event to occur
3006 */
wait_mgsl_event(SLMP_INFO * info,int * mask_ptr)3007 static int wait_mgsl_event(SLMP_INFO * info, int * mask_ptr)
3008 {
3009 unsigned long flags;
3010 int s;
3011 int rc=0;
3012 struct mgsl_icount cprev, cnow;
3013 int events;
3014 int mask;
3015 struct _input_signal_events oldsigs, newsigs;
3016 DECLARE_WAITQUEUE(wait, current);
3017
3018 COPY_FROM_USER(rc,&mask, mask_ptr, sizeof(int));
3019 if (rc) {
3020 return -EFAULT;
3021 }
3022
3023 if (debug_level >= DEBUG_LEVEL_INFO)
3024 printk("%s(%d):%s wait_mgsl_event(%d)\n",
3025 __FILE__,__LINE__,info->device_name,mask);
3026
3027 spin_lock_irqsave(&info->lock,flags);
3028
3029 /* return immediately if state matches requested events */
3030 get_signals(info);
3031 s = map_status(info->serial_signals);
3032
3033 events = mask &
3034 ( ((s & SerialSignal_DSR) ? MgslEvent_DsrActive:MgslEvent_DsrInactive) +
3035 ((s & SerialSignal_DCD) ? MgslEvent_DcdActive:MgslEvent_DcdInactive) +
3036 ((s & SerialSignal_CTS) ? MgslEvent_CtsActive:MgslEvent_CtsInactive) +
3037 ((s & SerialSignal_RI) ? MgslEvent_RiActive :MgslEvent_RiInactive) );
3038 if (events) {
3039 spin_unlock_irqrestore(&info->lock,flags);
3040 goto exit;
3041 }
3042
3043 /* save current irq counts */
3044 cprev = info->icount;
3045 oldsigs = info->input_signal_events;
3046
3047 /* enable hunt and idle irqs if needed */
3048 if (mask & (MgslEvent_ExitHuntMode+MgslEvent_IdleReceived)) {
3049 unsigned char oldval = info->ie1_value;
3050 unsigned char newval = oldval +
3051 (mask & MgslEvent_ExitHuntMode ? FLGD:0) +
3052 (mask & MgslEvent_IdleReceived ? IDLD:0);
3053 if ( oldval != newval ) {
3054 info->ie1_value = newval;
3055 write_reg(info, IE1, info->ie1_value);
3056 }
3057 }
3058
3059 set_current_state(TASK_INTERRUPTIBLE);
3060 add_wait_queue(&info->event_wait_q, &wait);
3061
3062 spin_unlock_irqrestore(&info->lock,flags);
3063
3064 for(;;) {
3065 schedule();
3066 if (signal_pending(current)) {
3067 rc = -ERESTARTSYS;
3068 break;
3069 }
3070
3071 /* get current irq counts */
3072 spin_lock_irqsave(&info->lock,flags);
3073 cnow = info->icount;
3074 newsigs = info->input_signal_events;
3075 set_current_state(TASK_INTERRUPTIBLE);
3076 spin_unlock_irqrestore(&info->lock,flags);
3077
3078 /* if no change, wait aborted for some reason */
3079 if (newsigs.dsr_up == oldsigs.dsr_up &&
3080 newsigs.dsr_down == oldsigs.dsr_down &&
3081 newsigs.dcd_up == oldsigs.dcd_up &&
3082 newsigs.dcd_down == oldsigs.dcd_down &&
3083 newsigs.cts_up == oldsigs.cts_up &&
3084 newsigs.cts_down == oldsigs.cts_down &&
3085 newsigs.ri_up == oldsigs.ri_up &&
3086 newsigs.ri_down == oldsigs.ri_down &&
3087 cnow.exithunt == cprev.exithunt &&
3088 cnow.rxidle == cprev.rxidle) {
3089 rc = -EIO;
3090 break;
3091 }
3092
3093 events = mask &
3094 ( (newsigs.dsr_up != oldsigs.dsr_up ? MgslEvent_DsrActive:0) +
3095 (newsigs.dsr_down != oldsigs.dsr_down ? MgslEvent_DsrInactive:0) +
3096 (newsigs.dcd_up != oldsigs.dcd_up ? MgslEvent_DcdActive:0) +
3097 (newsigs.dcd_down != oldsigs.dcd_down ? MgslEvent_DcdInactive:0) +
3098 (newsigs.cts_up != oldsigs.cts_up ? MgslEvent_CtsActive:0) +
3099 (newsigs.cts_down != oldsigs.cts_down ? MgslEvent_CtsInactive:0) +
3100 (newsigs.ri_up != oldsigs.ri_up ? MgslEvent_RiActive:0) +
3101 (newsigs.ri_down != oldsigs.ri_down ? MgslEvent_RiInactive:0) +
3102 (cnow.exithunt != cprev.exithunt ? MgslEvent_ExitHuntMode:0) +
3103 (cnow.rxidle != cprev.rxidle ? MgslEvent_IdleReceived:0) );
3104 if (events)
3105 break;
3106
3107 cprev = cnow;
3108 oldsigs = newsigs;
3109 }
3110
3111 remove_wait_queue(&info->event_wait_q, &wait);
3112 set_current_state(TASK_RUNNING);
3113
3114
3115 if (mask & (MgslEvent_ExitHuntMode + MgslEvent_IdleReceived)) {
3116 spin_lock_irqsave(&info->lock,flags);
3117 if (!waitqueue_active(&info->event_wait_q)) {
3118 /* disable enable exit hunt mode/idle rcvd IRQs */
3119 info->ie1_value &= ~(FLGD|IDLD);
3120 write_reg(info, IE1, info->ie1_value);
3121 }
3122 spin_unlock_irqrestore(&info->lock,flags);
3123 }
3124 exit:
3125 if ( rc == 0 )
3126 PUT_USER(rc, events, mask_ptr);
3127
3128 return rc;
3129 }
3130
modem_input_wait(SLMP_INFO * info,int arg)3131 static int modem_input_wait(SLMP_INFO *info,int arg)
3132 {
3133 unsigned long flags;
3134 int rc;
3135 struct mgsl_icount cprev, cnow;
3136 DECLARE_WAITQUEUE(wait, current);
3137
3138 /* save current irq counts */
3139 spin_lock_irqsave(&info->lock,flags);
3140 cprev = info->icount;
3141 add_wait_queue(&info->status_event_wait_q, &wait);
3142 set_current_state(TASK_INTERRUPTIBLE);
3143 spin_unlock_irqrestore(&info->lock,flags);
3144
3145 for(;;) {
3146 schedule();
3147 if (signal_pending(current)) {
3148 rc = -ERESTARTSYS;
3149 break;
3150 }
3151
3152 /* get new irq counts */
3153 spin_lock_irqsave(&info->lock,flags);
3154 cnow = info->icount;
3155 set_current_state(TASK_INTERRUPTIBLE);
3156 spin_unlock_irqrestore(&info->lock,flags);
3157
3158 /* if no change, wait aborted for some reason */
3159 if (cnow.rng == cprev.rng && cnow.dsr == cprev.dsr &&
3160 cnow.dcd == cprev.dcd && cnow.cts == cprev.cts) {
3161 rc = -EIO;
3162 break;
3163 }
3164
3165 /* check for change in caller specified modem input */
3166 if ((arg & TIOCM_RNG && cnow.rng != cprev.rng) ||
3167 (arg & TIOCM_DSR && cnow.dsr != cprev.dsr) ||
3168 (arg & TIOCM_CD && cnow.dcd != cprev.dcd) ||
3169 (arg & TIOCM_CTS && cnow.cts != cprev.cts)) {
3170 rc = 0;
3171 break;
3172 }
3173
3174 cprev = cnow;
3175 }
3176 remove_wait_queue(&info->status_event_wait_q, &wait);
3177 set_current_state(TASK_RUNNING);
3178 return rc;
3179 }
3180
3181 /* return the state of the serial control and status signals
3182 */
get_modem_info(SLMP_INFO * info,unsigned int * value)3183 static int get_modem_info(SLMP_INFO * info, unsigned int *value)
3184 {
3185 unsigned int result;
3186 unsigned long flags;
3187 int err;
3188
3189 spin_lock_irqsave(&info->lock,flags);
3190 get_signals(info);
3191 spin_unlock_irqrestore(&info->lock,flags);
3192
3193 result = ((info->serial_signals & SerialSignal_RTS) ? TIOCM_RTS:0) +
3194 ((info->serial_signals & SerialSignal_DTR) ? TIOCM_DTR:0) +
3195 ((info->serial_signals & SerialSignal_DCD) ? TIOCM_CAR:0) +
3196 ((info->serial_signals & SerialSignal_RI) ? TIOCM_RNG:0) +
3197 ((info->serial_signals & SerialSignal_DSR) ? TIOCM_DSR:0) +
3198 ((info->serial_signals & SerialSignal_CTS) ? TIOCM_CTS:0);
3199
3200 if (debug_level >= DEBUG_LEVEL_INFO)
3201 printk("%s(%d):%s synclinkmp_get_modem_info() value=%08X\n",
3202 __FILE__,__LINE__, info->device_name, result );
3203
3204 PUT_USER(err,result,value);
3205 return err;
3206 }
3207
3208 /* set modem control signals (DTR/RTS)
3209 *
3210 * cmd signal command: TIOCMBIS = set bit TIOCMBIC = clear bit
3211 * TIOCMSET = set/clear signal values
3212 * value bit mask for command
3213 */
set_modem_info(SLMP_INFO * info,unsigned int cmd,unsigned int * value)3214 static int set_modem_info(SLMP_INFO * info, unsigned int cmd,
3215 unsigned int *value)
3216 {
3217 int error;
3218 unsigned int arg;
3219 unsigned long flags;
3220
3221 if (debug_level >= DEBUG_LEVEL_INFO)
3222 printk("%s(%d):%s synclinkmp_set_modem_info()\n",
3223 __FILE__,__LINE__,info->device_name );
3224
3225 GET_USER(error,arg,value);
3226 if (error)
3227 return error;
3228
3229 switch (cmd) {
3230 case TIOCMBIS:
3231 if (arg & TIOCM_RTS)
3232 info->serial_signals |= SerialSignal_RTS;
3233 if (arg & TIOCM_DTR)
3234 info->serial_signals |= SerialSignal_DTR;
3235 break;
3236 case TIOCMBIC:
3237 if (arg & TIOCM_RTS)
3238 info->serial_signals &= ~SerialSignal_RTS;
3239 if (arg & TIOCM_DTR)
3240 info->serial_signals &= ~SerialSignal_DTR;
3241 break;
3242 case TIOCMSET:
3243 if (arg & TIOCM_RTS)
3244 info->serial_signals |= SerialSignal_RTS;
3245 else
3246 info->serial_signals &= ~SerialSignal_RTS;
3247
3248 if (arg & TIOCM_DTR)
3249 info->serial_signals |= SerialSignal_DTR;
3250 else
3251 info->serial_signals &= ~SerialSignal_DTR;
3252 break;
3253 default:
3254 return -EINVAL;
3255 }
3256
3257 spin_lock_irqsave(&info->lock,flags);
3258 set_signals(info);
3259 spin_unlock_irqrestore(&info->lock,flags);
3260
3261 return 0;
3262 }
3263
3264
3265
3266 /* Block the current process until the specified port is ready to open.
3267 */
block_til_ready(struct tty_struct * tty,struct file * filp,SLMP_INFO * info)3268 static int block_til_ready(struct tty_struct *tty, struct file *filp,
3269 SLMP_INFO *info)
3270 {
3271 DECLARE_WAITQUEUE(wait, current);
3272 int retval;
3273 int do_clocal = 0, extra_count = 0;
3274 unsigned long flags;
3275
3276 if (debug_level >= DEBUG_LEVEL_INFO)
3277 printk("%s(%d):%s block_til_ready()\n",
3278 __FILE__,__LINE__, tty->driver.name );
3279
3280 if (tty->driver.subtype == SERIAL_TYPE_CALLOUT) {
3281 /* this is a callout device */
3282 /* just verify that normal device is not in use */
3283 if (info->flags & ASYNC_NORMAL_ACTIVE)
3284 return -EBUSY;
3285 if ((info->flags & ASYNC_CALLOUT_ACTIVE) &&
3286 (info->flags & ASYNC_SESSION_LOCKOUT) &&
3287 (info->session != current->session))
3288 return -EBUSY;
3289 if ((info->flags & ASYNC_CALLOUT_ACTIVE) &&
3290 (info->flags & ASYNC_PGRP_LOCKOUT) &&
3291 (info->pgrp != current->pgrp))
3292 return -EBUSY;
3293 info->flags |= ASYNC_CALLOUT_ACTIVE;
3294 return 0;
3295 }
3296
3297 if (filp->f_flags & O_NONBLOCK || tty->flags & (1 << TTY_IO_ERROR)){
3298 /* nonblock mode is set or port is not enabled */
3299 /* just verify that callout device is not active */
3300 if (info->flags & ASYNC_CALLOUT_ACTIVE)
3301 return -EBUSY;
3302 info->flags |= ASYNC_NORMAL_ACTIVE;
3303 return 0;
3304 }
3305
3306 if (info->flags & ASYNC_CALLOUT_ACTIVE) {
3307 if (info->normal_termios.c_cflag & CLOCAL)
3308 do_clocal = 1;
3309 } else {
3310 if (tty->termios->c_cflag & CLOCAL)
3311 do_clocal = 1;
3312 }
3313
3314 /* Wait for carrier detect and the line to become
3315 * free (i.e., not in use by the callout). While we are in
3316 * this loop, info->count is dropped by one, so that
3317 * close() knows when to free things. We restore it upon
3318 * exit, either normal or abnormal.
3319 */
3320
3321 retval = 0;
3322 add_wait_queue(&info->open_wait, &wait);
3323
3324 if (debug_level >= DEBUG_LEVEL_INFO)
3325 printk("%s(%d):%s block_til_ready() before block, count=%d\n",
3326 __FILE__,__LINE__, tty->driver.name, info->count );
3327
3328 save_flags(flags); cli();
3329 if (!tty_hung_up_p(filp)) {
3330 extra_count = 1;
3331 info->count--;
3332 }
3333 restore_flags(flags);
3334 info->blocked_open++;
3335
3336 while (1) {
3337 if (!(info->flags & ASYNC_CALLOUT_ACTIVE) &&
3338 (tty->termios->c_cflag & CBAUD)) {
3339 spin_lock_irqsave(&info->lock,flags);
3340 info->serial_signals |= SerialSignal_RTS + SerialSignal_DTR;
3341 set_signals(info);
3342 spin_unlock_irqrestore(&info->lock,flags);
3343 }
3344
3345 set_current_state(TASK_INTERRUPTIBLE);
3346
3347 if (tty_hung_up_p(filp) || !(info->flags & ASYNC_INITIALIZED)){
3348 retval = (info->flags & ASYNC_HUP_NOTIFY) ?
3349 -EAGAIN : -ERESTARTSYS;
3350 break;
3351 }
3352
3353 spin_lock_irqsave(&info->lock,flags);
3354 get_signals(info);
3355 spin_unlock_irqrestore(&info->lock,flags);
3356
3357 if (!(info->flags & ASYNC_CALLOUT_ACTIVE) &&
3358 !(info->flags & ASYNC_CLOSING) &&
3359 (do_clocal || (info->serial_signals & SerialSignal_DCD)) ) {
3360 break;
3361 }
3362
3363 if (signal_pending(current)) {
3364 retval = -ERESTARTSYS;
3365 break;
3366 }
3367
3368 if (debug_level >= DEBUG_LEVEL_INFO)
3369 printk("%s(%d):%s block_til_ready() count=%d\n",
3370 __FILE__,__LINE__, tty->driver.name, info->count );
3371
3372 schedule();
3373 }
3374
3375 set_current_state(TASK_RUNNING);
3376 remove_wait_queue(&info->open_wait, &wait);
3377
3378 if (extra_count)
3379 info->count++;
3380 info->blocked_open--;
3381
3382 if (debug_level >= DEBUG_LEVEL_INFO)
3383 printk("%s(%d):%s block_til_ready() after, count=%d\n",
3384 __FILE__,__LINE__, tty->driver.name, info->count );
3385
3386 if (!retval)
3387 info->flags |= ASYNC_NORMAL_ACTIVE;
3388
3389 return retval;
3390 }
3391
alloc_dma_bufs(SLMP_INFO * info)3392 int alloc_dma_bufs(SLMP_INFO *info)
3393 {
3394 unsigned short BuffersPerFrame;
3395 unsigned short BufferCount;
3396
3397 // Force allocation to start at 64K boundary for each port.
3398 // This is necessary because *all* buffer descriptors for a port
3399 // *must* be in the same 64K block. All descriptors on a port
3400 // share a common 'base' address (upper 8 bits of 24 bits) programmed
3401 // into the CBP register.
3402 info->port_array[0]->last_mem_alloc = (SCA_MEM_SIZE/4) * info->port_num;
3403
3404 /* Calculate the number of DMA buffers necessary to hold the */
3405 /* largest allowable frame size. Note: If the max frame size is */
3406 /* not an even multiple of the DMA buffer size then we need to */
3407 /* round the buffer count per frame up one. */
3408
3409 BuffersPerFrame = (unsigned short)(info->max_frame_size/SCABUFSIZE);
3410 if ( info->max_frame_size % SCABUFSIZE )
3411 BuffersPerFrame++;
3412
3413 /* calculate total number of data buffers (SCABUFSIZE) possible
3414 * in one ports memory (SCA_MEM_SIZE/4) after allocating memory
3415 * for the descriptor list (BUFFERLISTSIZE).
3416 */
3417 BufferCount = (SCA_MEM_SIZE/4 - BUFFERLISTSIZE)/SCABUFSIZE;
3418
3419 /* limit number of buffers to maximum amount of descriptors */
3420 if (BufferCount > BUFFERLISTSIZE/sizeof(SCADESC))
3421 BufferCount = BUFFERLISTSIZE/sizeof(SCADESC);
3422
3423 /* use enough buffers to transmit one max size frame */
3424 info->tx_buf_count = BuffersPerFrame + 1;
3425
3426 /* never use more than half the available buffers for transmit */
3427 if (info->tx_buf_count > (BufferCount/2))
3428 info->tx_buf_count = BufferCount/2;
3429
3430 if (info->tx_buf_count > SCAMAXDESC)
3431 info->tx_buf_count = SCAMAXDESC;
3432
3433 /* use remaining buffers for receive */
3434 info->rx_buf_count = BufferCount - info->tx_buf_count;
3435
3436 if (info->rx_buf_count > SCAMAXDESC)
3437 info->rx_buf_count = SCAMAXDESC;
3438
3439 if ( debug_level >= DEBUG_LEVEL_INFO )
3440 printk("%s(%d):%s Allocating %d TX and %d RX DMA buffers.\n",
3441 __FILE__,__LINE__, info->device_name,
3442 info->tx_buf_count,info->rx_buf_count);
3443
3444 if ( alloc_buf_list( info ) < 0 ||
3445 alloc_frame_bufs(info,
3446 info->rx_buf_list,
3447 info->rx_buf_list_ex,
3448 info->rx_buf_count) < 0 ||
3449 alloc_frame_bufs(info,
3450 info->tx_buf_list,
3451 info->tx_buf_list_ex,
3452 info->tx_buf_count) < 0 ||
3453 alloc_tmp_rx_buf(info) < 0 ) {
3454 printk("%s(%d):%s Can't allocate DMA buffer memory\n",
3455 __FILE__,__LINE__, info->device_name);
3456 return -ENOMEM;
3457 }
3458
3459 rx_reset_buffers( info );
3460
3461 return 0;
3462 }
3463
3464 /* Allocate DMA buffers for the transmit and receive descriptor lists.
3465 */
alloc_buf_list(SLMP_INFO * info)3466 int alloc_buf_list(SLMP_INFO *info)
3467 {
3468 unsigned int i;
3469
3470 /* build list in adapter shared memory */
3471 info->buffer_list = info->memory_base + info->port_array[0]->last_mem_alloc;
3472 info->buffer_list_phys = info->port_array[0]->last_mem_alloc;
3473 info->port_array[0]->last_mem_alloc += BUFFERLISTSIZE;
3474
3475 memset(info->buffer_list, 0, BUFFERLISTSIZE);
3476
3477 /* Save virtual address pointers to the receive and */
3478 /* transmit buffer lists. (Receive 1st). These pointers will */
3479 /* be used by the processor to access the lists. */
3480 info->rx_buf_list = (SCADESC *)info->buffer_list;
3481
3482 info->tx_buf_list = (SCADESC *)info->buffer_list;
3483 info->tx_buf_list += info->rx_buf_count;
3484
3485 /* Build links for circular buffer entry lists (tx and rx)
3486 *
3487 * Note: links are physical addresses read by the SCA device
3488 * to determine the next buffer entry to use.
3489 */
3490
3491 for ( i = 0; i < info->rx_buf_count; i++ ) {
3492 /* calculate and store physical address of this buffer entry */
3493 info->rx_buf_list_ex[i].phys_entry =
3494 info->buffer_list_phys + (i * sizeof(SCABUFSIZE));
3495
3496 /* calculate and store physical address of */
3497 /* next entry in cirular list of entries */
3498 info->rx_buf_list[i].next = info->buffer_list_phys;
3499 if ( i < info->rx_buf_count - 1 )
3500 info->rx_buf_list[i].next += (i + 1) * sizeof(SCADESC);
3501
3502 info->rx_buf_list[i].length = SCABUFSIZE;
3503 }
3504
3505 for ( i = 0; i < info->tx_buf_count; i++ ) {
3506 /* calculate and store physical address of this buffer entry */
3507 info->tx_buf_list_ex[i].phys_entry = info->buffer_list_phys +
3508 ((info->rx_buf_count + i) * sizeof(SCADESC));
3509
3510 /* calculate and store physical address of */
3511 /* next entry in cirular list of entries */
3512
3513 info->tx_buf_list[i].next = info->buffer_list_phys +
3514 info->rx_buf_count * sizeof(SCADESC);
3515
3516 if ( i < info->tx_buf_count - 1 )
3517 info->tx_buf_list[i].next += (i + 1) * sizeof(SCADESC);
3518 }
3519
3520 return 0;
3521 }
3522
3523 /* Allocate the frame DMA buffers used by the specified buffer list.
3524 */
alloc_frame_bufs(SLMP_INFO * info,SCADESC * buf_list,SCADESC_EX * buf_list_ex,int count)3525 int alloc_frame_bufs(SLMP_INFO *info, SCADESC *buf_list,SCADESC_EX *buf_list_ex,int count)
3526 {
3527 int i;
3528 unsigned long phys_addr;
3529
3530 for ( i = 0; i < count; i++ ) {
3531 buf_list_ex[i].virt_addr = info->memory_base + info->port_array[0]->last_mem_alloc;
3532 phys_addr = info->port_array[0]->last_mem_alloc;
3533 info->port_array[0]->last_mem_alloc += SCABUFSIZE;
3534
3535 buf_list[i].buf_ptr = (unsigned short)phys_addr;
3536 buf_list[i].buf_base = (unsigned char)(phys_addr >> 16);
3537 }
3538
3539 return 0;
3540 }
3541
free_dma_bufs(SLMP_INFO * info)3542 void free_dma_bufs(SLMP_INFO *info)
3543 {
3544 info->buffer_list = NULL;
3545 info->rx_buf_list = NULL;
3546 info->tx_buf_list = NULL;
3547 }
3548
3549 /* allocate buffer large enough to hold max_frame_size.
3550 * This buffer is used to pass an assembled frame to the line discipline.
3551 */
alloc_tmp_rx_buf(SLMP_INFO * info)3552 int alloc_tmp_rx_buf(SLMP_INFO *info)
3553 {
3554 info->tmp_rx_buf = kmalloc(info->max_frame_size, GFP_KERNEL);
3555 if (info->tmp_rx_buf == NULL)
3556 return -ENOMEM;
3557 return 0;
3558 }
3559
free_tmp_rx_buf(SLMP_INFO * info)3560 void free_tmp_rx_buf(SLMP_INFO *info)
3561 {
3562 if (info->tmp_rx_buf)
3563 kfree(info->tmp_rx_buf);
3564 info->tmp_rx_buf = NULL;
3565 }
3566
claim_resources(SLMP_INFO * info)3567 int claim_resources(SLMP_INFO *info)
3568 {
3569 if (request_mem_region(info->phys_memory_base,SCA_MEM_SIZE,"synclinkmp") == NULL) {
3570 printk( "%s(%d):%s mem addr conflict, Addr=%08X\n",
3571 __FILE__,__LINE__,info->device_name, info->phys_memory_base);
3572 info->init_error = DiagStatus_AddressConflict;
3573 goto errout;
3574 }
3575 else
3576 info->shared_mem_requested = 1;
3577
3578 if (request_mem_region(info->phys_lcr_base + info->lcr_offset,128,"synclinkmp") == NULL) {
3579 printk( "%s(%d):%s lcr mem addr conflict, Addr=%08X\n",
3580 __FILE__,__LINE__,info->device_name, info->phys_lcr_base);
3581 info->init_error = DiagStatus_AddressConflict;
3582 goto errout;
3583 }
3584 else
3585 info->lcr_mem_requested = 1;
3586
3587 if (request_mem_region(info->phys_sca_base + info->sca_offset,SCA_BASE_SIZE,"synclinkmp") == NULL) {
3588 printk( "%s(%d):%s sca mem addr conflict, Addr=%08X\n",
3589 __FILE__,__LINE__,info->device_name, info->phys_sca_base);
3590 info->init_error = DiagStatus_AddressConflict;
3591 goto errout;
3592 }
3593 else
3594 info->sca_base_requested = 1;
3595
3596 if (request_mem_region(info->phys_statctrl_base + info->statctrl_offset,SCA_REG_SIZE,"synclinkmp") == NULL) {
3597 printk( "%s(%d):%s stat/ctrl mem addr conflict, Addr=%08X\n",
3598 __FILE__,__LINE__,info->device_name, info->phys_statctrl_base);
3599 info->init_error = DiagStatus_AddressConflict;
3600 goto errout;
3601 }
3602 else
3603 info->sca_statctrl_requested = 1;
3604
3605 info->memory_base = ioremap(info->phys_memory_base,SCA_MEM_SIZE);
3606 if (!info->memory_base) {
3607 printk( "%s(%d):%s Cant map shared memory, MemAddr=%08X\n",
3608 __FILE__,__LINE__,info->device_name, info->phys_memory_base );
3609 info->init_error = DiagStatus_CantAssignPciResources;
3610 goto errout;
3611 }
3612
3613 info->lcr_base = ioremap(info->phys_lcr_base,PAGE_SIZE);
3614 if (!info->lcr_base) {
3615 printk( "%s(%d):%s Cant map LCR memory, MemAddr=%08X\n",
3616 __FILE__,__LINE__,info->device_name, info->phys_lcr_base );
3617 info->init_error = DiagStatus_CantAssignPciResources;
3618 goto errout;
3619 }
3620 info->lcr_base += info->lcr_offset;
3621
3622 info->sca_base = ioremap(info->phys_sca_base,PAGE_SIZE);
3623 if (!info->sca_base) {
3624 printk( "%s(%d):%s Cant map SCA memory, MemAddr=%08X\n",
3625 __FILE__,__LINE__,info->device_name, info->phys_sca_base );
3626 info->init_error = DiagStatus_CantAssignPciResources;
3627 goto errout;
3628 }
3629 info->sca_base += info->sca_offset;
3630
3631 info->statctrl_base = ioremap(info->phys_statctrl_base,PAGE_SIZE);
3632 if (!info->statctrl_base) {
3633 printk( "%s(%d):%s Cant map SCA Status/Control memory, MemAddr=%08X\n",
3634 __FILE__,__LINE__,info->device_name, info->phys_statctrl_base );
3635 info->init_error = DiagStatus_CantAssignPciResources;
3636 goto errout;
3637 }
3638 info->statctrl_base += info->statctrl_offset;
3639
3640 if ( !memory_test(info) ) {
3641 printk( "%s(%d):Shared Memory Test failed for device %s MemAddr=%08X\n",
3642 __FILE__,__LINE__,info->device_name, info->phys_memory_base );
3643 info->init_error = DiagStatus_MemoryError;
3644 goto errout;
3645 }
3646
3647 return 0;
3648
3649 errout:
3650 release_resources( info );
3651 return -ENODEV;
3652 }
3653
release_resources(SLMP_INFO * info)3654 void release_resources(SLMP_INFO *info)
3655 {
3656 if ( debug_level >= DEBUG_LEVEL_INFO )
3657 printk( "%s(%d):%s release_resources() entry\n",
3658 __FILE__,__LINE__,info->device_name );
3659
3660 if ( info->irq_requested ) {
3661 free_irq(info->irq_level, info);
3662 info->irq_requested = 0;
3663 }
3664
3665 if ( info->shared_mem_requested ) {
3666 release_mem_region(info->phys_memory_base,SCA_MEM_SIZE);
3667 info->shared_mem_requested = 0;
3668 }
3669 if ( info->lcr_mem_requested ) {
3670 release_mem_region(info->phys_lcr_base + info->lcr_offset,128);
3671 info->lcr_mem_requested = 0;
3672 }
3673 if ( info->sca_base_requested ) {
3674 release_mem_region(info->phys_sca_base + info->sca_offset,SCA_BASE_SIZE);
3675 info->sca_base_requested = 0;
3676 }
3677 if ( info->sca_statctrl_requested ) {
3678 release_mem_region(info->phys_statctrl_base + info->statctrl_offset,SCA_REG_SIZE);
3679 info->sca_statctrl_requested = 0;
3680 }
3681
3682 if (info->memory_base){
3683 iounmap(info->memory_base);
3684 info->memory_base = 0;
3685 }
3686
3687 if (info->sca_base) {
3688 iounmap(info->sca_base - info->sca_offset);
3689 info->sca_base=0;
3690 }
3691
3692 if (info->statctrl_base) {
3693 iounmap(info->statctrl_base - info->statctrl_offset);
3694 info->statctrl_base=0;
3695 }
3696
3697 if (info->lcr_base){
3698 iounmap(info->lcr_base - info->lcr_offset);
3699 info->lcr_base = 0;
3700 }
3701
3702 if ( debug_level >= DEBUG_LEVEL_INFO )
3703 printk( "%s(%d):%s release_resources() exit\n",
3704 __FILE__,__LINE__,info->device_name );
3705 }
3706
3707 /* Add the specified device instance data structure to the
3708 * global linked list of devices and increment the device count.
3709 */
add_device(SLMP_INFO * info)3710 void add_device(SLMP_INFO *info)
3711 {
3712 info->next_device = NULL;
3713 info->line = synclinkmp_device_count;
3714 sprintf(info->device_name,"ttySLM%dp%d",info->adapter_num,info->port_num);
3715
3716 if (info->line < MAX_DEVICES) {
3717 if (maxframe[info->line])
3718 info->max_frame_size = maxframe[info->line];
3719 info->dosyncppp = dosyncppp[info->line];
3720 }
3721
3722 synclinkmp_device_count++;
3723
3724 if ( !synclinkmp_device_list )
3725 synclinkmp_device_list = info;
3726 else {
3727 SLMP_INFO *current_dev = synclinkmp_device_list;
3728 while( current_dev->next_device )
3729 current_dev = current_dev->next_device;
3730 current_dev->next_device = info;
3731 }
3732
3733 if ( info->max_frame_size < 4096 )
3734 info->max_frame_size = 4096;
3735 else if ( info->max_frame_size > 65535 )
3736 info->max_frame_size = 65535;
3737
3738 printk( "SyncLink MultiPort %s: "
3739 "Mem=(%08x %08X %08x %08X) IRQ=%d MaxFrameSize=%u\n",
3740 info->device_name,
3741 info->phys_sca_base,
3742 info->phys_memory_base,
3743 info->phys_statctrl_base,
3744 info->phys_lcr_base,
3745 info->irq_level,
3746 info->max_frame_size );
3747
3748 #ifdef CONFIG_SYNCLINK_SYNCPPP
3749 if (info->dosyncppp)
3750 sppp_init(info);
3751 #endif
3752 }
3753
3754 /* Allocate and initialize a device instance structure
3755 *
3756 * Return Value: pointer to SLMP_INFO if success, otherwise NULL
3757 */
alloc_dev(int adapter_num,int port_num,struct pci_dev * pdev)3758 SLMP_INFO *alloc_dev(int adapter_num, int port_num, struct pci_dev *pdev)
3759 {
3760 SLMP_INFO *info;
3761
3762 info = (SLMP_INFO *)kmalloc(sizeof(SLMP_INFO),
3763 GFP_KERNEL);
3764
3765 if (!info) {
3766 printk("%s(%d) Error can't allocate device instance data for adapter %d, port %d\n",
3767 __FILE__,__LINE__, adapter_num, port_num);
3768 } else {
3769 memset(info, 0, sizeof(SLMP_INFO));
3770 info->magic = MGSL_MAGIC;
3771 info->task.sync = 0;
3772 info->task.routine = bh_handler;
3773 info->task.data = info;
3774 info->max_frame_size = 4096;
3775 info->close_delay = 5*HZ/10;
3776 info->closing_wait = 30*HZ;
3777 init_waitqueue_head(&info->open_wait);
3778 init_waitqueue_head(&info->close_wait);
3779 init_waitqueue_head(&info->status_event_wait_q);
3780 init_waitqueue_head(&info->event_wait_q);
3781 spin_lock_init(&info->netlock);
3782 memcpy(&info->params,&default_params,sizeof(MGSL_PARAMS));
3783 info->idle_mode = HDLC_TXIDLE_FLAGS;
3784 info->adapter_num = adapter_num;
3785 info->port_num = port_num;
3786
3787 /* Copy configuration info to device instance data */
3788 info->irq_level = pdev->irq;
3789 info->phys_lcr_base = pci_resource_start(pdev,0);
3790 info->phys_sca_base = pci_resource_start(pdev,2);
3791 info->phys_memory_base = pci_resource_start(pdev,3);
3792 info->phys_statctrl_base = pci_resource_start(pdev,4);
3793
3794 /* Because veremap only works on page boundaries we must map
3795 * a larger area than is actually implemented for the LCR
3796 * memory range. We map a full page starting at the page boundary.
3797 */
3798 info->lcr_offset = info->phys_lcr_base & (PAGE_SIZE-1);
3799 info->phys_lcr_base &= ~(PAGE_SIZE-1);
3800
3801 info->sca_offset = info->phys_sca_base & (PAGE_SIZE-1);
3802 info->phys_sca_base &= ~(PAGE_SIZE-1);
3803
3804 info->statctrl_offset = info->phys_statctrl_base & (PAGE_SIZE-1);
3805 info->phys_statctrl_base &= ~(PAGE_SIZE-1);
3806
3807 info->bus_type = MGSL_BUS_TYPE_PCI;
3808 info->irq_flags = SA_SHIRQ;
3809
3810 /* Store the PCI9050 misc control register value because a flaw
3811 * in the PCI9050 prevents LCR registers from being read if
3812 * BIOS assigns an LCR base address with bit 7 set.
3813 *
3814 * Only the misc control register is accessed for which only
3815 * write access is needed, so set an initial value and change
3816 * bits to the device instance data as we write the value
3817 * to the actual misc control register.
3818 */
3819 info->misc_ctrl_value = 0x087e4546;
3820
3821 /* initial port state is unknown - if startup errors
3822 * occur, init_error will be set to indicate the
3823 * problem. Once the port is fully initialized,
3824 * this value will be set to 0 to indicate the
3825 * port is available.
3826 */
3827 info->init_error = -1;
3828 }
3829
3830 return info;
3831 }
3832
device_init(int adapter_num,struct pci_dev * pdev)3833 void device_init(int adapter_num, struct pci_dev *pdev)
3834 {
3835 SLMP_INFO *port_array[SCA_MAX_PORTS];
3836 int port;
3837
3838 /* allocate device instances for up to SCA_MAX_PORTS devices */
3839 for ( port = 0; port < SCA_MAX_PORTS; ++port ) {
3840 port_array[port] = alloc_dev(adapter_num,port,pdev);
3841 if( port_array[port] == NULL ) {
3842 for ( --port; port >= 0; --port )
3843 kfree(port_array[port]);
3844 return;
3845 }
3846 }
3847
3848 /* give copy of port_array to all ports and add to device list */
3849 for ( port = 0; port < SCA_MAX_PORTS; ++port ) {
3850 memcpy(port_array[port]->port_array,port_array,sizeof(port_array));
3851 add_device( port_array[port] );
3852 spin_lock_init(&port_array[port]->lock);
3853 }
3854
3855 /* Allocate and claim adapter resources */
3856 if ( !claim_resources(port_array[0]) ) {
3857
3858 alloc_dma_bufs(port_array[0]);
3859
3860 /* copy resource information from first port to others */
3861 for ( port = 1; port < SCA_MAX_PORTS; ++port ) {
3862 port_array[port]->lock = port_array[0]->lock;
3863 port_array[port]->irq_level = port_array[0]->irq_level;
3864 port_array[port]->memory_base = port_array[0]->memory_base;
3865 port_array[port]->sca_base = port_array[0]->sca_base;
3866 port_array[port]->statctrl_base = port_array[0]->statctrl_base;
3867 port_array[port]->lcr_base = port_array[0]->lcr_base;
3868 alloc_dma_bufs(port_array[port]);
3869 }
3870
3871 if ( request_irq(port_array[0]->irq_level,
3872 synclinkmp_interrupt,
3873 port_array[0]->irq_flags,
3874 port_array[0]->device_name,
3875 port_array[0]) < 0 ) {
3876 printk( "%s(%d):%s Cant request interrupt, IRQ=%d\n",
3877 __FILE__,__LINE__,
3878 port_array[0]->device_name,
3879 port_array[0]->irq_level );
3880 }
3881 else {
3882 port_array[0]->irq_requested = 1;
3883 adapter_test(port_array[0]);
3884 }
3885 }
3886 }
3887
3888 /* Driver initialization entry point.
3889 */
3890
synclinkmp_init(void)3891 static int __init synclinkmp_init(void)
3892 {
3893 SLMP_INFO *info;
3894
3895 EXPORT_NO_SYMBOLS;
3896
3897 if (break_on_load) {
3898 synclinkmp_get_text_ptr();
3899 BREAKPOINT();
3900 }
3901
3902 printk("%s %s\n", driver_name, driver_version);
3903
3904 synclinkmp_adapter_count = -1;
3905 pci_register_driver(&synclinkmp_pci_driver);
3906
3907 if ( !synclinkmp_device_list ) {
3908 printk("%s(%d):No SyncLink devices found.\n",__FILE__,__LINE__);
3909 return -ENODEV;
3910 }
3911
3912 memset(serial_table,0,sizeof(struct tty_struct*)*MAX_DEVICES);
3913 memset(serial_termios,0,sizeof(struct termios*)*MAX_DEVICES);
3914 memset(serial_termios_locked,0,sizeof(struct termios*)*MAX_DEVICES);
3915
3916 /* Initialize the tty_driver structure */
3917
3918 memset(&serial_driver, 0, sizeof(struct tty_driver));
3919 serial_driver.magic = TTY_DRIVER_MAGIC;
3920 serial_driver.driver_name = "synclinkmp";
3921 serial_driver.name = "ttySLM";
3922 serial_driver.major = ttymajor;
3923 serial_driver.minor_start = 64;
3924 serial_driver.num = synclinkmp_device_count;
3925 serial_driver.type = TTY_DRIVER_TYPE_SERIAL;
3926 serial_driver.subtype = SERIAL_TYPE_NORMAL;
3927 serial_driver.init_termios = tty_std_termios;
3928 serial_driver.init_termios.c_cflag =
3929 B9600 | CS8 | CREAD | HUPCL | CLOCAL;
3930 serial_driver.flags = TTY_DRIVER_REAL_RAW;
3931 serial_driver.refcount = &serial_refcount;
3932 serial_driver.table = serial_table;
3933 serial_driver.termios = serial_termios;
3934 serial_driver.termios_locked = serial_termios_locked;
3935
3936 serial_driver.open = open;
3937 serial_driver.close = close;
3938 serial_driver.write = write;
3939 serial_driver.put_char = put_char;
3940 serial_driver.flush_chars = flush_chars;
3941 serial_driver.write_room = write_room;
3942 serial_driver.chars_in_buffer = chars_in_buffer;
3943 serial_driver.flush_buffer = flush_buffer;
3944 serial_driver.ioctl = ioctl;
3945 serial_driver.throttle = throttle;
3946 serial_driver.unthrottle = unthrottle;
3947 serial_driver.send_xchar = send_xchar;
3948 serial_driver.break_ctl = set_break;
3949 serial_driver.wait_until_sent = wait_until_sent;
3950 serial_driver.read_proc = read_proc;
3951 serial_driver.set_termios = set_termios;
3952 serial_driver.stop = tx_hold;
3953 serial_driver.start = tx_release;
3954 serial_driver.hangup = hangup;
3955
3956 /*
3957 * The callout device is just like normal device except for
3958 * major number and the subtype code.
3959 */
3960 callout_driver = serial_driver;
3961 callout_driver.name = "cuaSLM";
3962 callout_driver.major = cuamajor;
3963 callout_driver.subtype = SERIAL_TYPE_CALLOUT;
3964 callout_driver.read_proc = 0;
3965 callout_driver.proc_entry = 0;
3966
3967 if (tty_register_driver(&serial_driver) < 0)
3968 printk("%s(%d):Couldn't register serial driver\n",
3969 __FILE__,__LINE__);
3970
3971 if (tty_register_driver(&callout_driver) < 0)
3972 printk("%s(%d):Couldn't register callout driver\n",
3973 __FILE__,__LINE__);
3974
3975 printk("%s %s, tty major#%d callout major#%d\n",
3976 driver_name, driver_version,
3977 serial_driver.major, callout_driver.major);
3978
3979 /* Propagate these values to all device instances */
3980
3981 info = synclinkmp_device_list;
3982 while(info){
3983 info->callout_termios = callout_driver.init_termios;
3984 info->normal_termios = serial_driver.init_termios;
3985 info = info->next_device;
3986 }
3987
3988 return 0;
3989 }
3990
synclinkmp_exit(void)3991 static void __exit synclinkmp_exit(void)
3992 {
3993 unsigned long flags;
3994 int rc;
3995 SLMP_INFO *info;
3996 SLMP_INFO *tmp;
3997
3998 printk("Unloading %s %s\n", driver_name, driver_version);
3999 save_flags(flags);
4000 cli();
4001 if ((rc = tty_unregister_driver(&serial_driver)))
4002 printk("%s(%d) failed to unregister tty driver err=%d\n",
4003 __FILE__,__LINE__,rc);
4004 if ((rc = tty_unregister_driver(&callout_driver)))
4005 printk("%s(%d) failed to unregister callout driver err=%d\n",
4006 __FILE__,__LINE__,rc);
4007 restore_flags(flags);
4008
4009 /* reset devices */
4010 info = synclinkmp_device_list;
4011 while(info) {
4012 reset_port(info);
4013 info = info->next_device;
4014 }
4015
4016 /* release devices */
4017 info = synclinkmp_device_list;
4018 while(info) {
4019 #ifdef CONFIG_SYNCLINK_SYNCPPP
4020 if (info->dosyncppp)
4021 sppp_delete(info);
4022 #endif
4023 free_dma_bufs(info);
4024 free_tmp_rx_buf(info);
4025 if ( info->port_num == 0 ) {
4026 if (info->sca_base)
4027 write_reg(info, LPR, 1); /* set low power mode */
4028 release_resources(info);
4029 }
4030 tmp = info;
4031 info = info->next_device;
4032 kfree(tmp);
4033 }
4034
4035 pci_unregister_driver(&synclinkmp_pci_driver);
4036 }
4037
4038 module_init(synclinkmp_init);
4039 module_exit(synclinkmp_exit);
4040
4041 /* Set the port for internal loopback mode.
4042 * The TxCLK and RxCLK signals are generated from the BRG and
4043 * the TxD is looped back to the RxD internally.
4044 */
enable_loopback(SLMP_INFO * info,int enable)4045 void enable_loopback(SLMP_INFO *info, int enable)
4046 {
4047 if (enable) {
4048 /* MD2 (Mode Register 2)
4049 * 01..00 CNCT<1..0> Channel Connection 11=Local Loopback
4050 */
4051 write_reg(info, MD2, (unsigned char)(read_reg(info, MD2) | (BIT1 + BIT0)));
4052
4053 /* degate external TxC clock source */
4054 info->port_array[0]->ctrlreg_value |= (BIT0 << (info->port_num * 2));
4055 write_control_reg(info);
4056
4057 /* RXS/TXS (Rx/Tx clock source)
4058 * 07 Reserved, must be 0
4059 * 06..04 Clock Source, 100=BRG
4060 * 03..00 Clock Divisor, 0000=1
4061 */
4062 write_reg(info, RXS, 0x40);
4063 write_reg(info, TXS, 0x40);
4064
4065 } else {
4066 /* MD2 (Mode Register 2)
4067 * 01..00 CNCT<1..0> Channel connection, 0=normal
4068 */
4069 write_reg(info, MD2, (unsigned char)(read_reg(info, MD2) & ~(BIT1 + BIT0)));
4070
4071 /* RXS/TXS (Rx/Tx clock source)
4072 * 07 Reserved, must be 0
4073 * 06..04 Clock Source, 000=RxC/TxC Pin
4074 * 03..00 Clock Divisor, 0000=1
4075 */
4076 write_reg(info, RXS, 0x00);
4077 write_reg(info, TXS, 0x00);
4078 }
4079
4080 /* set LinkSpeed if available, otherwise default to 2Mbps */
4081 if (info->params.clock_speed)
4082 set_rate(info, info->params.clock_speed);
4083 else
4084 set_rate(info, 3686400);
4085 }
4086
4087 /* Set the baud rate register to the desired speed
4088 *
4089 * data_rate data rate of clock in bits per second
4090 * A data rate of 0 disables the AUX clock.
4091 */
set_rate(SLMP_INFO * info,u32 data_rate)4092 void set_rate( SLMP_INFO *info, u32 data_rate )
4093 {
4094 u32 TMCValue;
4095 unsigned char BRValue;
4096 u32 Divisor=0;
4097
4098 /* fBRG = fCLK/(TMC * 2^BR)
4099 */
4100 if (data_rate != 0) {
4101 Divisor = 14745600/data_rate;
4102 if (!Divisor)
4103 Divisor = 1;
4104
4105 TMCValue = Divisor;
4106
4107 BRValue = 0;
4108 if (TMCValue != 1 && TMCValue != 2) {
4109 /* BRValue of 0 provides 50/50 duty cycle *only* when
4110 * TMCValue is 1 or 2. BRValue of 1 to 9 always provides
4111 * 50/50 duty cycle.
4112 */
4113 BRValue = 1;
4114 TMCValue >>= 1;
4115 }
4116
4117 /* while TMCValue is too big for TMC register, divide
4118 * by 2 and increment BR exponent.
4119 */
4120 for(; TMCValue > 256 && BRValue < 10; BRValue++)
4121 TMCValue >>= 1;
4122
4123 write_reg(info, TXS,
4124 (unsigned char)((read_reg(info, TXS) & 0xf0) | BRValue));
4125 write_reg(info, RXS,
4126 (unsigned char)((read_reg(info, RXS) & 0xf0) | BRValue));
4127 write_reg(info, TMC, (unsigned char)TMCValue);
4128 }
4129 else {
4130 write_reg(info, TXS,0);
4131 write_reg(info, RXS,0);
4132 write_reg(info, TMC, 0);
4133 }
4134 }
4135
4136 /* Disable receiver
4137 */
rx_stop(SLMP_INFO * info)4138 void rx_stop(SLMP_INFO *info)
4139 {
4140 if (debug_level >= DEBUG_LEVEL_ISR)
4141 printk("%s(%d):%s rx_stop()\n",
4142 __FILE__,__LINE__, info->device_name );
4143
4144 write_reg(info, CMD, RXRESET);
4145
4146 info->ie0_value &= ~RXRDYE;
4147 write_reg(info, IE0, info->ie0_value); /* disable Rx data interrupts */
4148
4149 write_reg(info, RXDMA + DSR, 0); /* disable Rx DMA */
4150 write_reg(info, RXDMA + DCMD, SWABORT); /* reset/init Rx DMA */
4151 write_reg(info, RXDMA + DIR, 0); /* disable Rx DMA interrupts */
4152
4153 info->rx_enabled = 0;
4154 info->rx_overflow = 0;
4155 }
4156
4157 /* enable the receiver
4158 */
rx_start(SLMP_INFO * info)4159 void rx_start(SLMP_INFO *info)
4160 {
4161 int i;
4162
4163 if (debug_level >= DEBUG_LEVEL_ISR)
4164 printk("%s(%d):%s rx_start()\n",
4165 __FILE__,__LINE__, info->device_name );
4166
4167 write_reg(info, CMD, RXRESET);
4168
4169 if ( info->params.mode == MGSL_MODE_HDLC ) {
4170 /* HDLC, disabe IRQ on rxdata */
4171 info->ie0_value &= ~RXRDYE;
4172 write_reg(info, IE0, info->ie0_value);
4173
4174 /* Reset all Rx DMA buffers and program rx dma */
4175 write_reg(info, RXDMA + DSR, 0); /* disable Rx DMA */
4176 write_reg(info, RXDMA + DCMD, SWABORT); /* reset/init Rx DMA */
4177
4178 for (i = 0; i < info->rx_buf_count; i++) {
4179 info->rx_buf_list[i].status = 0xff;
4180
4181 // throttle to 4 shared memory writes at a time to prevent
4182 // hogging local bus (keep latency time for DMA requests low).
4183 if (!(i % 4))
4184 read_status_reg(info);
4185 }
4186 info->current_rx_buf = 0;
4187
4188 /* set current/1st descriptor address */
4189 write_reg16(info, RXDMA + CDA,
4190 info->rx_buf_list_ex[0].phys_entry);
4191
4192 /* set new last rx descriptor address */
4193 write_reg16(info, RXDMA + EDA,
4194 info->rx_buf_list_ex[info->rx_buf_count - 1].phys_entry);
4195
4196 /* set buffer length (shared by all rx dma data buffers) */
4197 write_reg16(info, RXDMA + BFL, SCABUFSIZE);
4198
4199 write_reg(info, RXDMA + DIR, 0x60); /* enable Rx DMA interrupts (EOM/BOF) */
4200 write_reg(info, RXDMA + DSR, 0xf2); /* clear Rx DMA IRQs, enable Rx DMA */
4201 } else {
4202 /* async, enable IRQ on rxdata */
4203 info->ie0_value |= RXRDYE;
4204 write_reg(info, IE0, info->ie0_value);
4205 }
4206
4207 write_reg(info, CMD, RXENABLE);
4208
4209 info->rx_overflow = FALSE;
4210 info->rx_enabled = 1;
4211 }
4212
4213 /* Enable the transmitter and send a transmit frame if
4214 * one is loaded in the DMA buffers.
4215 */
tx_start(SLMP_INFO * info)4216 void tx_start(SLMP_INFO *info)
4217 {
4218 if (debug_level >= DEBUG_LEVEL_ISR)
4219 printk("%s(%d):%s tx_start() tx_count=%d\n",
4220 __FILE__,__LINE__, info->device_name,info->tx_count );
4221
4222 if (!info->tx_enabled ) {
4223 write_reg(info, CMD, TXRESET);
4224 write_reg(info, CMD, TXENABLE);
4225 info->tx_enabled = TRUE;
4226 }
4227
4228 if ( info->tx_count ) {
4229
4230 /* If auto RTS enabled and RTS is inactive, then assert */
4231 /* RTS and set a flag indicating that the driver should */
4232 /* negate RTS when the transmission completes. */
4233
4234 info->drop_rts_on_tx_done = 0;
4235
4236 if (info->params.mode != MGSL_MODE_ASYNC) {
4237
4238 if ( info->params.flags & HDLC_FLAG_AUTO_RTS ) {
4239 get_signals( info );
4240 if ( !(info->serial_signals & SerialSignal_RTS) ) {
4241 info->serial_signals |= SerialSignal_RTS;
4242 set_signals( info );
4243 info->drop_rts_on_tx_done = 1;
4244 }
4245 }
4246
4247 write_reg16(info, TRC0,
4248 (unsigned short)(((tx_negate_fifo_level-1)<<8) + tx_active_fifo_level));
4249
4250 write_reg(info, TXDMA + DSR, 0); /* disable DMA channel */
4251 write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
4252
4253 /* set TX CDA (current descriptor address) */
4254 write_reg16(info, TXDMA + CDA,
4255 info->tx_buf_list_ex[0].phys_entry);
4256
4257 /* set TX EDA (last descriptor address) */
4258 write_reg16(info, TXDMA + EDA,
4259 info->tx_buf_list_ex[info->last_tx_buf].phys_entry);
4260
4261 /* enable underrun IRQ */
4262 info->ie1_value &= ~IDLE;
4263 info->ie1_value |= UDRN;
4264 write_reg(info, IE1, info->ie1_value);
4265 write_reg(info, SR1, (unsigned char)(IDLE + UDRN));
4266
4267 write_reg(info, TXDMA + DIR, 0x40); /* enable Tx DMA interrupts (EOM) */
4268 write_reg(info, TXDMA + DSR, 0xf2); /* clear Tx DMA IRQs, enable Tx DMA */
4269
4270 info->tx_timer.expires = jiffies + jiffies_from_ms(5000);
4271 add_timer(&info->tx_timer);
4272 }
4273 else {
4274 tx_load_fifo(info);
4275 /* async, enable IRQ on txdata */
4276 info->ie0_value |= TXRDYE;
4277 write_reg(info, IE0, info->ie0_value);
4278 }
4279
4280 info->tx_active = 1;
4281 }
4282 }
4283
4284 /* stop the transmitter and DMA
4285 */
tx_stop(SLMP_INFO * info)4286 void tx_stop( SLMP_INFO *info )
4287 {
4288 if (debug_level >= DEBUG_LEVEL_ISR)
4289 printk("%s(%d):%s tx_stop()\n",
4290 __FILE__,__LINE__, info->device_name );
4291
4292 del_timer(&info->tx_timer);
4293
4294 write_reg(info, TXDMA + DSR, 0); /* disable DMA channel */
4295 write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
4296
4297 write_reg(info, CMD, TXRESET);
4298
4299 info->ie1_value &= ~(UDRN + IDLE);
4300 write_reg(info, IE1, info->ie1_value); /* disable tx status interrupts */
4301 write_reg(info, SR1, (unsigned char)(IDLE + UDRN)); /* clear pending */
4302
4303 info->ie0_value &= ~TXRDYE;
4304 write_reg(info, IE0, info->ie0_value); /* disable tx data interrupts */
4305
4306 info->tx_enabled = 0;
4307 info->tx_active = 0;
4308 }
4309
4310 /* Fill the transmit FIFO until the FIFO is full or
4311 * there is no more data to load.
4312 */
tx_load_fifo(SLMP_INFO * info)4313 void tx_load_fifo(SLMP_INFO *info)
4314 {
4315 u8 TwoBytes[2];
4316
4317 /* do nothing is now tx data available and no XON/XOFF pending */
4318
4319 if ( !info->tx_count && !info->x_char )
4320 return;
4321
4322 /* load the Transmit FIFO until FIFOs full or all data sent */
4323
4324 while( info->tx_count && (read_reg(info,SR0) & BIT1) ) {
4325
4326 /* there is more space in the transmit FIFO and */
4327 /* there is more data in transmit buffer */
4328
4329 if ( (info->tx_count > 1) && !info->x_char ) {
4330 /* write 16-bits */
4331 TwoBytes[0] = info->tx_buf[info->tx_get++];
4332 if (info->tx_get >= info->max_frame_size)
4333 info->tx_get -= info->max_frame_size;
4334 TwoBytes[1] = info->tx_buf[info->tx_get++];
4335 if (info->tx_get >= info->max_frame_size)
4336 info->tx_get -= info->max_frame_size;
4337
4338 write_reg16(info, TRB, *((u16 *)TwoBytes));
4339
4340 info->tx_count -= 2;
4341 info->icount.tx += 2;
4342 } else {
4343 /* only 1 byte left to transmit or 1 FIFO slot left */
4344
4345 if (info->x_char) {
4346 /* transmit pending high priority char */
4347 write_reg(info, TRB, info->x_char);
4348 info->x_char = 0;
4349 } else {
4350 write_reg(info, TRB, info->tx_buf[info->tx_get++]);
4351 if (info->tx_get >= info->max_frame_size)
4352 info->tx_get -= info->max_frame_size;
4353 info->tx_count--;
4354 }
4355 info->icount.tx++;
4356 }
4357 }
4358 }
4359
4360 /* Reset a port to a known state
4361 */
reset_port(SLMP_INFO * info)4362 void reset_port(SLMP_INFO *info)
4363 {
4364 if (info->sca_base) {
4365
4366 tx_stop(info);
4367 rx_stop(info);
4368
4369 info->serial_signals &= ~(SerialSignal_DTR + SerialSignal_RTS);
4370 set_signals(info);
4371
4372 /* disable all port interrupts */
4373 info->ie0_value = 0;
4374 info->ie1_value = 0;
4375 info->ie2_value = 0;
4376 write_reg(info, IE0, info->ie0_value);
4377 write_reg(info, IE1, info->ie1_value);
4378 write_reg(info, IE2, info->ie2_value);
4379
4380 write_reg(info, CMD, CHRESET);
4381 }
4382 }
4383
4384 /* Reset all the ports to a known state.
4385 */
reset_adapter(SLMP_INFO * info)4386 void reset_adapter(SLMP_INFO *info)
4387 {
4388 int i;
4389
4390 for ( i=0; i < SCA_MAX_PORTS; ++i) {
4391 if (info->port_array[i])
4392 reset_port(info->port_array[i]);
4393 }
4394 }
4395
4396 /* Program port for asynchronous communications.
4397 */
async_mode(SLMP_INFO * info)4398 void async_mode(SLMP_INFO *info)
4399 {
4400
4401 unsigned char RegValue;
4402
4403 tx_stop(info);
4404 rx_stop(info);
4405
4406 /* MD0, Mode Register 0
4407 *
4408 * 07..05 PRCTL<2..0>, Protocol Mode, 000=async
4409 * 04 AUTO, Auto-enable (RTS/CTS/DCD)
4410 * 03 Reserved, must be 0
4411 * 02 CRCCC, CRC Calculation, 0=disabled
4412 * 01..00 STOP<1..0> Stop bits (00=1,10=2)
4413 *
4414 * 0000 0000
4415 */
4416 RegValue = 0x00;
4417 if (info->params.stop_bits != 1)
4418 RegValue |= BIT1;
4419 write_reg(info, MD0, RegValue);
4420
4421 /* MD1, Mode Register 1
4422 *
4423 * 07..06 BRATE<1..0>, bit rate, 00=1/1 01=1/16 10=1/32 11=1/64
4424 * 05..04 TXCHR<1..0>, tx char size, 00=8 bits,01=7,10=6,11=5
4425 * 03..02 RXCHR<1..0>, rx char size
4426 * 01..00 PMPM<1..0>, Parity mode, 00=none 10=even 11=odd
4427 *
4428 * 0100 0000
4429 */
4430 RegValue = 0x40;
4431 switch (info->params.data_bits) {
4432 case 7: RegValue |= BIT4 + BIT2; break;
4433 case 6: RegValue |= BIT5 + BIT3; break;
4434 case 5: RegValue |= BIT5 + BIT4 + BIT3 + BIT2; break;
4435 }
4436 if (info->params.parity != ASYNC_PARITY_NONE) {
4437 RegValue |= BIT1;
4438 if (info->params.parity == ASYNC_PARITY_ODD)
4439 RegValue |= BIT0;
4440 }
4441 write_reg(info, MD1, RegValue);
4442
4443 /* MD2, Mode Register 2
4444 *
4445 * 07..02 Reserved, must be 0
4446 * 01..00 CNCT<1..0> Channel connection, 0=normal
4447 *
4448 * 0000 0000
4449 */
4450 RegValue = 0x00;
4451 write_reg(info, MD2, RegValue);
4452
4453 /* RXS, Receive clock source
4454 *
4455 * 07 Reserved, must be 0
4456 * 06..04 RXCS<2..0>, clock source, 000=RxC Pin, 100=BRG, 110=DPLL
4457 * 03..00 RXBR<3..0>, rate divisor, 0000=1
4458 */
4459 RegValue=BIT6;
4460 write_reg(info, RXS, RegValue);
4461
4462 /* TXS, Transmit clock source
4463 *
4464 * 07 Reserved, must be 0
4465 * 06..04 RXCS<2..0>, clock source, 000=TxC Pin, 100=BRG, 110=Receive Clock
4466 * 03..00 RXBR<3..0>, rate divisor, 0000=1
4467 */
4468 RegValue=BIT6;
4469 write_reg(info, TXS, RegValue);
4470
4471 /* Control Register
4472 *
4473 * 6,4,2,0 CLKSEL<3..0>, 0 = TcCLK in, 1 = Auxclk out
4474 */
4475 info->port_array[0]->ctrlreg_value |= (BIT0 << (info->port_num * 2));
4476 write_control_reg(info);
4477
4478 tx_set_idle(info);
4479
4480 /* RRC Receive Ready Control 0
4481 *
4482 * 07..05 Reserved, must be 0
4483 * 04..00 RRC<4..0> Rx FIFO trigger active 0x00 = 1 byte
4484 */
4485 write_reg(info, RRC, 0x00);
4486
4487 /* TRC0 Transmit Ready Control 0
4488 *
4489 * 07..05 Reserved, must be 0
4490 * 04..00 TRC<4..0> Tx FIFO trigger active 0x10 = 16 bytes
4491 */
4492 write_reg(info, TRC0, 0x10);
4493
4494 /* TRC1 Transmit Ready Control 1
4495 *
4496 * 07..05 Reserved, must be 0
4497 * 04..00 TRC<4..0> Tx FIFO trigger inactive 0x1e = 31 bytes (full-1)
4498 */
4499 write_reg(info, TRC1, 0x1e);
4500
4501 /* CTL, MSCI control register
4502 *
4503 * 07..06 Reserved, set to 0
4504 * 05 UDRNC, underrun control, 0=abort 1=CRC+flag (HDLC/BSC)
4505 * 04 IDLC, idle control, 0=mark 1=idle register
4506 * 03 BRK, break, 0=off 1 =on (async)
4507 * 02 SYNCLD, sync char load enable (BSC) 1=enabled
4508 * 01 GOP, go active on poll (LOOP mode) 1=enabled
4509 * 00 RTS, RTS output control, 0=active 1=inactive
4510 *
4511 * 0001 0001
4512 */
4513 RegValue = 0x10;
4514 if (!(info->serial_signals & SerialSignal_RTS))
4515 RegValue |= 0x01;
4516 write_reg(info, CTL, RegValue);
4517
4518 /* enable status interrupts */
4519 info->ie0_value |= TXINTE + RXINTE;
4520 write_reg(info, IE0, info->ie0_value);
4521
4522 /* enable break detect interrupt */
4523 info->ie1_value = BRKD;
4524 write_reg(info, IE1, info->ie1_value);
4525
4526 /* enable rx overrun interrupt */
4527 info->ie2_value = OVRN;
4528 write_reg(info, IE2, info->ie2_value);
4529
4530 set_rate( info, info->params.data_rate * 16 );
4531
4532 if (info->params.loopback)
4533 enable_loopback(info,1);
4534 }
4535
4536 /* Program the SCA for HDLC communications.
4537 */
hdlc_mode(SLMP_INFO * info)4538 void hdlc_mode(SLMP_INFO *info)
4539 {
4540 unsigned char RegValue;
4541 u32 DpllDivisor;
4542
4543 // Can't use DPLL because SCA outputs recovered clock on RxC when
4544 // DPLL mode selected. This causes output contention with RxC receiver.
4545 // Use of DPLL would require external hardware to disable RxC receiver
4546 // when DPLL mode selected.
4547 info->params.flags &= ~(HDLC_FLAG_TXC_DPLL + HDLC_FLAG_RXC_DPLL);
4548
4549 /* disable DMA interrupts */
4550 write_reg(info, TXDMA + DIR, 0);
4551 write_reg(info, RXDMA + DIR, 0);
4552
4553 /* MD0, Mode Register 0
4554 *
4555 * 07..05 PRCTL<2..0>, Protocol Mode, 100=HDLC
4556 * 04 AUTO, Auto-enable (RTS/CTS/DCD)
4557 * 03 Reserved, must be 0
4558 * 02 CRCCC, CRC Calculation, 1=enabled
4559 * 01 CRC1, CRC selection, 0=CRC-16,1=CRC-CCITT-16
4560 * 00 CRC0, CRC initial value, 1 = all 1s
4561 *
4562 * 1000 0001
4563 */
4564 RegValue = 0x81;
4565 if (info->params.flags & HDLC_FLAG_AUTO_CTS)
4566 RegValue |= BIT4;
4567 if (info->params.flags & HDLC_FLAG_AUTO_DCD)
4568 RegValue |= BIT4;
4569 if (info->params.crc_type == HDLC_CRC_16_CCITT)
4570 RegValue |= BIT2 + BIT1;
4571 write_reg(info, MD0, RegValue);
4572
4573 /* MD1, Mode Register 1
4574 *
4575 * 07..06 ADDRS<1..0>, Address detect, 00=no addr check
4576 * 05..04 TXCHR<1..0>, tx char size, 00=8 bits
4577 * 03..02 RXCHR<1..0>, rx char size, 00=8 bits
4578 * 01..00 PMPM<1..0>, Parity mode, 00=no parity
4579 *
4580 * 0000 0000
4581 */
4582 RegValue = 0x00;
4583 write_reg(info, MD1, RegValue);
4584
4585 /* MD2, Mode Register 2
4586 *
4587 * 07 NRZFM, 0=NRZ, 1=FM
4588 * 06..05 CODE<1..0> Encoding, 00=NRZ
4589 * 04..03 DRATE<1..0> DPLL Divisor, 00=8
4590 * 02 Reserved, must be 0
4591 * 01..00 CNCT<1..0> Channel connection, 0=normal
4592 *
4593 * 0000 0000
4594 */
4595 RegValue = 0x00;
4596 switch(info->params.encoding) {
4597 case HDLC_ENCODING_NRZI: RegValue |= BIT5; break;
4598 case HDLC_ENCODING_BIPHASE_MARK: RegValue |= BIT7 + BIT5; break; /* aka FM1 */
4599 case HDLC_ENCODING_BIPHASE_SPACE: RegValue |= BIT7 + BIT6; break; /* aka FM0 */
4600 case HDLC_ENCODING_BIPHASE_LEVEL: RegValue |= BIT7; break; /* aka Manchester */
4601 #if 0
4602 case HDLC_ENCODING_NRZB: /* not supported */
4603 case HDLC_ENCODING_NRZI_MARK: /* not supported */
4604 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: /* not supported */
4605 #endif
4606 }
4607 if ( info->params.flags & HDLC_FLAG_DPLL_DIV16 ) {
4608 DpllDivisor = 16;
4609 RegValue |= BIT3;
4610 } else if ( info->params.flags & HDLC_FLAG_DPLL_DIV8 ) {
4611 DpllDivisor = 8;
4612 } else {
4613 DpllDivisor = 32;
4614 RegValue |= BIT4;
4615 }
4616 write_reg(info, MD2, RegValue);
4617
4618
4619 /* RXS, Receive clock source
4620 *
4621 * 07 Reserved, must be 0
4622 * 06..04 RXCS<2..0>, clock source, 000=RxC Pin, 100=BRG, 110=DPLL
4623 * 03..00 RXBR<3..0>, rate divisor, 0000=1
4624 */
4625 RegValue=0;
4626 if (info->params.flags & HDLC_FLAG_RXC_BRG)
4627 RegValue |= BIT6;
4628 if (info->params.flags & HDLC_FLAG_RXC_DPLL)
4629 RegValue |= BIT6 + BIT5;
4630 write_reg(info, RXS, RegValue);
4631
4632 /* TXS, Transmit clock source
4633 *
4634 * 07 Reserved, must be 0
4635 * 06..04 RXCS<2..0>, clock source, 000=TxC Pin, 100=BRG, 110=Receive Clock
4636 * 03..00 RXBR<3..0>, rate divisor, 0000=1
4637 */
4638 RegValue=0;
4639 if (info->params.flags & HDLC_FLAG_TXC_BRG)
4640 RegValue |= BIT6;
4641 if (info->params.flags & HDLC_FLAG_TXC_DPLL)
4642 RegValue |= BIT6 + BIT5;
4643 write_reg(info, TXS, RegValue);
4644
4645 if (info->params.flags & HDLC_FLAG_RXC_DPLL)
4646 set_rate(info, info->params.clock_speed * DpllDivisor);
4647 else
4648 set_rate(info, info->params.clock_speed);
4649
4650 /* GPDATA (General Purpose I/O Data Register)
4651 *
4652 * 6,4,2,0 CLKSEL<3..0>, 0 = TcCLK in, 1 = Auxclk out
4653 */
4654 if (info->params.flags & HDLC_FLAG_TXC_BRG)
4655 info->port_array[0]->ctrlreg_value |= (BIT0 << (info->port_num * 2));
4656 else
4657 info->port_array[0]->ctrlreg_value &= ~(BIT0 << (info->port_num * 2));
4658 write_control_reg(info);
4659
4660 /* RRC Receive Ready Control 0
4661 *
4662 * 07..05 Reserved, must be 0
4663 * 04..00 RRC<4..0> Rx FIFO trigger active
4664 */
4665 write_reg(info, RRC, rx_active_fifo_level);
4666
4667 /* TRC0 Transmit Ready Control 0
4668 *
4669 * 07..05 Reserved, must be 0
4670 * 04..00 TRC<4..0> Tx FIFO trigger active
4671 */
4672 write_reg(info, TRC0, tx_active_fifo_level);
4673
4674 /* TRC1 Transmit Ready Control 1
4675 *
4676 * 07..05 Reserved, must be 0
4677 * 04..00 TRC<4..0> Tx FIFO trigger inactive 0x1f = 32 bytes (full)
4678 */
4679 write_reg(info, TRC1, (unsigned char)(tx_negate_fifo_level - 1));
4680
4681 /* DMR, DMA Mode Register
4682 *
4683 * 07..05 Reserved, must be 0
4684 * 04 TMOD, Transfer Mode: 1=chained-block
4685 * 03 Reserved, must be 0
4686 * 02 NF, Number of Frames: 1=multi-frame
4687 * 01 CNTE, Frame End IRQ Counter enable: 0=disabled
4688 * 00 Reserved, must be 0
4689 *
4690 * 0001 0100
4691 */
4692 write_reg(info, TXDMA + DMR, 0x14);
4693 write_reg(info, RXDMA + DMR, 0x14);
4694
4695 /* Set chain pointer base (upper 8 bits of 24 bit addr) */
4696 write_reg(info, RXDMA + CPB,
4697 (unsigned char)(info->buffer_list_phys >> 16));
4698
4699 /* Set chain pointer base (upper 8 bits of 24 bit addr) */
4700 write_reg(info, TXDMA + CPB,
4701 (unsigned char)(info->buffer_list_phys >> 16));
4702
4703 /* enable status interrupts. other code enables/disables
4704 * the individual sources for these two interrupt classes.
4705 */
4706 info->ie0_value |= TXINTE + RXINTE;
4707 write_reg(info, IE0, info->ie0_value);
4708
4709 /* CTL, MSCI control register
4710 *
4711 * 07..06 Reserved, set to 0
4712 * 05 UDRNC, underrun control, 0=abort 1=CRC+flag (HDLC/BSC)
4713 * 04 IDLC, idle control, 0=mark 1=idle register
4714 * 03 BRK, break, 0=off 1 =on (async)
4715 * 02 SYNCLD, sync char load enable (BSC) 1=enabled
4716 * 01 GOP, go active on poll (LOOP mode) 1=enabled
4717 * 00 RTS, RTS output control, 0=active 1=inactive
4718 *
4719 * 0001 0001
4720 */
4721 RegValue = 0x10;
4722 if (!(info->serial_signals & SerialSignal_RTS))
4723 RegValue |= 0x01;
4724 write_reg(info, CTL, RegValue);
4725
4726 /* preamble not supported ! */
4727
4728 tx_set_idle(info);
4729 tx_stop(info);
4730 rx_stop(info);
4731
4732 set_rate(info, info->params.clock_speed);
4733
4734 if (info->params.loopback)
4735 enable_loopback(info,1);
4736 }
4737
4738 /* Set the transmit HDLC idle mode
4739 */
tx_set_idle(SLMP_INFO * info)4740 void tx_set_idle(SLMP_INFO *info)
4741 {
4742 unsigned char RegValue = 0xff;
4743
4744 /* Map API idle mode to SCA register bits */
4745 switch(info->idle_mode) {
4746 case HDLC_TXIDLE_FLAGS: RegValue = 0x7e; break;
4747 case HDLC_TXIDLE_ALT_ZEROS_ONES: RegValue = 0xaa; break;
4748 case HDLC_TXIDLE_ZEROS: RegValue = 0x00; break;
4749 case HDLC_TXIDLE_ONES: RegValue = 0xff; break;
4750 case HDLC_TXIDLE_ALT_MARK_SPACE: RegValue = 0xaa; break;
4751 case HDLC_TXIDLE_SPACE: RegValue = 0x00; break;
4752 case HDLC_TXIDLE_MARK: RegValue = 0xff; break;
4753 }
4754
4755 write_reg(info, IDL, RegValue);
4756 }
4757
4758 /* Query the adapter for the state of the V24 status (input) signals.
4759 */
get_signals(SLMP_INFO * info)4760 void get_signals(SLMP_INFO *info)
4761 {
4762 u16 status = read_reg(info, SR3);
4763 u16 gpstatus = read_status_reg(info);
4764 u16 testbit;
4765
4766 /* clear all serial signals except DTR and RTS */
4767 info->serial_signals &= SerialSignal_DTR + SerialSignal_RTS;
4768
4769 /* set serial signal bits to reflect MISR */
4770
4771 if (!(status & BIT3))
4772 info->serial_signals |= SerialSignal_CTS;
4773
4774 if ( !(status & BIT2))
4775 info->serial_signals |= SerialSignal_DCD;
4776
4777 testbit = BIT1 << (info->port_num * 2); // Port 0..3 RI is GPDATA<1,3,5,7>
4778 if (!(gpstatus & testbit))
4779 info->serial_signals |= SerialSignal_RI;
4780
4781 testbit = BIT0 << (info->port_num * 2); // Port 0..3 DSR is GPDATA<0,2,4,6>
4782 if (!(gpstatus & testbit))
4783 info->serial_signals |= SerialSignal_DSR;
4784 }
4785
4786 /* Set the state of DTR and RTS based on contents of
4787 * serial_signals member of device context.
4788 */
set_signals(SLMP_INFO * info)4789 void set_signals(SLMP_INFO *info)
4790 {
4791 unsigned char RegValue;
4792 u16 EnableBit;
4793
4794 RegValue = read_reg(info, CTL);
4795 if (info->serial_signals & SerialSignal_RTS)
4796 RegValue &= ~BIT0;
4797 else
4798 RegValue |= BIT0;
4799 write_reg(info, CTL, RegValue);
4800
4801 // Port 0..3 DTR is ctrl reg <1,3,5,7>
4802 EnableBit = BIT1 << (info->port_num*2);
4803 if (info->serial_signals & SerialSignal_DTR)
4804 info->port_array[0]->ctrlreg_value &= ~EnableBit;
4805 else
4806 info->port_array[0]->ctrlreg_value |= EnableBit;
4807 write_control_reg(info);
4808 }
4809
4810 /*******************/
4811 /* DMA Buffer Code */
4812 /*******************/
4813
4814 /* Set the count for all receive buffers to SCABUFSIZE
4815 * and set the current buffer to the first buffer. This effectively
4816 * makes all buffers free and discards any data in buffers.
4817 */
rx_reset_buffers(SLMP_INFO * info)4818 void rx_reset_buffers(SLMP_INFO *info)
4819 {
4820 rx_free_frame_buffers(info, 0, info->rx_buf_count - 1);
4821 }
4822
4823 /* Free the buffers used by a received frame
4824 *
4825 * info pointer to device instance data
4826 * first index of 1st receive buffer of frame
4827 * last index of last receive buffer of frame
4828 */
rx_free_frame_buffers(SLMP_INFO * info,unsigned int first,unsigned int last)4829 void rx_free_frame_buffers(SLMP_INFO *info, unsigned int first, unsigned int last)
4830 {
4831 int done = 0;
4832
4833 while(!done) {
4834 /* reset current buffer for reuse */
4835 info->rx_buf_list[first].status = 0xff;
4836
4837 if (first == last) {
4838 done = 1;
4839 /* set new last rx descriptor address */
4840 write_reg16(info, RXDMA + EDA, info->rx_buf_list_ex[first].phys_entry);
4841 }
4842
4843 first++;
4844 if (first == info->rx_buf_count)
4845 first = 0;
4846 }
4847
4848 /* set current buffer to next buffer after last buffer of frame */
4849 info->current_rx_buf = first;
4850 }
4851
4852 /* Return a received frame from the receive DMA buffers.
4853 * Only frames received without errors are returned.
4854 *
4855 * Return Value: 1 if frame returned, otherwise 0
4856 */
rx_get_frame(SLMP_INFO * info)4857 int rx_get_frame(SLMP_INFO *info)
4858 {
4859 unsigned int StartIndex, EndIndex; /* index of 1st and last buffers of Rx frame */
4860 unsigned short status;
4861 unsigned int framesize = 0;
4862 int ReturnCode = 0;
4863 unsigned long flags;
4864 struct tty_struct *tty = info->tty;
4865 unsigned char addr_field = 0xff;
4866 SCADESC *desc;
4867 SCADESC_EX *desc_ex;
4868
4869 CheckAgain:
4870 /* assume no frame returned, set zero length */
4871 framesize = 0;
4872 addr_field = 0xff;
4873
4874 /*
4875 * current_rx_buf points to the 1st buffer of the next available
4876 * receive frame. To find the last buffer of the frame look for
4877 * a non-zero status field in the buffer entries. (The status
4878 * field is set by the 16C32 after completing a receive frame.
4879 */
4880 StartIndex = EndIndex = info->current_rx_buf;
4881
4882 for ( ;; ) {
4883 desc = &info->rx_buf_list[EndIndex];
4884 desc_ex = &info->rx_buf_list_ex[EndIndex];
4885
4886 if (desc->status == 0xff)
4887 goto Cleanup; /* current desc still in use, no frames available */
4888
4889 if (framesize == 0 && info->params.addr_filter != 0xff)
4890 addr_field = desc_ex->virt_addr[0];
4891
4892 framesize += desc->length;
4893
4894 /* Status != 0 means last buffer of frame */
4895 if (desc->status)
4896 break;
4897
4898 EndIndex++;
4899 if (EndIndex == info->rx_buf_count)
4900 EndIndex = 0;
4901
4902 if (EndIndex == info->current_rx_buf) {
4903 /* all buffers have been 'used' but none mark */
4904 /* the end of a frame. Reset buffers and receiver. */
4905 if ( info->rx_enabled ){
4906 spin_lock_irqsave(&info->lock,flags);
4907 rx_start(info);
4908 spin_unlock_irqrestore(&info->lock,flags);
4909 }
4910 goto Cleanup;
4911 }
4912
4913 }
4914
4915 /* check status of receive frame */
4916
4917 /* frame status is byte stored after frame data
4918 *
4919 * 7 EOM (end of msg), 1 = last buffer of frame
4920 * 6 Short Frame, 1 = short frame
4921 * 5 Abort, 1 = frame aborted
4922 * 4 Residue, 1 = last byte is partial
4923 * 3 Overrun, 1 = overrun occurred during frame reception
4924 * 2 CRC, 1 = CRC error detected
4925 *
4926 */
4927 status = desc->status;
4928
4929 /* ignore CRC bit if not using CRC (bit is undefined) */
4930 /* Note:CRC is not save to data buffer */
4931 if (info->params.crc_type == HDLC_CRC_NONE)
4932 status &= ~BIT2;
4933
4934 if (framesize == 0 ||
4935 (addr_field != 0xff && addr_field != info->params.addr_filter)) {
4936 /* discard 0 byte frames, this seems to occur sometime
4937 * when remote is idling flags.
4938 */
4939 rx_free_frame_buffers(info, StartIndex, EndIndex);
4940 goto CheckAgain;
4941 }
4942
4943 if (framesize < 2)
4944 status |= BIT6;
4945
4946 if (status & (BIT6+BIT5+BIT3+BIT2)) {
4947 /* received frame has errors,
4948 * update counts and mark frame size as 0
4949 */
4950 if (status & BIT6)
4951 info->icount.rxshort++;
4952 else if (status & BIT5)
4953 info->icount.rxabort++;
4954 else if (status & BIT3)
4955 info->icount.rxover++;
4956 else
4957 info->icount.rxcrc++;
4958
4959 framesize = 0;
4960
4961 #ifdef CONFIG_SYNCLINK_SYNCPPP
4962 info->netstats.rx_errors++;
4963 info->netstats.rx_frame_errors++;
4964 #endif
4965 }
4966
4967 if ( debug_level >= DEBUG_LEVEL_BH )
4968 printk("%s(%d):%s rx_get_frame() status=%04X size=%d\n",
4969 __FILE__,__LINE__,info->device_name,status,framesize);
4970
4971 if ( debug_level >= DEBUG_LEVEL_DATA )
4972 trace_block(info,info->rx_buf_list_ex[StartIndex].virt_addr,
4973 MIN(framesize,SCABUFSIZE),0);
4974
4975 if (framesize) {
4976 if (framesize > info->max_frame_size)
4977 info->icount.rxlong++;
4978 else {
4979 /* copy dma buffer(s) to contiguous intermediate buffer */
4980 int copy_count = framesize;
4981 int index = StartIndex;
4982 unsigned char *ptmp = info->tmp_rx_buf;
4983 info->tmp_rx_buf_count = framesize;
4984
4985 info->icount.rxok++;
4986
4987 while(copy_count) {
4988 int partial_count = MIN(copy_count,SCABUFSIZE);
4989 memcpy( ptmp,
4990 info->rx_buf_list_ex[index].virt_addr,
4991 partial_count );
4992 ptmp += partial_count;
4993 copy_count -= partial_count;
4994
4995 if ( ++index == info->rx_buf_count )
4996 index = 0;
4997 }
4998
4999 #ifdef CONFIG_SYNCLINK_SYNCPPP
5000 if (info->netcount) {
5001 /* pass frame to syncppp device */
5002 sppp_rx_done(info,info->tmp_rx_buf,framesize);
5003 }
5004 else
5005 #endif
5006 ldisc_receive_buf(tty,info->tmp_rx_buf,
5007 info->flag_buf, framesize);
5008 }
5009 }
5010 /* Free the buffers used by this frame. */
5011 rx_free_frame_buffers( info, StartIndex, EndIndex );
5012
5013 ReturnCode = 1;
5014
5015 Cleanup:
5016 if ( info->rx_enabled && info->rx_overflow ) {
5017 /* Receiver is enabled, but needs to restarted due to
5018 * rx buffer overflow. If buffers are empty, restart receiver.
5019 */
5020 if (info->rx_buf_list[EndIndex].status == 0xff) {
5021 spin_lock_irqsave(&info->lock,flags);
5022 rx_start(info);
5023 spin_unlock_irqrestore(&info->lock,flags);
5024 }
5025 }
5026
5027 return ReturnCode;
5028 }
5029
5030 /* load the transmit DMA buffer with data
5031 */
tx_load_dma_buffer(SLMP_INFO * info,const char * buf,unsigned int count)5032 void tx_load_dma_buffer(SLMP_INFO *info, const char *buf, unsigned int count)
5033 {
5034 unsigned short copy_count;
5035 unsigned int i = 0;
5036 SCADESC *desc;
5037 SCADESC_EX *desc_ex;
5038
5039 if ( debug_level >= DEBUG_LEVEL_DATA )
5040 trace_block(info,buf, MIN(count,SCABUFSIZE), 1);
5041
5042 /* Copy source buffer to one or more DMA buffers, starting with
5043 * the first transmit dma buffer.
5044 */
5045 for(i=0;;)
5046 {
5047 copy_count = MIN(count,SCABUFSIZE);
5048
5049 desc = &info->tx_buf_list[i];
5050 desc_ex = &info->tx_buf_list_ex[i];
5051
5052 load_pci_memory(info, desc_ex->virt_addr,buf,copy_count);
5053
5054 desc->length = copy_count;
5055 desc->status = 0;
5056
5057 buf += copy_count;
5058 count -= copy_count;
5059
5060 if (!count)
5061 break;
5062
5063 i++;
5064 if (i >= info->tx_buf_count)
5065 i = 0;
5066 }
5067
5068 info->tx_buf_list[i].status = 0x81; /* set EOM and EOT status */
5069 info->last_tx_buf = ++i;
5070 }
5071
register_test(SLMP_INFO * info)5072 int register_test(SLMP_INFO *info)
5073 {
5074 static unsigned char testval[] = {0x00, 0xff, 0xaa, 0x55, 0x69, 0x96};
5075 static unsigned int count = sizeof(testval)/sizeof(unsigned char);
5076 unsigned int i;
5077 int rc = TRUE;
5078 unsigned long flags;
5079
5080 spin_lock_irqsave(&info->lock,flags);
5081 reset_port(info);
5082
5083 /* assume failure */
5084 info->init_error = DiagStatus_AddressFailure;
5085
5086 /* Write bit patterns to various registers but do it out of */
5087 /* sync, then read back and verify values. */
5088
5089 for (i = 0 ; i < count ; i++) {
5090 write_reg(info, TMC, testval[i]);
5091 write_reg(info, IDL, testval[(i+1)%count]);
5092 write_reg(info, SA0, testval[(i+2)%count]);
5093 write_reg(info, SA1, testval[(i+3)%count]);
5094
5095 if ( (read_reg(info, TMC) != testval[i]) ||
5096 (read_reg(info, IDL) != testval[(i+1)%count]) ||
5097 (read_reg(info, SA0) != testval[(i+2)%count]) ||
5098 (read_reg(info, SA1) != testval[(i+3)%count]) )
5099 {
5100 rc = FALSE;
5101 break;
5102 }
5103 }
5104
5105 reset_port(info);
5106 spin_unlock_irqrestore(&info->lock,flags);
5107
5108 return rc;
5109 }
5110
irq_test(SLMP_INFO * info)5111 int irq_test(SLMP_INFO *info)
5112 {
5113 unsigned long timeout;
5114 unsigned long flags;
5115
5116 unsigned char timer = (info->port_num & 1) ? TIMER2 : TIMER0;
5117
5118 spin_lock_irqsave(&info->lock,flags);
5119 reset_port(info);
5120
5121 /* assume failure */
5122 info->init_error = DiagStatus_IrqFailure;
5123 info->irq_occurred = FALSE;
5124
5125 /* setup timer0 on SCA0 to interrupt */
5126
5127 /* IER2<7..4> = timer<3..0> interrupt enables (1=enabled) */
5128 write_reg(info, IER2, (unsigned char)((info->port_num & 1) ? BIT6 : BIT4));
5129
5130 write_reg(info, (unsigned char)(timer + TEPR), 0); /* timer expand prescale */
5131 write_reg16(info, (unsigned char)(timer + TCONR), 1); /* timer constant */
5132
5133
5134 /* TMCS, Timer Control/Status Register
5135 *
5136 * 07 CMF, Compare match flag (read only) 1=match
5137 * 06 ECMI, CMF Interrupt Enable: 1=enabled
5138 * 05 Reserved, must be 0
5139 * 04 TME, Timer Enable
5140 * 03..00 Reserved, must be 0
5141 *
5142 * 0101 0000
5143 */
5144 write_reg(info, (unsigned char)(timer + TMCS), 0x50);
5145
5146 spin_unlock_irqrestore(&info->lock,flags);
5147
5148 timeout=100;
5149 while( timeout-- && !info->irq_occurred ) {
5150 set_current_state(TASK_INTERRUPTIBLE);
5151 schedule_timeout(jiffies_from_ms(10));
5152 }
5153
5154 spin_lock_irqsave(&info->lock,flags);
5155 reset_port(info);
5156 spin_unlock_irqrestore(&info->lock,flags);
5157
5158 return info->irq_occurred;
5159 }
5160
5161 /* initialize individual SCA device (2 ports)
5162 */
sca_init(SLMP_INFO * info)5163 int sca_init(SLMP_INFO *info)
5164 {
5165 /* set wait controller to single mem partition (low), no wait states */
5166 write_reg(info, PABR0, 0); /* wait controller addr boundary 0 */
5167 write_reg(info, PABR1, 0); /* wait controller addr boundary 1 */
5168 write_reg(info, WCRL, 0); /* wait controller low range */
5169 write_reg(info, WCRM, 0); /* wait controller mid range */
5170 write_reg(info, WCRH, 0); /* wait controller high range */
5171
5172 /* DPCR, DMA Priority Control
5173 *
5174 * 07..05 Not used, must be 0
5175 * 04 BRC, bus release condition: 0=all transfers complete
5176 * 03 CCC, channel change condition: 0=every cycle
5177 * 02..00 PR<2..0>, priority 100=round robin
5178 *
5179 * 00000100 = 0x04
5180 */
5181 write_reg(info, DPCR, dma_priority);
5182
5183 /* DMA Master Enable, BIT7: 1=enable all channels */
5184 write_reg(info, DMER, 0x80);
5185
5186 /* enable all interrupt classes */
5187 write_reg(info, IER0, 0xff); /* TxRDY,RxRDY,TxINT,RxINT (ports 0-1) */
5188 write_reg(info, IER1, 0xff); /* DMIB,DMIA (channels 0-3) */
5189 write_reg(info, IER2, 0xf0); /* TIRQ (timers 0-3) */
5190
5191 /* ITCR, interrupt control register
5192 * 07 IPC, interrupt priority, 0=MSCI->DMA
5193 * 06..05 IAK<1..0>, Acknowledge cycle, 00=non-ack cycle
5194 * 04 VOS, Vector Output, 0=unmodified vector
5195 * 03..00 Reserved, must be 0
5196 */
5197 write_reg(info, ITCR, 0);
5198
5199 return TRUE;
5200 }
5201
5202 /* initialize adapter hardware
5203 */
init_adapter(SLMP_INFO * info)5204 int init_adapter(SLMP_INFO *info)
5205 {
5206 int i;
5207
5208 /* Set BIT30 of Local Control Reg 0x50 to reset SCA */
5209 volatile u32 *MiscCtrl = (u32 *)(info->lcr_base + 0x50);
5210 u32 readval;
5211
5212 info->misc_ctrl_value |= BIT30;
5213 *MiscCtrl = info->misc_ctrl_value;
5214
5215 /*
5216 * Force at least 170ns delay before clearing
5217 * reset bit. Each read from LCR takes at least
5218 * 30ns so 10 times for 300ns to be safe.
5219 */
5220 for(i=0;i<10;i++)
5221 readval = *MiscCtrl;
5222
5223 info->misc_ctrl_value &= ~BIT30;
5224 *MiscCtrl = info->misc_ctrl_value;
5225
5226 /* init control reg (all DTRs off, all clksel=input) */
5227 info->ctrlreg_value = 0xaa;
5228 write_control_reg(info);
5229
5230 {
5231 volatile u32 *LCR1BRDR = (u32 *)(info->lcr_base + 0x2c);
5232 lcr1_brdr_value &= ~(BIT5 + BIT4 + BIT3);
5233
5234 switch(read_ahead_count)
5235 {
5236 case 16:
5237 lcr1_brdr_value |= BIT5 + BIT4 + BIT3;
5238 break;
5239 case 8:
5240 lcr1_brdr_value |= BIT5 + BIT4;
5241 break;
5242 case 4:
5243 lcr1_brdr_value |= BIT5 + BIT3;
5244 break;
5245 case 0:
5246 lcr1_brdr_value |= BIT5;
5247 break;
5248 }
5249
5250 *LCR1BRDR = lcr1_brdr_value;
5251 *MiscCtrl = misc_ctrl_value;
5252 }
5253
5254 sca_init(info->port_array[0]);
5255 sca_init(info->port_array[2]);
5256
5257 return TRUE;
5258 }
5259
5260 /* Loopback an HDLC frame to test the hardware
5261 * interrupt and DMA functions.
5262 */
loopback_test(SLMP_INFO * info)5263 int loopback_test(SLMP_INFO *info)
5264 {
5265 #define TESTFRAMESIZE 20
5266
5267 unsigned long timeout;
5268 u16 count = TESTFRAMESIZE;
5269 unsigned char buf[TESTFRAMESIZE];
5270 int rc = FALSE;
5271 unsigned long flags;
5272
5273 struct tty_struct *oldtty = info->tty;
5274 u32 speed = info->params.clock_speed;
5275
5276 info->params.clock_speed = 3686400;
5277 info->tty = 0;
5278
5279 /* assume failure */
5280 info->init_error = DiagStatus_DmaFailure;
5281
5282 /* build and send transmit frame */
5283 for (count = 0; count < TESTFRAMESIZE;++count)
5284 buf[count] = (unsigned char)count;
5285
5286 memset(info->tmp_rx_buf,0,TESTFRAMESIZE);
5287
5288 /* program hardware for HDLC and enabled receiver */
5289 spin_lock_irqsave(&info->lock,flags);
5290 hdlc_mode(info);
5291 enable_loopback(info,1);
5292 rx_start(info);
5293 info->tx_count = count;
5294 tx_load_dma_buffer(info,buf,count);
5295 tx_start(info);
5296 spin_unlock_irqrestore(&info->lock,flags);
5297
5298 /* wait for receive complete */
5299 /* Set a timeout for waiting for interrupt. */
5300 for ( timeout = 100; timeout; --timeout ) {
5301 set_current_state(TASK_INTERRUPTIBLE);
5302 schedule_timeout(jiffies_from_ms(10));
5303
5304 if (rx_get_frame(info)) {
5305 rc = TRUE;
5306 break;
5307 }
5308 }
5309
5310 /* verify received frame length and contents */
5311 if (rc == TRUE &&
5312 ( info->tmp_rx_buf_count != count ||
5313 memcmp(buf, info->tmp_rx_buf,count))) {
5314 rc = FALSE;
5315 }
5316
5317 spin_lock_irqsave(&info->lock,flags);
5318 reset_adapter(info);
5319 spin_unlock_irqrestore(&info->lock,flags);
5320
5321 info->params.clock_speed = speed;
5322 info->tty = oldtty;
5323
5324 return rc;
5325 }
5326
5327 /* Perform diagnostics on hardware
5328 */
adapter_test(SLMP_INFO * info)5329 int adapter_test( SLMP_INFO *info )
5330 {
5331 unsigned long flags;
5332 if ( debug_level >= DEBUG_LEVEL_INFO )
5333 printk( "%s(%d):Testing device %s\n",
5334 __FILE__,__LINE__,info->device_name );
5335
5336 spin_lock_irqsave(&info->lock,flags);
5337 init_adapter(info);
5338 spin_unlock_irqrestore(&info->lock,flags);
5339
5340 info->port_array[0]->port_count = 0;
5341
5342 if ( register_test(info->port_array[0]) &&
5343 register_test(info->port_array[1])) {
5344
5345 info->port_array[0]->port_count = 2;
5346
5347 if ( register_test(info->port_array[2]) &&
5348 register_test(info->port_array[3]) )
5349 info->port_array[0]->port_count += 2;
5350 }
5351 else {
5352 printk( "%s(%d):Register test failure for device %s Addr=%08lX\n",
5353 __FILE__,__LINE__,info->device_name, (unsigned long)(info->phys_sca_base));
5354 return -ENODEV;
5355 }
5356
5357 if ( !irq_test(info->port_array[0]) ||
5358 !irq_test(info->port_array[1]) ||
5359 (info->port_count == 4 && !irq_test(info->port_array[2])) ||
5360 (info->port_count == 4 && !irq_test(info->port_array[3]))) {
5361 printk( "%s(%d):Interrupt test failure for device %s IRQ=%d\n",
5362 __FILE__,__LINE__,info->device_name, (unsigned short)(info->irq_level) );
5363 return -ENODEV;
5364 }
5365
5366 if (!loopback_test(info->port_array[0]) ||
5367 !loopback_test(info->port_array[1]) ||
5368 (info->port_count == 4 && !loopback_test(info->port_array[2])) ||
5369 (info->port_count == 4 && !loopback_test(info->port_array[3]))) {
5370 printk( "%s(%d):DMA test failure for device %s\n",
5371 __FILE__,__LINE__,info->device_name);
5372 return -ENODEV;
5373 }
5374
5375 if ( debug_level >= DEBUG_LEVEL_INFO )
5376 printk( "%s(%d):device %s passed diagnostics\n",
5377 __FILE__,__LINE__,info->device_name );
5378
5379 info->port_array[0]->init_error = 0;
5380 info->port_array[1]->init_error = 0;
5381 if ( info->port_count > 2 ) {
5382 info->port_array[2]->init_error = 0;
5383 info->port_array[3]->init_error = 0;
5384 }
5385
5386 return 0;
5387 }
5388
5389 /* Test the shared memory on a PCI adapter.
5390 */
memory_test(SLMP_INFO * info)5391 int memory_test(SLMP_INFO *info)
5392 {
5393 static unsigned long testval[] = { 0x0, 0x55555555, 0xaaaaaaaa,
5394 0x66666666, 0x99999999, 0xffffffff, 0x12345678 };
5395 unsigned long count = sizeof(testval)/sizeof(unsigned long);
5396 unsigned long i;
5397 unsigned long limit = SCA_MEM_SIZE/sizeof(unsigned long);
5398 unsigned long * addr = (unsigned long *)info->memory_base;
5399
5400 /* Test data lines with test pattern at one location. */
5401
5402 for ( i = 0 ; i < count ; i++ ) {
5403 *addr = testval[i];
5404 if ( *addr != testval[i] )
5405 return FALSE;
5406 }
5407
5408 /* Test address lines with incrementing pattern over */
5409 /* entire address range. */
5410
5411 for ( i = 0 ; i < limit ; i++ ) {
5412 *addr = i * 4;
5413 addr++;
5414 }
5415
5416 addr = (unsigned long *)info->memory_base;
5417
5418 for ( i = 0 ; i < limit ; i++ ) {
5419 if ( *addr != i * 4 )
5420 return FALSE;
5421 addr++;
5422 }
5423
5424 memset( info->memory_base, 0, SCA_MEM_SIZE );
5425 return TRUE;
5426 }
5427
5428 /* Load data into PCI adapter shared memory.
5429 *
5430 * The PCI9050 releases control of the local bus
5431 * after completing the current read or write operation.
5432 *
5433 * While the PCI9050 write FIFO not empty, the
5434 * PCI9050 treats all of the writes as a single transaction
5435 * and does not release the bus. This causes DMA latency problems
5436 * at high speeds when copying large data blocks to the shared memory.
5437 *
5438 * This function breaks a write into multiple transations by
5439 * interleaving a read which flushes the write FIFO and 'completes'
5440 * the write transation. This allows any pending DMA request to gain control
5441 * of the local bus in a timely fasion.
5442 */
load_pci_memory(SLMP_INFO * info,char * dest,const char * src,unsigned short count)5443 void load_pci_memory(SLMP_INFO *info, char* dest, const char* src, unsigned short count)
5444 {
5445 /* A load interval of 16 allows for 4 32-bit writes at */
5446 /* 136ns each for a maximum latency of 542ns on the local bus.*/
5447
5448 unsigned short interval = count / sca_pci_load_interval;
5449 unsigned short i;
5450
5451 for ( i = 0 ; i < interval ; i++ )
5452 {
5453 memcpy(dest, src, sca_pci_load_interval);
5454 read_status_reg(info);
5455 dest += sca_pci_load_interval;
5456 src += sca_pci_load_interval;
5457 }
5458
5459 memcpy(dest, src, count % sca_pci_load_interval);
5460 }
5461
trace_block(SLMP_INFO * info,const char * data,int count,int xmit)5462 void trace_block(SLMP_INFO *info,const char* data, int count, int xmit)
5463 {
5464 int i;
5465 int linecount;
5466 if (xmit)
5467 printk("%s tx data:\n",info->device_name);
5468 else
5469 printk("%s rx data:\n",info->device_name);
5470
5471 while(count) {
5472 if (count > 16)
5473 linecount = 16;
5474 else
5475 linecount = count;
5476
5477 for(i=0;i<linecount;i++)
5478 printk("%02X ",(unsigned char)data[i]);
5479 for(;i<17;i++)
5480 printk(" ");
5481 for(i=0;i<linecount;i++) {
5482 if (data[i]>=040 && data[i]<=0176)
5483 printk("%c",data[i]);
5484 else
5485 printk(".");
5486 }
5487 printk("\n");
5488
5489 data += linecount;
5490 count -= linecount;
5491 }
5492 } /* end of trace_block() */
5493
5494 /* called when HDLC frame times out
5495 * update stats and do tx completion processing
5496 */
tx_timeout(unsigned long context)5497 void tx_timeout(unsigned long context)
5498 {
5499 SLMP_INFO *info = (SLMP_INFO*)context;
5500 unsigned long flags;
5501
5502 if ( debug_level >= DEBUG_LEVEL_INFO )
5503 printk( "%s(%d):%s tx_timeout()\n",
5504 __FILE__,__LINE__,info->device_name);
5505 if(info->tx_active && info->params.mode == MGSL_MODE_HDLC) {
5506 info->icount.txtimeout++;
5507 }
5508 spin_lock_irqsave(&info->lock,flags);
5509 info->tx_active = 0;
5510 info->tx_count = info->tx_put = info->tx_get = 0;
5511
5512 spin_unlock_irqrestore(&info->lock,flags);
5513
5514 #ifdef CONFIG_SYNCLINK_SYNCPPP
5515 if (info->netcount)
5516 sppp_tx_done(info);
5517 else
5518 #endif
5519 bh_transmit(info);
5520 }
5521
5522 /* called to periodically check the DSR/RI modem signal input status
5523 */
status_timeout(unsigned long context)5524 void status_timeout(unsigned long context)
5525 {
5526 u16 status = 0;
5527 SLMP_INFO *info = (SLMP_INFO*)context;
5528 unsigned long flags;
5529 unsigned char delta;
5530
5531
5532 spin_lock_irqsave(&info->lock,flags);
5533 get_signals(info);
5534 spin_unlock_irqrestore(&info->lock,flags);
5535
5536 /* check for DSR/RI state change */
5537
5538 delta = info->old_signals ^ info->serial_signals;
5539 info->old_signals = info->serial_signals;
5540
5541 if (delta & SerialSignal_DSR)
5542 status |= MISCSTATUS_DSR_LATCHED|(info->serial_signals&SerialSignal_DSR);
5543
5544 if (delta & SerialSignal_RI)
5545 status |= MISCSTATUS_RI_LATCHED|(info->serial_signals&SerialSignal_RI);
5546
5547 if (delta & SerialSignal_DCD)
5548 status |= MISCSTATUS_DCD_LATCHED|(info->serial_signals&SerialSignal_DCD);
5549
5550 if (delta & SerialSignal_CTS)
5551 status |= MISCSTATUS_CTS_LATCHED|(info->serial_signals&SerialSignal_CTS);
5552
5553 if (status)
5554 isr_io_pin(info,status);
5555
5556 info->status_timer.data = (unsigned long)info;
5557 info->status_timer.function = status_timeout;
5558 info->status_timer.expires = jiffies + jiffies_from_ms(10);
5559 add_timer(&info->status_timer);
5560 }
5561
5562
5563 /* Register Access Routines -
5564 * All registers are memory mapped
5565 */
5566 #define CALC_REGADDR() \
5567 unsigned char * RegAddr = (unsigned char*)(info->sca_base + Addr); \
5568 if (info->port_num > 1) \
5569 RegAddr += 256; /* port 0-1 SCA0, 2-3 SCA1 */ \
5570 if ( info->port_num & 1) { \
5571 if (Addr > 0x7f) \
5572 RegAddr += 0x40; /* DMA access */ \
5573 else if (Addr > 0x1f && Addr < 0x60) \
5574 RegAddr += 0x20; /* MSCI access */ \
5575 }
5576
5577
read_reg(SLMP_INFO * info,unsigned char Addr)5578 unsigned char read_reg(SLMP_INFO * info, unsigned char Addr)
5579 {
5580 CALC_REGADDR();
5581 return *RegAddr;
5582 }
write_reg(SLMP_INFO * info,unsigned char Addr,unsigned char Value)5583 void write_reg(SLMP_INFO * info, unsigned char Addr, unsigned char Value)
5584 {
5585 CALC_REGADDR();
5586 *RegAddr = Value;
5587 }
5588
read_reg16(SLMP_INFO * info,unsigned char Addr)5589 u16 read_reg16(SLMP_INFO * info, unsigned char Addr)
5590 {
5591 CALC_REGADDR();
5592 return *((u16 *)RegAddr);
5593 }
5594
write_reg16(SLMP_INFO * info,unsigned char Addr,u16 Value)5595 void write_reg16(SLMP_INFO * info, unsigned char Addr, u16 Value)
5596 {
5597 CALC_REGADDR();
5598 *((u16 *)RegAddr) = Value;
5599 }
5600
read_status_reg(SLMP_INFO * info)5601 unsigned char read_status_reg(SLMP_INFO * info)
5602 {
5603 unsigned char *RegAddr = (unsigned char *)info->statctrl_base;
5604 return *RegAddr;
5605 }
5606
write_control_reg(SLMP_INFO * info)5607 void write_control_reg(SLMP_INFO * info)
5608 {
5609 unsigned char *RegAddr = (unsigned char *)info->statctrl_base;
5610 *RegAddr = info->port_array[0]->ctrlreg_value;
5611 }
5612
5613
synclinkmp_init_one(struct pci_dev * dev,const struct pci_device_id * ent)5614 static int __devinit synclinkmp_init_one (struct pci_dev *dev,
5615 const struct pci_device_id *ent)
5616 {
5617 if (pci_enable_device(dev)) {
5618 printk("error enabling pci device %p\n", dev);
5619 return -EIO;
5620 }
5621 device_init( ++synclinkmp_adapter_count, dev );
5622 return 0;
5623 }
5624
synclinkmp_remove_one(struct pci_dev * dev)5625 static void __devexit synclinkmp_remove_one (struct pci_dev *dev)
5626 {
5627 }
5628