1 /* radeon_drm.h -- Public header for the radeon driver -*- linux-c -*- 2 * 3 * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas. 4 * Copyright 2000 VA Linux Systems, Inc., Fremont, California. 5 * Copyright 2002 Tungsten Graphics, Inc., Cedar Park, Texas. 6 * All rights reserved. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a 9 * copy of this software and associated documentation files (the "Software"), 10 * to deal in the Software without restriction, including without limitation 11 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 12 * and/or sell copies of the Software, and to permit persons to whom the 13 * Software is furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice (including the next 16 * paragraph) shall be included in all copies or substantial portions of the 17 * Software. 18 * 19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 22 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 23 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 24 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 25 * DEALINGS IN THE SOFTWARE. 26 * 27 * Authors: 28 * Kevin E. Martin <martin@valinux.com> 29 * Gareth Hughes <gareth@valinux.com> 30 * Keith Whitwell <keith@tungstengraphics.com> 31 */ 32 33 #ifndef __RADEON_DRM_H__ 34 #define __RADEON_DRM_H__ 35 36 /* WARNING: If you change any of these defines, make sure to change the 37 * defines in the X server file (radeon_sarea.h) 38 */ 39 #ifndef __RADEON_SAREA_DEFINES__ 40 #define __RADEON_SAREA_DEFINES__ 41 42 /* Old style state flags, required for sarea interface (1.1 and 1.2 43 * clears) and 1.2 drm_vertex2 ioctl. 44 */ 45 #define RADEON_UPLOAD_CONTEXT 0x00000001 46 #define RADEON_UPLOAD_VERTFMT 0x00000002 47 #define RADEON_UPLOAD_LINE 0x00000004 48 #define RADEON_UPLOAD_BUMPMAP 0x00000008 49 #define RADEON_UPLOAD_MASKS 0x00000010 50 #define RADEON_UPLOAD_VIEWPORT 0x00000020 51 #define RADEON_UPLOAD_SETUP 0x00000040 52 #define RADEON_UPLOAD_TCL 0x00000080 53 #define RADEON_UPLOAD_MISC 0x00000100 54 #define RADEON_UPLOAD_TEX0 0x00000200 55 #define RADEON_UPLOAD_TEX1 0x00000400 56 #define RADEON_UPLOAD_TEX2 0x00000800 57 #define RADEON_UPLOAD_TEX0IMAGES 0x00001000 58 #define RADEON_UPLOAD_TEX1IMAGES 0x00002000 59 #define RADEON_UPLOAD_TEX2IMAGES 0x00004000 60 #define RADEON_UPLOAD_CLIPRECTS 0x00008000 /* handled client-side */ 61 #define RADEON_REQUIRE_QUIESCENCE 0x00010000 62 #define RADEON_UPLOAD_ZBIAS 0x00020000 /* version 1.2 and newer */ 63 #define RADEON_UPLOAD_ALL 0x003effff 64 #define RADEON_UPLOAD_CONTEXT_ALL 0x003e01ff 65 66 67 /* New style per-packet identifiers for use in cmd_buffer ioctl with 68 * the RADEON_EMIT_PACKET command. Comments relate new packets to old 69 * state bits and the packet size: 70 */ 71 #define RADEON_EMIT_PP_MISC 0 /* context/7 */ 72 #define RADEON_EMIT_PP_CNTL 1 /* context/3 */ 73 #define RADEON_EMIT_RB3D_COLORPITCH 2 /* context/1 */ 74 #define RADEON_EMIT_RE_LINE_PATTERN 3 /* line/2 */ 75 #define RADEON_EMIT_SE_LINE_WIDTH 4 /* line/1 */ 76 #define RADEON_EMIT_PP_LUM_MATRIX 5 /* bumpmap/1 */ 77 #define RADEON_EMIT_PP_ROT_MATRIX_0 6 /* bumpmap/2 */ 78 #define RADEON_EMIT_RB3D_STENCILREFMASK 7 /* masks/3 */ 79 #define RADEON_EMIT_SE_VPORT_XSCALE 8 /* viewport/6 */ 80 #define RADEON_EMIT_SE_CNTL 9 /* setup/2 */ 81 #define RADEON_EMIT_SE_CNTL_STATUS 10 /* setup/1 */ 82 #define RADEON_EMIT_RE_MISC 11 /* misc/1 */ 83 #define RADEON_EMIT_PP_TXFILTER_0 12 /* tex0/6 */ 84 #define RADEON_EMIT_PP_BORDER_COLOR_0 13 /* tex0/1 */ 85 #define RADEON_EMIT_PP_TXFILTER_1 14 /* tex1/6 */ 86 #define RADEON_EMIT_PP_BORDER_COLOR_1 15 /* tex1/1 */ 87 #define RADEON_EMIT_PP_TXFILTER_2 16 /* tex2/6 */ 88 #define RADEON_EMIT_PP_BORDER_COLOR_2 17 /* tex2/1 */ 89 #define RADEON_EMIT_SE_ZBIAS_FACTOR 18 /* zbias/2 */ 90 #define RADEON_EMIT_SE_TCL_OUTPUT_VTX_FMT 19 /* tcl/11 */ 91 #define RADEON_EMIT_SE_TCL_MATERIAL_EMMISSIVE_RED 20 /* material/17 */ 92 #define R200_EMIT_PP_TXCBLEND_0 21 /* tex0/4 */ 93 #define R200_EMIT_PP_TXCBLEND_1 22 /* tex1/4 */ 94 #define R200_EMIT_PP_TXCBLEND_2 23 /* tex2/4 */ 95 #define R200_EMIT_PP_TXCBLEND_3 24 /* tex3/4 */ 96 #define R200_EMIT_PP_TXCBLEND_4 25 /* tex4/4 */ 97 #define R200_EMIT_PP_TXCBLEND_5 26 /* tex5/4 */ 98 #define R200_EMIT_PP_TXCBLEND_6 27 /* /4 */ 99 #define R200_EMIT_PP_TXCBLEND_7 28 /* /4 */ 100 #define R200_EMIT_TCL_LIGHT_MODEL_CTL_0 29 /* tcl/7 */ 101 #define R200_EMIT_TFACTOR_0 30 /* tf/7 */ 102 #define R200_EMIT_VTX_FMT_0 31 /* vtx/5 */ 103 #define R200_EMIT_VAP_CTL 32 /* vap/1 */ 104 #define R200_EMIT_MATRIX_SELECT_0 33 /* msl/5 */ 105 #define R200_EMIT_TEX_PROC_CTL_2 34 /* tcg/5 */ 106 #define R200_EMIT_TCL_UCP_VERT_BLEND_CTL 35 /* tcl/1 */ 107 #define R200_EMIT_PP_TXFILTER_0 36 /* tex0/6 */ 108 #define R200_EMIT_PP_TXFILTER_1 37 /* tex1/6 */ 109 #define R200_EMIT_PP_TXFILTER_2 38 /* tex2/6 */ 110 #define R200_EMIT_PP_TXFILTER_3 39 /* tex3/6 */ 111 #define R200_EMIT_PP_TXFILTER_4 40 /* tex4/6 */ 112 #define R200_EMIT_PP_TXFILTER_5 41 /* tex5/6 */ 113 #define R200_EMIT_PP_TXOFFSET_0 42 /* tex0/1 */ 114 #define R200_EMIT_PP_TXOFFSET_1 43 /* tex1/1 */ 115 #define R200_EMIT_PP_TXOFFSET_2 44 /* tex2/1 */ 116 #define R200_EMIT_PP_TXOFFSET_3 45 /* tex3/1 */ 117 #define R200_EMIT_PP_TXOFFSET_4 46 /* tex4/1 */ 118 #define R200_EMIT_PP_TXOFFSET_5 47 /* tex5/1 */ 119 #define R200_EMIT_VTE_CNTL 48 /* vte/1 */ 120 #define R200_EMIT_OUTPUT_VTX_COMP_SEL 49 /* vtx/1 */ 121 #define R200_EMIT_PP_TAM_DEBUG3 50 /* tam/1 */ 122 #define R200_EMIT_PP_CNTL_X 51 /* cst/1 */ 123 #define R200_EMIT_RB3D_DEPTHXY_OFFSET 52 /* cst/1 */ 124 #define R200_EMIT_RE_AUX_SCISSOR_CNTL 53 /* cst/1 */ 125 #define R200_EMIT_RE_SCISSOR_TL_0 54 /* cst/2 */ 126 #define R200_EMIT_RE_SCISSOR_TL_1 55 /* cst/2 */ 127 #define R200_EMIT_RE_SCISSOR_TL_2 56 /* cst/2 */ 128 #define R200_EMIT_SE_VAP_CNTL_STATUS 57 /* cst/1 */ 129 #define R200_EMIT_SE_VTX_STATE_CNTL 58 /* cst/1 */ 130 #define R200_EMIT_RE_POINTSIZE 59 /* cst/1 */ 131 #define R200_EMIT_TCL_INPUT_VTX_VECTOR_ADDR_0 60 /* cst/4 */ 132 #define R200_EMIT_PP_CUBIC_FACES_0 61 133 #define R200_EMIT_PP_CUBIC_OFFSETS_0 62 134 #define R200_EMIT_PP_CUBIC_FACES_1 63 135 #define R200_EMIT_PP_CUBIC_OFFSETS_1 64 136 #define R200_EMIT_PP_CUBIC_FACES_2 65 137 #define R200_EMIT_PP_CUBIC_OFFSETS_2 66 138 #define R200_EMIT_PP_CUBIC_FACES_3 67 139 #define R200_EMIT_PP_CUBIC_OFFSETS_3 68 140 #define R200_EMIT_PP_CUBIC_FACES_4 69 141 #define R200_EMIT_PP_CUBIC_OFFSETS_4 70 142 #define R200_EMIT_PP_CUBIC_FACES_5 71 143 #define R200_EMIT_PP_CUBIC_OFFSETS_5 72 144 #define RADEON_MAX_STATE_PACKETS 73 145 146 147 /* Commands understood by cmd_buffer ioctl. More can be added but 148 * obviously these can't be removed or changed: 149 */ 150 #define RADEON_CMD_PACKET 1 /* emit one of the register packets above */ 151 #define RADEON_CMD_SCALARS 2 /* emit scalar data */ 152 #define RADEON_CMD_VECTORS 3 /* emit vector data */ 153 #define RADEON_CMD_DMA_DISCARD 4 /* discard current dma buf */ 154 #define RADEON_CMD_PACKET3 5 /* emit hw packet */ 155 #define RADEON_CMD_PACKET3_CLIP 6 /* emit hw packet wrapped in cliprects */ 156 #define RADEON_CMD_SCALARS2 7 /* r200 stopgap */ 157 #define RADEON_CMD_WAIT 8 /* emit hw wait commands -- note: 158 * doesn't make the cpu wait, just 159 * the graphics hardware */ 160 161 162 typedef union { 163 int i; 164 struct { 165 unsigned char cmd_type, pad0, pad1, pad2; 166 } header; 167 struct { 168 unsigned char cmd_type, packet_id, pad0, pad1; 169 } packet; 170 struct { 171 unsigned char cmd_type, offset, stride, count; 172 } scalars; 173 struct { 174 unsigned char cmd_type, offset, stride, count; 175 } vectors; 176 struct { 177 unsigned char cmd_type, buf_idx, pad0, pad1; 178 } dma; 179 struct { 180 unsigned char cmd_type, flags, pad0, pad1; 181 } wait; 182 } drm_radeon_cmd_header_t; 183 184 #define RADEON_WAIT_2D 0x1 185 #define RADEON_WAIT_3D 0x2 186 187 188 #define RADEON_FRONT 0x1 189 #define RADEON_BACK 0x2 190 #define RADEON_DEPTH 0x4 191 #define RADEON_STENCIL 0x8 192 193 /* Primitive types 194 */ 195 #define RADEON_POINTS 0x1 196 #define RADEON_LINES 0x2 197 #define RADEON_LINE_STRIP 0x3 198 #define RADEON_TRIANGLES 0x4 199 #define RADEON_TRIANGLE_FAN 0x5 200 #define RADEON_TRIANGLE_STRIP 0x6 201 202 /* Vertex/indirect buffer size 203 */ 204 #define RADEON_BUFFER_SIZE 65536 205 206 /* Byte offsets for indirect buffer data 207 */ 208 #define RADEON_INDEX_PRIM_OFFSET 20 209 210 #define RADEON_SCRATCH_REG_OFFSET 32 211 212 #define RADEON_NR_SAREA_CLIPRECTS 12 213 214 /* There are 2 heaps (local/AGP). Each region within a heap is a 215 * minimum of 64k, and there are at most 64 of them per heap. 216 */ 217 #define RADEON_LOCAL_TEX_HEAP 0 218 #define RADEON_AGP_TEX_HEAP 1 219 #define RADEON_NR_TEX_HEAPS 2 220 #define RADEON_NR_TEX_REGIONS 64 221 #define RADEON_LOG_TEX_GRANULARITY 16 222 223 #define RADEON_MAX_TEXTURE_LEVELS 12 224 #define RADEON_MAX_TEXTURE_UNITS 3 225 226 #endif /* __RADEON_SAREA_DEFINES__ */ 227 228 typedef struct { 229 unsigned int red; 230 unsigned int green; 231 unsigned int blue; 232 unsigned int alpha; 233 } radeon_color_regs_t; 234 235 typedef struct { 236 /* Context state */ 237 unsigned int pp_misc; /* 0x1c14 */ 238 unsigned int pp_fog_color; 239 unsigned int re_solid_color; 240 unsigned int rb3d_blendcntl; 241 unsigned int rb3d_depthoffset; 242 unsigned int rb3d_depthpitch; 243 unsigned int rb3d_zstencilcntl; 244 245 unsigned int pp_cntl; /* 0x1c38 */ 246 unsigned int rb3d_cntl; 247 unsigned int rb3d_coloroffset; 248 unsigned int re_width_height; 249 unsigned int rb3d_colorpitch; 250 unsigned int se_cntl; 251 252 /* Vertex format state */ 253 unsigned int se_coord_fmt; /* 0x1c50 */ 254 255 /* Line state */ 256 unsigned int re_line_pattern; /* 0x1cd0 */ 257 unsigned int re_line_state; 258 259 unsigned int se_line_width; /* 0x1db8 */ 260 261 /* Bumpmap state */ 262 unsigned int pp_lum_matrix; /* 0x1d00 */ 263 264 unsigned int pp_rot_matrix_0; /* 0x1d58 */ 265 unsigned int pp_rot_matrix_1; 266 267 /* Mask state */ 268 unsigned int rb3d_stencilrefmask; /* 0x1d7c */ 269 unsigned int rb3d_ropcntl; 270 unsigned int rb3d_planemask; 271 272 /* Viewport state */ 273 unsigned int se_vport_xscale; /* 0x1d98 */ 274 unsigned int se_vport_xoffset; 275 unsigned int se_vport_yscale; 276 unsigned int se_vport_yoffset; 277 unsigned int se_vport_zscale; 278 unsigned int se_vport_zoffset; 279 280 /* Setup state */ 281 unsigned int se_cntl_status; /* 0x2140 */ 282 283 /* Misc state */ 284 unsigned int re_top_left; /* 0x26c0 */ 285 unsigned int re_misc; 286 } drm_radeon_context_regs_t; 287 288 typedef struct { 289 /* Zbias state */ 290 unsigned int se_zbias_factor; /* 0x1dac */ 291 unsigned int se_zbias_constant; 292 } drm_radeon_context2_regs_t; 293 294 295 /* Setup registers for each texture unit 296 */ 297 typedef struct { 298 unsigned int pp_txfilter; 299 unsigned int pp_txformat; 300 unsigned int pp_txoffset; 301 unsigned int pp_txcblend; 302 unsigned int pp_txablend; 303 unsigned int pp_tfactor; 304 unsigned int pp_border_color; 305 } drm_radeon_texture_regs_t; 306 307 typedef struct { 308 unsigned int start; 309 unsigned int finish; 310 unsigned int prim:8; 311 unsigned int stateidx:8; 312 unsigned int numverts:16; /* overloaded as offset/64 for elt prims */ 313 unsigned int vc_format; /* vertex format */ 314 } drm_radeon_prim_t; 315 316 317 typedef struct { 318 drm_radeon_context_regs_t context; 319 drm_radeon_texture_regs_t tex[RADEON_MAX_TEXTURE_UNITS]; 320 drm_radeon_context2_regs_t context2; 321 unsigned int dirty; 322 } drm_radeon_state_t; 323 324 325 typedef struct { 326 unsigned char next, prev; 327 unsigned char in_use; 328 int age; 329 } drm_radeon_tex_region_t; 330 331 typedef struct { 332 /* The channel for communication of state information to the 333 * kernel on firing a vertex buffer with either of the 334 * obsoleted vertex/index ioctls. 335 */ 336 drm_radeon_context_regs_t context_state; 337 drm_radeon_texture_regs_t tex_state[RADEON_MAX_TEXTURE_UNITS]; 338 unsigned int dirty; 339 unsigned int vertsize; 340 unsigned int vc_format; 341 342 /* The current cliprects, or a subset thereof. 343 */ 344 drm_clip_rect_t boxes[RADEON_NR_SAREA_CLIPRECTS]; 345 unsigned int nbox; 346 347 /* Counters for client-side throttling of rendering clients. 348 */ 349 unsigned int last_frame; 350 unsigned int last_dispatch; 351 unsigned int last_clear; 352 353 drm_radeon_tex_region_t tex_list[RADEON_NR_TEX_HEAPS][RADEON_NR_TEX_REGIONS+1]; 354 int tex_age[RADEON_NR_TEX_HEAPS]; 355 int ctx_owner; 356 int pfState; /* number of 3d windows (0,1,2ormore) */ 357 int pfCurrentPage; /* which buffer is being displayed? */ 358 int crtc2_base; /* CRTC2 frame offset */ 359 } drm_radeon_sarea_t; 360 361 362 /* WARNING: If you change any of these defines, make sure to change the 363 * defines in the Xserver file (xf86drmRadeon.h) 364 * 365 * KW: actually it's illegal to change any of this (backwards compatibility). 366 */ 367 368 /* Radeon specific ioctls 369 * The device specific ioctl range is 0x40 to 0x79. 370 */ 371 #define DRM_IOCTL_RADEON_CP_INIT DRM_IOW( 0x40, drm_radeon_init_t) 372 #define DRM_IOCTL_RADEON_CP_START DRM_IO( 0x41) 373 #define DRM_IOCTL_RADEON_CP_STOP DRM_IOW( 0x42, drm_radeon_cp_stop_t) 374 #define DRM_IOCTL_RADEON_CP_RESET DRM_IO( 0x43) 375 #define DRM_IOCTL_RADEON_CP_IDLE DRM_IO( 0x44) 376 #define DRM_IOCTL_RADEON_RESET DRM_IO( 0x45) 377 #define DRM_IOCTL_RADEON_FULLSCREEN DRM_IOW( 0x46, drm_radeon_fullscreen_t) 378 #define DRM_IOCTL_RADEON_SWAP DRM_IO( 0x47) 379 #define DRM_IOCTL_RADEON_CLEAR DRM_IOW( 0x48, drm_radeon_clear_t) 380 #define DRM_IOCTL_RADEON_VERTEX DRM_IOW( 0x49, drm_radeon_vertex_t) 381 #define DRM_IOCTL_RADEON_INDICES DRM_IOW( 0x4a, drm_radeon_indices_t) 382 #define DRM_IOCTL_RADEON_STIPPLE DRM_IOW( 0x4c, drm_radeon_stipple_t) 383 #define DRM_IOCTL_RADEON_INDIRECT DRM_IOWR(0x4d, drm_radeon_indirect_t) 384 #define DRM_IOCTL_RADEON_TEXTURE DRM_IOWR(0x4e, drm_radeon_texture_t) 385 #define DRM_IOCTL_RADEON_VERTEX2 DRM_IOW( 0x4f, drm_radeon_vertex2_t) 386 #define DRM_IOCTL_RADEON_CMDBUF DRM_IOW( 0x50, drm_radeon_cmd_buffer_t) 387 #define DRM_IOCTL_RADEON_GETPARAM DRM_IOWR(0x51, drm_radeon_getparam_t) 388 #define DRM_IOCTL_RADEON_FLIP DRM_IO( 0x52) 389 #define DRM_IOCTL_RADEON_ALLOC DRM_IOWR( 0x53, drm_radeon_mem_alloc_t) 390 #define DRM_IOCTL_RADEON_FREE DRM_IOW( 0x54, drm_radeon_mem_free_t) 391 #define DRM_IOCTL_RADEON_INIT_HEAP DRM_IOW( 0x55, drm_radeon_mem_init_heap_t) 392 #define DRM_IOCTL_RADEON_IRQ_EMIT DRM_IOWR( 0x56, drm_radeon_irq_emit_t) 393 #define DRM_IOCTL_RADEON_IRQ_WAIT DRM_IOW( 0x57, drm_radeon_irq_wait_t) 394 395 typedef struct drm_radeon_init { 396 enum { 397 RADEON_INIT_CP = 0x01, 398 RADEON_CLEANUP_CP = 0x02, 399 RADEON_INIT_R200_CP = 0x03, 400 } func; 401 unsigned long sarea_priv_offset; 402 int is_pci; 403 int cp_mode; 404 int agp_size; 405 int ring_size; 406 int usec_timeout; 407 408 unsigned int fb_bpp; 409 unsigned int front_offset, front_pitch; 410 unsigned int back_offset, back_pitch; 411 unsigned int depth_bpp; 412 unsigned int depth_offset, depth_pitch; 413 414 unsigned long fb_offset; 415 unsigned long mmio_offset; 416 unsigned long ring_offset; 417 unsigned long ring_rptr_offset; 418 unsigned long buffers_offset; 419 unsigned long agp_textures_offset; 420 } drm_radeon_init_t; 421 422 typedef struct drm_radeon_cp_stop { 423 int flush; 424 int idle; 425 } drm_radeon_cp_stop_t; 426 427 typedef struct drm_radeon_fullscreen { 428 enum { 429 RADEON_INIT_FULLSCREEN = 0x01, 430 RADEON_CLEANUP_FULLSCREEN = 0x02 431 } func; 432 } drm_radeon_fullscreen_t; 433 434 #define CLEAR_X1 0 435 #define CLEAR_Y1 1 436 #define CLEAR_X2 2 437 #define CLEAR_Y2 3 438 #define CLEAR_DEPTH 4 439 440 typedef union drm_radeon_clear_rect { 441 float f[5]; 442 unsigned int ui[5]; 443 } drm_radeon_clear_rect_t; 444 445 typedef struct drm_radeon_clear { 446 unsigned int flags; 447 unsigned int clear_color; 448 unsigned int clear_depth; 449 unsigned int color_mask; 450 unsigned int depth_mask; /* misnamed field: should be stencil */ 451 drm_radeon_clear_rect_t *depth_boxes; 452 } drm_radeon_clear_t; 453 454 typedef struct drm_radeon_vertex { 455 int prim; 456 int idx; /* Index of vertex buffer */ 457 int count; /* Number of vertices in buffer */ 458 int discard; /* Client finished with buffer? */ 459 } drm_radeon_vertex_t; 460 461 typedef struct drm_radeon_indices { 462 int prim; 463 int idx; 464 int start; 465 int end; 466 int discard; /* Client finished with buffer? */ 467 } drm_radeon_indices_t; 468 469 /* v1.2 - obsoletes drm_radeon_vertex and drm_radeon_indices 470 * - allows multiple primitives and state changes in a single ioctl 471 * - supports driver change to emit native primitives 472 */ 473 typedef struct drm_radeon_vertex2 { 474 int idx; /* Index of vertex buffer */ 475 int discard; /* Client finished with buffer? */ 476 int nr_states; 477 drm_radeon_state_t *state; 478 int nr_prims; 479 drm_radeon_prim_t *prim; 480 } drm_radeon_vertex2_t; 481 482 /* v1.3 - obsoletes drm_radeon_vertex2 483 * - allows arbitarily large cliprect list 484 * - allows updating of tcl packet, vector and scalar state 485 * - allows memory-efficient description of state updates 486 * - allows state to be emitted without a primitive 487 * (for clears, ctx switches) 488 * - allows more than one dma buffer to be referenced per ioctl 489 * - supports tcl driver 490 * - may be extended in future versions with new cmd types, packets 491 */ 492 typedef struct drm_radeon_cmd_buffer { 493 int bufsz; 494 char *buf; 495 int nbox; 496 drm_clip_rect_t *boxes; 497 } drm_radeon_cmd_buffer_t; 498 499 typedef struct drm_radeon_tex_image { 500 unsigned int x, y; /* Blit coordinates */ 501 unsigned int width, height; 502 const void *data; 503 } drm_radeon_tex_image_t; 504 505 typedef struct drm_radeon_texture { 506 int offset; 507 int pitch; 508 int format; 509 int width; /* Texture image coordinates */ 510 int height; 511 drm_radeon_tex_image_t *image; 512 } drm_radeon_texture_t; 513 514 typedef struct drm_radeon_stipple { 515 unsigned int *mask; 516 } drm_radeon_stipple_t; 517 518 typedef struct drm_radeon_indirect { 519 int idx; 520 int start; 521 int end; 522 int discard; 523 } drm_radeon_indirect_t; 524 525 526 /* 1.3: An ioctl to get parameters that aren't available to the 3d 527 * client any other way. 528 */ 529 #define RADEON_PARAM_AGP_BUFFER_OFFSET 1 /* card offset of 1st agp buffer */ 530 #define RADEON_PARAM_LAST_FRAME 2 531 #define RADEON_PARAM_LAST_DISPATCH 3 532 #define RADEON_PARAM_LAST_CLEAR 4 533 #define RADEON_PARAM_IRQ_NR 5 534 #define RADEON_PARAM_AGP_BASE 6 /* card offset of agp base */ 535 536 typedef struct drm_radeon_getparam { 537 int param; 538 int *value; 539 } drm_radeon_getparam_t; 540 541 /* 1.6: Set up a memory manager for regions of shared memory: 542 */ 543 #define RADEON_MEM_REGION_AGP 1 544 #define RADEON_MEM_REGION_FB 2 545 546 typedef struct drm_radeon_mem_alloc { 547 int region; 548 int alignment; 549 int size; 550 int *region_offset; /* offset from start of fb or agp */ 551 } drm_radeon_mem_alloc_t; 552 553 typedef struct drm_radeon_mem_free { 554 int region; 555 int region_offset; 556 } drm_radeon_mem_free_t; 557 558 typedef struct drm_radeon_mem_init_heap { 559 int region; 560 int size; 561 int start; 562 } drm_radeon_mem_init_heap_t; 563 564 565 /* 1.6: Userspace can request & wait on irq's: 566 */ 567 typedef struct drm_radeon_irq_emit { 568 int *irq_seq; 569 } drm_radeon_irq_emit_t; 570 571 typedef struct drm_radeon_irq_wait { 572 int irq_seq; 573 } drm_radeon_irq_wait_t; 574 575 576 #endif 577