1 #ifndef _I830_DRM_H_ 2 #define _I830_DRM_H_ 3 4 /* WARNING: These defines must be the same as what the Xserver uses. 5 * if you change them, you must change the defines in the Xserver. 6 * 7 * KW: Actually, you can't ever change them because doing so would 8 * break backwards compatibility. 9 */ 10 11 #ifndef _I830_DEFINES_ 12 #define _I830_DEFINES_ 13 14 #define I830_DMA_BUF_ORDER 12 15 #define I830_DMA_BUF_SZ (1<<I830_DMA_BUF_ORDER) 16 #define I830_DMA_BUF_NR 256 17 #define I830_NR_SAREA_CLIPRECTS 8 18 19 /* Each region is a minimum of 64k, and there are at most 64 of them. 20 */ 21 #define I830_NR_TEX_REGIONS 64 22 #define I830_LOG_MIN_TEX_REGION_SIZE 16 23 24 /* KW: These aren't correct but someone set them to two and then 25 * released the module. Now we can't change them as doing so would 26 * break backwards compatibility. 27 */ 28 #define I830_TEXTURE_COUNT 2 29 #define I830_TEXBLEND_COUNT I830_TEXTURE_COUNT 30 31 #define I830_TEXBLEND_SIZE 12 /* (4 args + op) * 2 + COLOR_FACTOR */ 32 33 #define I830_UPLOAD_CTX 0x1 34 #define I830_UPLOAD_BUFFERS 0x2 35 #define I830_UPLOAD_CLIPRECTS 0x4 36 #define I830_UPLOAD_TEX0_IMAGE 0x100 /* handled clientside */ 37 #define I830_UPLOAD_TEX0_CUBE 0x200 /* handled clientside */ 38 #define I830_UPLOAD_TEX1_IMAGE 0x400 /* handled clientside */ 39 #define I830_UPLOAD_TEX1_CUBE 0x800 /* handled clientside */ 40 #define I830_UPLOAD_TEX2_IMAGE 0x1000 /* handled clientside */ 41 #define I830_UPLOAD_TEX2_CUBE 0x2000 /* handled clientside */ 42 #define I830_UPLOAD_TEX3_IMAGE 0x4000 /* handled clientside */ 43 #define I830_UPLOAD_TEX3_CUBE 0x8000 /* handled clientside */ 44 #define I830_UPLOAD_TEX_N_IMAGE(n) (0x100 << (n * 2)) 45 #define I830_UPLOAD_TEX_N_CUBE(n) (0x200 << (n * 2)) 46 #define I830_UPLOAD_TEXIMAGE_MASK 0xff00 47 #define I830_UPLOAD_TEX0 0x10000 48 #define I830_UPLOAD_TEX1 0x20000 49 #define I830_UPLOAD_TEX2 0x40000 50 #define I830_UPLOAD_TEX3 0x80000 51 #define I830_UPLOAD_TEX_N(n) (0x10000 << (n)) 52 #define I830_UPLOAD_TEX_MASK 0xf0000 53 #define I830_UPLOAD_TEXBLEND0 0x100000 54 #define I830_UPLOAD_TEXBLEND1 0x200000 55 #define I830_UPLOAD_TEXBLEND2 0x400000 56 #define I830_UPLOAD_TEXBLEND3 0x800000 57 #define I830_UPLOAD_TEXBLEND_N(n) (0x100000 << (n)) 58 #define I830_UPLOAD_TEXBLEND_MASK 0xf00000 59 #define I830_UPLOAD_TEX_PALETTE_N(n) (0x1000000 << (n)) 60 #define I830_UPLOAD_TEX_PALETTE_SHARED 0x4000000 61 #define I830_UPLOAD_STIPPLE 0x8000000 62 63 /* Indices into buf.Setup where various bits of state are mirrored per 64 * context and per buffer. These can be fired at the card as a unit, 65 * or in a piecewise fashion as required. 66 */ 67 68 /* Destbuffer state 69 * - backbuffer linear offset and pitch -- invarient in the current dri 70 * - zbuffer linear offset and pitch -- also invarient 71 * - drawing origin in back and depth buffers. 72 * 73 * Keep the depth/back buffer state here to acommodate private buffers 74 * in the future. 75 */ 76 77 #define I830_DESTREG_CBUFADDR 0 78 #define I830_DESTREG_DBUFADDR 1 79 #define I830_DESTREG_DV0 2 80 #define I830_DESTREG_DV1 3 81 #define I830_DESTREG_SENABLE 4 82 #define I830_DESTREG_SR0 5 83 #define I830_DESTREG_SR1 6 84 #define I830_DESTREG_SR2 7 85 #define I830_DESTREG_DR0 8 86 #define I830_DESTREG_DR1 9 87 #define I830_DESTREG_DR2 10 88 #define I830_DESTREG_DR3 11 89 #define I830_DESTREG_DR4 12 90 #define I830_DEST_SETUP_SIZE 13 91 92 /* Context state 93 */ 94 #define I830_CTXREG_STATE1 0 95 #define I830_CTXREG_STATE2 1 96 #define I830_CTXREG_STATE3 2 97 #define I830_CTXREG_STATE4 3 98 #define I830_CTXREG_STATE5 4 99 #define I830_CTXREG_IALPHAB 5 100 #define I830_CTXREG_STENCILTST 6 101 #define I830_CTXREG_ENABLES_1 7 102 #define I830_CTXREG_ENABLES_2 8 103 #define I830_CTXREG_AA 9 104 #define I830_CTXREG_FOGCOLOR 10 105 #define I830_CTXREG_BLENDCOLR0 11 106 #define I830_CTXREG_BLENDCOLR 12 /* Dword 1 of 2 dword command */ 107 #define I830_CTXREG_VF 13 108 #define I830_CTXREG_VF2 14 109 #define I830_CTXREG_MCSB0 15 110 #define I830_CTXREG_MCSB1 16 111 #define I830_CTX_SETUP_SIZE 17 112 113 /* 1.3: Stipple state 114 */ 115 #define I830_STPREG_ST0 0 116 #define I830_STPREG_ST1 1 117 #define I830_STP_SETUP_SIZE 2 118 119 120 /* Texture state (per tex unit) 121 */ 122 123 #define I830_TEXREG_MI0 0 /* GFX_OP_MAP_INFO (6 dwords) */ 124 #define I830_TEXREG_MI1 1 125 #define I830_TEXREG_MI2 2 126 #define I830_TEXREG_MI3 3 127 #define I830_TEXREG_MI4 4 128 #define I830_TEXREG_MI5 5 129 #define I830_TEXREG_MF 6 /* GFX_OP_MAP_FILTER */ 130 #define I830_TEXREG_MLC 7 /* GFX_OP_MAP_LOD_CTL */ 131 #define I830_TEXREG_MLL 8 /* GFX_OP_MAP_LOD_LIMITS */ 132 #define I830_TEXREG_MCS 9 /* GFX_OP_MAP_COORD_SETS */ 133 #define I830_TEX_SETUP_SIZE 10 134 135 #define I830_TEXREG_TM0LI 0 /* load immediate 2 texture map n */ 136 #define I830_TEXREG_TM0S0 1 137 #define I830_TEXREG_TM0S1 2 138 #define I830_TEXREG_TM0S2 3 139 #define I830_TEXREG_TM0S3 4 140 #define I830_TEXREG_TM0S4 5 141 #define I830_TEXREG_NOP0 6 /* noop */ 142 #define I830_TEXREG_NOP1 7 /* noop */ 143 #define I830_TEXREG_NOP2 8 /* noop */ 144 #define __I830_TEXREG_MCS 9 /* GFX_OP_MAP_COORD_SETS -- shared */ 145 #define __I830_TEX_SETUP_SIZE 10 146 147 #define I830_FRONT 0x1 148 #define I830_BACK 0x2 149 #define I830_DEPTH 0x4 150 151 #endif /* _I830_DEFINES_ */ 152 153 typedef struct _drm_i830_init { 154 enum { 155 I830_INIT_DMA = 0x01, 156 I830_CLEANUP_DMA = 0x02 157 } func; 158 unsigned int mmio_offset; 159 unsigned int buffers_offset; 160 int sarea_priv_offset; 161 unsigned int ring_start; 162 unsigned int ring_end; 163 unsigned int ring_size; 164 unsigned int front_offset; 165 unsigned int back_offset; 166 unsigned int depth_offset; 167 unsigned int w; 168 unsigned int h; 169 unsigned int pitch; 170 unsigned int pitch_bits; 171 unsigned int back_pitch; 172 unsigned int depth_pitch; 173 unsigned int cpp; 174 } drm_i830_init_t; 175 176 /* Warning: If you change the SAREA structure you must change the Xserver 177 * structure as well */ 178 179 typedef struct _drm_i830_tex_region { 180 unsigned char next, prev; /* indices to form a circular LRU */ 181 unsigned char in_use; /* owned by a client, or free? */ 182 int age; /* tracked by clients to update local LRU's */ 183 } drm_i830_tex_region_t; 184 185 typedef struct _drm_i830_sarea { 186 unsigned int ContextState[I830_CTX_SETUP_SIZE]; 187 unsigned int BufferState[I830_DEST_SETUP_SIZE]; 188 unsigned int TexState[I830_TEXTURE_COUNT][I830_TEX_SETUP_SIZE]; 189 unsigned int TexBlendState[I830_TEXBLEND_COUNT][I830_TEXBLEND_SIZE]; 190 unsigned int TexBlendStateWordsUsed[I830_TEXBLEND_COUNT]; 191 unsigned int Palette[2][256]; 192 unsigned int dirty; 193 194 unsigned int nbox; 195 drm_clip_rect_t boxes[I830_NR_SAREA_CLIPRECTS]; 196 197 /* Maintain an LRU of contiguous regions of texture space. If 198 * you think you own a region of texture memory, and it has an 199 * age different to the one you set, then you are mistaken and 200 * it has been stolen by another client. If global texAge 201 * hasn't changed, there is no need to walk the list. 202 * 203 * These regions can be used as a proxy for the fine-grained 204 * texture information of other clients - by maintaining them 205 * in the same lru which is used to age their own textures, 206 * clients have an approximate lru for the whole of global 207 * texture space, and can make informed decisions as to which 208 * areas to kick out. There is no need to choose whether to 209 * kick out your own texture or someone else's - simply eject 210 * them all in LRU order. 211 */ 212 213 drm_i830_tex_region_t texList[I830_NR_TEX_REGIONS+1]; 214 /* Last elt is sentinal */ 215 int texAge; /* last time texture was uploaded */ 216 int last_enqueue; /* last time a buffer was enqueued */ 217 int last_dispatch; /* age of the most recently dispatched buffer */ 218 int last_quiescent; /* */ 219 int ctxOwner; /* last context to upload state */ 220 221 int vertex_prim; 222 223 int pf_enabled; /* is pageflipping allowed? */ 224 int pf_active; 225 int pf_current_page; /* which buffer is being displayed? */ 226 227 int perf_boxes; /* performance boxes to be displayed */ 228 229 /* Here's the state for texunits 2,3: 230 */ 231 unsigned int TexState2[I830_TEX_SETUP_SIZE]; 232 unsigned int TexBlendState2[I830_TEXBLEND_SIZE]; 233 unsigned int TexBlendStateWordsUsed2; 234 235 unsigned int TexState3[I830_TEX_SETUP_SIZE]; 236 unsigned int TexBlendState3[I830_TEXBLEND_SIZE]; 237 unsigned int TexBlendStateWordsUsed3; 238 239 unsigned int StippleState[I830_STP_SETUP_SIZE]; 240 } drm_i830_sarea_t; 241 242 /* Flags for perf_boxes 243 */ 244 #define I830_BOX_RING_EMPTY 0x1 /* populated by kernel */ 245 #define I830_BOX_FLIP 0x2 /* populated by kernel */ 246 #define I830_BOX_WAIT 0x4 /* populated by kernel & client */ 247 #define I830_BOX_TEXTURE_LOAD 0x8 /* populated by kernel */ 248 #define I830_BOX_LOST_CONTEXT 0x10 /* populated by client */ 249 250 251 /* I830 specific ioctls 252 * The device specific ioctl range is 0x40 to 0x79. 253 */ 254 #define DRM_IOCTL_I830_INIT DRM_IOW( 0x40, drm_i830_init_t) 255 #define DRM_IOCTL_I830_VERTEX DRM_IOW( 0x41, drm_i830_vertex_t) 256 #define DRM_IOCTL_I830_CLEAR DRM_IOW( 0x42, drm_i830_clear_t) 257 #define DRM_IOCTL_I830_FLUSH DRM_IO ( 0x43) 258 #define DRM_IOCTL_I830_GETAGE DRM_IO ( 0x44) 259 #define DRM_IOCTL_I830_GETBUF DRM_IOWR(0x45, drm_i830_dma_t) 260 #define DRM_IOCTL_I830_SWAP DRM_IO ( 0x46) 261 #define DRM_IOCTL_I830_COPY DRM_IOW( 0x47, drm_i830_copy_t) 262 #define DRM_IOCTL_I830_DOCOPY DRM_IO ( 0x48) 263 #define DRM_IOCTL_I830_FLIP DRM_IO ( 0x49) 264 #define DRM_IOCTL_I830_IRQ_EMIT DRM_IOWR(0x4a, drm_i830_irq_emit_t) 265 #define DRM_IOCTL_I830_IRQ_WAIT DRM_IOW( 0x4b, drm_i830_irq_wait_t) 266 #define DRM_IOCTL_I830_GETPARAM DRM_IOWR(0x4c, drm_i830_getparam_t) 267 #define DRM_IOCTL_I830_SETPARAM DRM_IOWR(0x4d, drm_i830_setparam_t) 268 269 typedef struct _drm_i830_clear { 270 int clear_color; 271 int clear_depth; 272 int flags; 273 unsigned int clear_colormask; 274 unsigned int clear_depthmask; 275 } drm_i830_clear_t; 276 277 278 279 /* These may be placeholders if we have more cliprects than 280 * I830_NR_SAREA_CLIPRECTS. In that case, the client sets discard to 281 * false, indicating that the buffer will be dispatched again with a 282 * new set of cliprects. 283 */ 284 typedef struct _drm_i830_vertex { 285 int idx; /* buffer index */ 286 int used; /* nr bytes in use */ 287 int discard; /* client is finished with the buffer? */ 288 } drm_i830_vertex_t; 289 290 typedef struct _drm_i830_copy_t { 291 int idx; /* buffer index */ 292 int used; /* nr bytes in use */ 293 void *address; /* Address to copy from */ 294 } drm_i830_copy_t; 295 296 typedef struct drm_i830_dma { 297 void *virtual; 298 int request_idx; 299 int request_size; 300 int granted; 301 } drm_i830_dma_t; 302 303 304 /* 1.3: Userspace can request & wait on irq's: 305 */ 306 typedef struct drm_i830_irq_emit { 307 int *irq_seq; 308 } drm_i830_irq_emit_t; 309 310 typedef struct drm_i830_irq_wait { 311 int irq_seq; 312 } drm_i830_irq_wait_t; 313 314 315 /* 1.3: New ioctl to query kernel params: 316 */ 317 #define I830_PARAM_IRQ_ACTIVE 1 318 319 typedef struct drm_i830_getparam { 320 int param; 321 int *value; 322 } drm_i830_getparam_t; 323 324 325 /* 1.3: New ioctl to set kernel params: 326 */ 327 #define I830_SETPARAM_USE_MI_BATCHBUFFER_START 1 328 329 typedef struct drm_i830_setparam { 330 int param; 331 int value; 332 } drm_i830_setparam_t; 333 334 335 #endif /* _I830_DRM_H_ */ 336