1 #ifndef _I810_DRM_H_ 2 #define _I810_DRM_H_ 3 4 /* WARNING: These defines must be the same as what the Xserver uses. 5 * if you change them, you must change the defines in the Xserver. 6 */ 7 8 #ifndef _I810_DEFINES_ 9 #define _I810_DEFINES_ 10 11 #define I810_DMA_BUF_ORDER 12 12 #define I810_DMA_BUF_SZ (1<<I810_DMA_BUF_ORDER) 13 #define I810_DMA_BUF_NR 256 14 #define I810_NR_SAREA_CLIPRECTS 8 15 16 /* Each region is a minimum of 64k, and there are at most 64 of them. 17 */ 18 #define I810_NR_TEX_REGIONS 64 19 #define I810_LOG_MIN_TEX_REGION_SIZE 16 20 #endif 21 22 #define I810_UPLOAD_TEX0IMAGE 0x1 /* handled clientside */ 23 #define I810_UPLOAD_TEX1IMAGE 0x2 /* handled clientside */ 24 #define I810_UPLOAD_CTX 0x4 25 #define I810_UPLOAD_BUFFERS 0x8 26 #define I810_UPLOAD_TEX0 0x10 27 #define I810_UPLOAD_TEX1 0x20 28 #define I810_UPLOAD_CLIPRECTS 0x40 29 30 31 /* Indices into buf.Setup where various bits of state are mirrored per 32 * context and per buffer. These can be fired at the card as a unit, 33 * or in a piecewise fashion as required. 34 */ 35 36 /* Destbuffer state 37 * - backbuffer linear offset and pitch -- invarient in the current dri 38 * - zbuffer linear offset and pitch -- also invarient 39 * - drawing origin in back and depth buffers. 40 * 41 * Keep the depth/back buffer state here to acommodate private buffers 42 * in the future. 43 */ 44 #define I810_DESTREG_DI0 0 /* CMD_OP_DESTBUFFER_INFO (2 dwords) */ 45 #define I810_DESTREG_DI1 1 46 #define I810_DESTREG_DV0 2 /* GFX_OP_DESTBUFFER_VARS (2 dwords) */ 47 #define I810_DESTREG_DV1 3 48 #define I810_DESTREG_DR0 4 /* GFX_OP_DRAWRECT_INFO (4 dwords) */ 49 #define I810_DESTREG_DR1 5 50 #define I810_DESTREG_DR2 6 51 #define I810_DESTREG_DR3 7 52 #define I810_DESTREG_DR4 8 53 #define I810_DEST_SETUP_SIZE 10 54 55 /* Context state 56 */ 57 #define I810_CTXREG_CF0 0 /* GFX_OP_COLOR_FACTOR */ 58 #define I810_CTXREG_CF1 1 59 #define I810_CTXREG_ST0 2 /* GFX_OP_STIPPLE */ 60 #define I810_CTXREG_ST1 3 61 #define I810_CTXREG_VF 4 /* GFX_OP_VERTEX_FMT */ 62 #define I810_CTXREG_MT 5 /* GFX_OP_MAP_TEXELS */ 63 #define I810_CTXREG_MC0 6 /* GFX_OP_MAP_COLOR_STAGES - stage 0 */ 64 #define I810_CTXREG_MC1 7 /* GFX_OP_MAP_COLOR_STAGES - stage 1 */ 65 #define I810_CTXREG_MC2 8 /* GFX_OP_MAP_COLOR_STAGES - stage 2 */ 66 #define I810_CTXREG_MA0 9 /* GFX_OP_MAP_ALPHA_STAGES - stage 0 */ 67 #define I810_CTXREG_MA1 10 /* GFX_OP_MAP_ALPHA_STAGES - stage 1 */ 68 #define I810_CTXREG_MA2 11 /* GFX_OP_MAP_ALPHA_STAGES - stage 2 */ 69 #define I810_CTXREG_SDM 12 /* GFX_OP_SRC_DEST_MONO */ 70 #define I810_CTXREG_FOG 13 /* GFX_OP_FOG_COLOR */ 71 #define I810_CTXREG_B1 14 /* GFX_OP_BOOL_1 */ 72 #define I810_CTXREG_B2 15 /* GFX_OP_BOOL_2 */ 73 #define I810_CTXREG_LCS 16 /* GFX_OP_LINEWIDTH_CULL_SHADE_MODE */ 74 #define I810_CTXREG_PV 17 /* GFX_OP_PV_RULE -- Invarient! */ 75 #define I810_CTXREG_ZA 18 /* GFX_OP_ZBIAS_ALPHAFUNC */ 76 #define I810_CTXREG_AA 19 /* GFX_OP_ANTIALIAS */ 77 #define I810_CTX_SETUP_SIZE 20 78 79 /* Texture state (per tex unit) 80 */ 81 #define I810_TEXREG_MI0 0 /* GFX_OP_MAP_INFO (4 dwords) */ 82 #define I810_TEXREG_MI1 1 83 #define I810_TEXREG_MI2 2 84 #define I810_TEXREG_MI3 3 85 #define I810_TEXREG_MF 4 /* GFX_OP_MAP_FILTER */ 86 #define I810_TEXREG_MLC 5 /* GFX_OP_MAP_LOD_CTL */ 87 #define I810_TEXREG_MLL 6 /* GFX_OP_MAP_LOD_LIMITS */ 88 #define I810_TEXREG_MCS 7 /* GFX_OP_MAP_COORD_SETS ??? */ 89 #define I810_TEX_SETUP_SIZE 8 90 91 /* Flags for clear ioctl 92 */ 93 #define I810_FRONT 0x1 94 #define I810_BACK 0x2 95 #define I810_DEPTH 0x4 96 97 98 typedef struct _drm_i810_init { 99 enum { 100 I810_INIT_DMA = 0x01, 101 I810_CLEANUP_DMA = 0x02 102 } func; 103 #if CONFIG_XFREE86_VERSION < XFREE86_VERSION(4,1,0,0) 104 int ring_map_idx; 105 int buffer_map_idx; 106 #else 107 unsigned int mmio_offset; 108 unsigned int buffers_offset; 109 #endif 110 int sarea_priv_offset; 111 unsigned int ring_start; 112 unsigned int ring_end; 113 unsigned int ring_size; 114 unsigned int front_offset; 115 unsigned int back_offset; 116 unsigned int depth_offset; 117 unsigned int overlay_offset; 118 unsigned int overlay_physical; 119 unsigned int w; 120 unsigned int h; 121 unsigned int pitch; 122 unsigned int pitch_bits; 123 } drm_i810_init_t; 124 125 /* Warning: If you change the SAREA structure you must change the Xserver 126 * structure as well */ 127 128 typedef struct _drm_i810_tex_region { 129 unsigned char next, prev; /* indices to form a circular LRU */ 130 unsigned char in_use; /* owned by a client, or free? */ 131 int age; /* tracked by clients to update local LRU's */ 132 } drm_i810_tex_region_t; 133 134 typedef struct _drm_i810_sarea { 135 unsigned int ContextState[I810_CTX_SETUP_SIZE]; 136 unsigned int BufferState[I810_DEST_SETUP_SIZE]; 137 unsigned int TexState[2][I810_TEX_SETUP_SIZE]; 138 unsigned int dirty; 139 140 unsigned int nbox; 141 drm_clip_rect_t boxes[I810_NR_SAREA_CLIPRECTS]; 142 143 /* Maintain an LRU of contiguous regions of texture space. If 144 * you think you own a region of texture memory, and it has an 145 * age different to the one you set, then you are mistaken and 146 * it has been stolen by another client. If global texAge 147 * hasn't changed, there is no need to walk the list. 148 * 149 * These regions can be used as a proxy for the fine-grained 150 * texture information of other clients - by maintaining them 151 * in the same lru which is used to age their own textures, 152 * clients have an approximate lru for the whole of global 153 * texture space, and can make informed decisions as to which 154 * areas to kick out. There is no need to choose whether to 155 * kick out your own texture or someone else's - simply eject 156 * them all in LRU order. 157 */ 158 159 drm_i810_tex_region_t texList[I810_NR_TEX_REGIONS+1]; 160 /* Last elt is sentinal */ 161 int texAge; /* last time texture was uploaded */ 162 int last_enqueue; /* last time a buffer was enqueued */ 163 int last_dispatch; /* age of the most recently dispatched buffer */ 164 int last_quiescent; /* */ 165 int ctxOwner; /* last context to upload state */ 166 167 int vertex_prim; 168 169 } drm_i810_sarea_t; 170 171 /* WARNING: If you change any of these defines, make sure to wear a bullet 172 * proof vest since these are part of the stable kernel<->userspace ABI 173 */ 174 175 /* i810 specific ioctls 176 * The device specific ioctl range is 0x40 to 0x79. 177 */ 178 #define DRM_IOCTL_I810_INIT DRM_IOW( 0x40, drm_i810_init_t) 179 #define DRM_IOCTL_I810_VERTEX DRM_IOW( 0x41, drm_i810_vertex_t) 180 #define DRM_IOCTL_I810_CLEAR DRM_IOW( 0x42, drm_i810_clear_t) 181 #define DRM_IOCTL_I810_FLUSH DRM_IO( 0x43) 182 #define DRM_IOCTL_I810_GETAGE DRM_IO( 0x44) 183 #define DRM_IOCTL_I810_GETBUF DRM_IOWR(0x45, drm_i810_dma_t) 184 #define DRM_IOCTL_I810_SWAP DRM_IO( 0x46) 185 #define DRM_IOCTL_I810_COPY DRM_IOW( 0x47, drm_i810_copy_t) 186 #define DRM_IOCTL_I810_DOCOPY DRM_IO( 0x48) 187 #define DRM_IOCTL_I810_OV0INFO DRM_IOR( 0x49, drm_i810_overlay_t) 188 #define DRM_IOCTL_I810_FSTATUS DRM_IO ( 0x4a) 189 #define DRM_IOCTL_I810_OV0FLIP DRM_IO ( 0x4b) 190 #define DRM_IOCTL_I810_MC DRM_IOW( 0x4c, drm_i810_mc_t) 191 #define DRM_IOCTL_I810_RSTATUS DRM_IO ( 0x4d ) 192 193 typedef struct _drm_i810_clear { 194 int clear_color; 195 int clear_depth; 196 int flags; 197 } drm_i810_clear_t; 198 199 /* These may be placeholders if we have more cliprects than 200 * I810_NR_SAREA_CLIPRECTS. In that case, the client sets discard to 201 * false, indicating that the buffer will be dispatched again with a 202 * new set of cliprects. 203 */ 204 typedef struct _drm_i810_vertex { 205 int idx; /* buffer index */ 206 int used; /* nr bytes in use */ 207 int discard; /* client is finished with the buffer? */ 208 } drm_i810_vertex_t; 209 210 typedef struct _drm_i810_copy_t { 211 int idx; /* buffer index */ 212 int used; /* nr bytes in use */ 213 void *address; /* Address to copy from */ 214 } drm_i810_copy_t; 215 216 #define PR_TRIANGLES (0x0<<18) 217 #define PR_TRISTRIP_0 (0x1<<18) 218 #define PR_TRISTRIP_1 (0x2<<18) 219 #define PR_TRIFAN (0x3<<18) 220 #define PR_POLYGON (0x4<<18) 221 #define PR_LINES (0x5<<18) 222 #define PR_LINESTRIP (0x6<<18) 223 #define PR_RECTS (0x7<<18) 224 #define PR_MASK (0x7<<18) 225 226 227 typedef struct drm_i810_dma { 228 void *virtual; 229 int request_idx; 230 int request_size; 231 int granted; 232 } drm_i810_dma_t; 233 234 typedef struct _drm_i810_overlay_t { 235 unsigned int offset; /* Address of the Overlay Regs */ 236 unsigned int physical; 237 } drm_i810_overlay_t; 238 239 typedef struct _drm_i810_mc { 240 int idx; /* buffer index */ 241 int used; /* nr bytes in use */ 242 int num_blocks; /* number of GFXBlocks */ 243 int *length; /* List of lengths for GFXBlocks (FUTURE)*/ 244 unsigned int last_render; /* Last Render Request */ 245 } drm_i810_mc_t; 246 247 248 #endif /* _I810_DRM_H_ */ 249