1 /* align.c - handle alignment exceptions for the Power PC.
2 *
3 * Copyright (c) 1996 Paul Mackerras <paulus@cs.anu.edu.au>
4 * Copyright (c) 1998-1999 TiVo, Inc.
5 * PowerPC 403GCX modifications.
6 * Copyright (c) 1999 Grant Erickson <grant@lcse.umn.edu>
7 * PowerPC 403GCX/405GP modifications.
8 * Copyright (c) 2001-2002 PPC64 team, IBM Corp
9 * 64-bit and Power4 support
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License
13 * as published by the Free Software Foundation; either version
14 * 2 of the License, or (at your option) any later version.
15 */
16
17 #include <linux/kernel.h>
18 #include <linux/mm.h>
19 #include <asm/ptrace.h>
20 #include <asm/processor.h>
21 #include <asm/uaccess.h>
22 #include <asm/system.h>
23 #include <asm/cache.h>
24 #include <asm/cputable.h>
25
26 struct aligninfo {
27 unsigned char len;
28 unsigned char flags;
29 };
30
31 #define IS_XFORM(inst) (((inst) >> 26) == 31)
32 #define IS_DSFORM(inst) (((inst) >> 26) >= 56)
33
34 #define INVALID { 0, 0 }
35
36 #define LD 1 /* load */
37 #define ST 2 /* store */
38 #define SE 4 /* sign-extend value */
39 #define F 8 /* to/from fp regs */
40 #define U 0x10 /* update index register */
41 #define M 0x20 /* multiple load/store */
42 #define SW 0x40 /* byte swap */
43
44 #define DCBZ 0x5f /* 8xx/82xx dcbz faults when cache not enabled */
45
46 /*
47 * The PowerPC stores certain bits of the instruction that caused the
48 * alignment exception in the DSISR register. This array maps those
49 * bits to information about the operand length and what the
50 * instruction would do.
51 */
52 static struct aligninfo aligninfo[128] = {
53 { 4, LD }, /* 00 0 0000: lwz / lwarx */
54 INVALID, /* 00 0 0001 */
55 { 4, ST }, /* 00 0 0010: stw */
56 INVALID, /* 00 0 0011 */
57 { 2, LD }, /* 00 0 0100: lhz */
58 { 2, LD+SE }, /* 00 0 0101: lha */
59 { 2, ST }, /* 00 0 0110: sth */
60 { 4, LD+M }, /* 00 0 0111: lmw */
61 { 4, LD+F }, /* 00 0 1000: lfs */
62 { 8, LD+F }, /* 00 0 1001: lfd */
63 { 4, ST+F }, /* 00 0 1010: stfs */
64 { 8, ST+F }, /* 00 0 1011: stfd */
65 INVALID, /* 00 0 1100 */
66 { 8, LD }, /* 00 0 1101: ld */
67 INVALID, /* 00 0 1110 */
68 { 8, ST }, /* 00 0 1111: std */
69 { 4, LD+U }, /* 00 1 0000: lwzu */
70 INVALID, /* 00 1 0001 */
71 { 4, ST+U }, /* 00 1 0010: stwu */
72 INVALID, /* 00 1 0011 */
73 { 2, LD+U }, /* 00 1 0100: lhzu */
74 { 2, LD+SE+U }, /* 00 1 0101: lhau */
75 { 2, ST+U }, /* 00 1 0110: sthu */
76 { 4, ST+M }, /* 00 1 0111: stmw */
77 { 4, LD+F+U }, /* 00 1 1000: lfsu */
78 { 8, LD+F+U }, /* 00 1 1001: lfdu */
79 { 4, ST+F+U }, /* 00 1 1010: stfsu */
80 { 8, ST+F+U }, /* 00 1 1011: stfdu */
81 INVALID, /* 00 1 1100 */
82 INVALID, /* 00 1 1101 */
83 INVALID, /* 00 1 1110 */
84 INVALID, /* 00 1 1111 */
85 { 8, LD }, /* 01 0 0000: ldx */
86 INVALID, /* 01 0 0001 */
87 { 8, ST }, /* 01 0 0010: stdx */
88 INVALID, /* 01 0 0011 */
89 INVALID, /* 01 0 0100 */
90 { 4, LD+SE }, /* 01 0 0101: lwax */
91 INVALID, /* 01 0 0110 */
92 INVALID, /* 01 0 0111 */
93 { 0, LD }, /* 01 0 1000: lswx */
94 { 0, LD }, /* 01 0 1001: lswi */
95 { 0, ST }, /* 01 0 1010: stswx */
96 { 0, ST }, /* 01 0 1011: stswi */
97 INVALID, /* 01 0 1100 */
98 { 8, LD+U }, /* 01 0 1101: ldu */
99 INVALID, /* 01 0 1110 */
100 { 8, ST+U }, /* 01 0 1111: stdu */
101 { 8, LD+U }, /* 01 1 0000: ldux */
102 INVALID, /* 01 1 0001 */
103 { 8, ST+U }, /* 01 1 0010: stdux */
104 INVALID, /* 01 1 0011 */
105 INVALID, /* 01 1 0100 */
106 { 4, LD+SE+U }, /* 01 1 0101: lwaux */
107 INVALID, /* 01 1 0110 */
108 INVALID, /* 01 1 0111 */
109 INVALID, /* 01 1 1000 */
110 INVALID, /* 01 1 1001 */
111 INVALID, /* 01 1 1010 */
112 INVALID, /* 01 1 1011 */
113 INVALID, /* 01 1 1100 */
114 INVALID, /* 01 1 1101 */
115 INVALID, /* 01 1 1110 */
116 INVALID, /* 01 1 1111 */
117 INVALID, /* 10 0 0000 */
118 INVALID, /* 10 0 0001 */
119 { 0, ST }, /* 10 0 0010: stwcx. */
120 INVALID, /* 10 0 0011 */
121 INVALID, /* 10 0 0100 */
122 INVALID, /* 10 0 0101 */
123 INVALID, /* 10 0 0110 */
124 INVALID, /* 10 0 0111 */
125 { 4, LD+SW }, /* 10 0 1000: lwbrx */
126 INVALID, /* 10 0 1001 */
127 { 4, ST+SW }, /* 10 0 1010: stwbrx */
128 INVALID, /* 10 0 1011 */
129 { 2, LD+SW }, /* 10 0 1100: lhbrx */
130 { 4, LD+SE }, /* 10 0 1101 lwa */
131 { 2, ST+SW }, /* 10 0 1110: sthbrx */
132 INVALID, /* 10 0 1111 */
133 INVALID, /* 10 1 0000 */
134 INVALID, /* 10 1 0001 */
135 INVALID, /* 10 1 0010 */
136 INVALID, /* 10 1 0011 */
137 INVALID, /* 10 1 0100 */
138 INVALID, /* 10 1 0101 */
139 INVALID, /* 10 1 0110 */
140 INVALID, /* 10 1 0111 */
141 INVALID, /* 10 1 1000 */
142 INVALID, /* 10 1 1001 */
143 INVALID, /* 10 1 1010 */
144 INVALID, /* 10 1 1011 */
145 INVALID, /* 10 1 1100 */
146 INVALID, /* 10 1 1101 */
147 INVALID, /* 10 1 1110 */
148 { L1_CACHE_BYTES, ST }, /* 10 1 1111: dcbz */
149 { 4, LD }, /* 11 0 0000: lwzx */
150 INVALID, /* 11 0 0001 */
151 { 4, ST }, /* 11 0 0010: stwx */
152 INVALID, /* 11 0 0011 */
153 { 2, LD }, /* 11 0 0100: lhzx */
154 { 2, LD+SE }, /* 11 0 0101: lhax */
155 { 2, ST }, /* 11 0 0110: sthx */
156 INVALID, /* 11 0 0111 */
157 { 4, LD+F }, /* 11 0 1000: lfsx */
158 { 8, LD+F }, /* 11 0 1001: lfdx */
159 { 4, ST+F }, /* 11 0 1010: stfsx */
160 { 8, ST+F }, /* 11 0 1011: stfdx */
161 INVALID, /* 11 0 1100 */
162 { 8, LD+M }, /* 11 0 1101: lmd */
163 INVALID, /* 11 0 1110 */
164 { 8, ST+M }, /* 11 0 1111: stmd */
165 { 4, LD+U }, /* 11 1 0000: lwzux */
166 INVALID, /* 11 1 0001 */
167 { 4, ST+U }, /* 11 1 0010: stwux */
168 INVALID, /* 11 1 0011 */
169 { 2, LD+U }, /* 11 1 0100: lhzux */
170 { 2, LD+SE+U }, /* 11 1 0101: lhaux */
171 { 2, ST+U }, /* 11 1 0110: sthux */
172 INVALID, /* 11 1 0111 */
173 { 4, LD+F+U }, /* 11 1 1000: lfsux */
174 { 8, LD+F+U }, /* 11 1 1001: lfdux */
175 { 4, ST+F+U }, /* 11 1 1010: stfsux */
176 { 8, ST+F+U }, /* 11 1 1011: stfdux */
177 INVALID, /* 11 1 1100 */
178 INVALID, /* 11 1 1101 */
179 INVALID, /* 11 1 1110 */
180 INVALID, /* 11 1 1111 */
181 };
182
183 #define SWAP(a, b) (t = (a), (a) = (b), (b) = t)
184
make_dsisr(unsigned instr)185 unsigned static inline make_dsisr( unsigned instr )
186 {
187 unsigned dsisr;
188
189 /* create a DSISR value from the instruction */
190 dsisr = (instr & 0x03ff0000) >> 16; /* bits 6:15 --> 22:31 */
191
192 if ( IS_XFORM(instr) ) {
193 dsisr |= (instr & 0x00000006) << 14; /* bits 29:30 --> 15:16 */
194 dsisr |= (instr & 0x00000040) << 8; /* bit 25 --> 17 */
195 dsisr |= (instr & 0x00000780) << 3; /* bits 21:24 --> 18:21 */
196 }
197 else {
198 dsisr |= (instr & 0x04000000) >> 12; /* bit 5 --> 17 */
199 dsisr |= (instr & 0x78000000) >> 17; /* bits 1: 4 --> 18:21 */
200 if ( IS_DSFORM(instr) ) {
201 dsisr |= (instr & 0x00000003) << 18; /* bits 30:31 --> 12:13 */
202 }
203 }
204
205 return dsisr;
206 }
207
208 int
fix_alignment(struct pt_regs * regs)209 fix_alignment(struct pt_regs *regs)
210 {
211 unsigned int instr, nb, flags;
212 int t;
213 unsigned long reg, areg;
214 unsigned long i;
215 int ret;
216 unsigned dsisr;
217 unsigned char *addr, *p;
218 unsigned long *lp;
219 union {
220 long ll;
221 double dd;
222 unsigned char v[8];
223 struct {
224 unsigned hi32;
225 int low32;
226 } x32;
227 struct {
228 unsigned char hi48[6];
229 short low16;
230 } x16;
231 } data;
232
233 /*
234 * Return 1 on success
235 * Return 0 if unable to handle the interrupt
236 * Return -EFAULT if data address is bad
237 */
238
239 dsisr = regs->dsisr;
240
241 /* Power4 doesn't set DSISR for an alignment interrupt */
242 if (cur_cpu_spec->cpu_features & CPU_FTR_NODSISRALIGN)
243 dsisr = make_dsisr( *((unsigned *)regs->nip) );
244
245 /* extract the operation and registers from the dsisr */
246 reg = (dsisr >> 5) & 0x1f; /* source/dest register */
247 areg = dsisr & 0x1f; /* register to update */
248 instr = (dsisr >> 10) & 0x7f;
249 instr |= (dsisr >> 13) & 0x60;
250
251 /* Lookup the operation in our table */
252 nb = aligninfo[instr].len;
253 flags = aligninfo[instr].flags;
254
255 /* DAR has the operand effective address */
256 addr = (unsigned char *)regs->dar;
257
258 /* A size of 0 indicates an instruction we don't support */
259 /* we also don't support the multiples (lmw, stmw, lmd, stmd) */
260 if ((nb == 0) || (flags & M))
261 return 0; /* too hard or invalid instruction */
262
263 /*
264 * Special handling for dcbz
265 * dcbz may give an alignment exception for accesses to caching inhibited
266 * storage
267 */
268 if (instr == DCBZ)
269 addr = (unsigned char *) ((unsigned long)addr & -L1_CACHE_BYTES);
270
271 /* Verify the address of the operand */
272 if (user_mode(regs)) {
273 if (verify_area((flags & ST? VERIFY_WRITE: VERIFY_READ), addr, nb))
274 return -EFAULT; /* bad address */
275 }
276
277 /* Force the fprs into the save area so we can reference them */
278 if ((flags & F) && (regs->msr & MSR_FP))
279 giveup_fpu(current);
280
281 /* If we are loading, get the data from user space */
282 if (flags & LD) {
283 data.ll = 0;
284 ret = 0;
285 p = addr;
286 switch (nb) {
287 case 8:
288 ret |= __get_user(data.v[0], p++);
289 ret |= __get_user(data.v[1], p++);
290 ret |= __get_user(data.v[2], p++);
291 ret |= __get_user(data.v[3], p++);
292 case 4:
293 ret |= __get_user(data.v[4], p++);
294 ret |= __get_user(data.v[5], p++);
295 case 2:
296 ret |= __get_user(data.v[6], p++);
297 ret |= __get_user(data.v[7], p++);
298 if (ret)
299 return -EFAULT;
300 }
301 }
302
303 /* If we are storing, get the data from the saved gpr or fpr */
304 if (flags & ST) {
305 if (flags & F) {
306 if (nb == 4) {
307 /* Doing stfs, have to convert to single */
308 enable_kernel_fp();
309 cvt_df(¤t->thread.fpr[reg], (float *)&data.v[4], ¤t->thread.fpscr);
310 disable_kernel_fp();
311 }
312 else
313 data.dd = current->thread.fpr[reg];
314 }
315 else
316 data.ll = regs->gpr[reg];
317 }
318
319 /* Swap bytes as needed */
320 if (flags & SW) {
321 if (nb == 2)
322 SWAP(data.v[6], data.v[7]);
323 else { /* nb must be 4 */
324 SWAP(data.v[4], data.v[7]);
325 SWAP(data.v[5], data.v[6]);
326 }
327 }
328
329 /* Sign extend as needed */
330 if (flags & SE) {
331 if ( nb == 2 )
332 data.ll = data.x16.low16;
333 else /* nb must be 4 */
334 data.ll = data.x32.low32;
335 }
336
337 /* If we are loading, move the data to the gpr or fpr */
338 if (flags & LD) {
339 if (flags & F) {
340 if (nb == 4) {
341 /* Doing lfs, have to convert to double */
342 enable_kernel_fp();
343 cvt_fd((float *)&data.v[4], ¤t->thread.fpr[reg], ¤t->thread.fpscr);
344 disable_kernel_fp();
345 }
346 else
347 current->thread.fpr[reg] = data.dd;
348 }
349 else
350 regs->gpr[reg] = data.ll;
351 }
352
353 /* If we are storing, copy the data to the user */
354 if (flags & ST) {
355 ret = 0;
356 p = addr;
357 switch (nb) {
358 case 128: /* Special case - must be dcbz */
359 lp = (unsigned long *)p;
360 for (i = 0; i < L1_CACHE_BYTES / sizeof(long); ++i)
361 ret |= __put_user(0, lp++);
362 break;
363 case 8:
364 ret |= __put_user(data.v[0], p++);
365 ret |= __put_user(data.v[1], p++);
366 ret |= __put_user(data.v[2], p++);
367 ret |= __put_user(data.v[3], p++);
368 case 4:
369 ret |= __put_user(data.v[4], p++);
370 ret |= __put_user(data.v[5], p++);
371 case 2:
372 ret |= __put_user(data.v[6], p++);
373 ret |= __put_user(data.v[7], p++);
374 }
375 if (ret)
376 return -EFAULT;
377 }
378
379 /* Update RA as needed */
380 if (flags & U) {
381 regs->gpr[areg] = regs->dar;
382 }
383
384 return 1;
385 }
386
387