1 2 /* 3 * A collection of structures, addresses, and values associated with 4 * the Embedded Planet RPX6 (or RPX Super) MPC8260 board. 5 * Copied from the RPX-Classic and SBS8260 stuff. 6 * 7 * Copyright (c) 2001 Dan Malek (dan@embeddededge.com) 8 */ 9 #ifdef __KERNEL__ 10 #ifndef __MACH_RPXSUPER_DEFS 11 #define __MACH_RPXSUPER_DEFS 12 13 /* A Board Information structure that is given to a program when 14 * prom starts it up. 15 */ 16 typedef struct bd_info { 17 unsigned int bi_memstart; /* Memory start address */ 18 unsigned int bi_memsize; /* Memory (end) size in bytes */ 19 unsigned int bi_nvsize; /* NVRAM size in bytes (can be 0) */ 20 unsigned int bi_intfreq; /* Internal Freq, in Hz */ 21 unsigned int bi_busfreq; /* Bus Freq, in MHz */ 22 unsigned int bi_cpmfreq; /* CPM Freq, in MHz */ 23 unsigned int bi_brgfreq; /* BRG Freq, in MHz */ 24 unsigned int bi_vco; /* VCO Out from PLL */ 25 unsigned int bi_baudrate; /* Default console baud rate */ 26 unsigned int bi_immr; /* IMMR when called from boot rom */ 27 unsigned char bi_enetaddr[6]; 28 } bd_t; 29 30 extern bd_t m8xx_board_info; 31 32 /* Memory map is configured by the PROM startup. 33 * We just map a few things we need. The CSR is actually 4 byte-wide 34 * registers that can be accessed as 8-, 16-, or 32-bit values. 35 */ 36 #define CPM_MAP_ADDR ((uint)0xf0000000) 37 #define RPX_CSR_ADDR ((uint)0xfa000000) 38 #define RPX_CSR_SIZE ((uint)(512 * 1024)) 39 #define RPX_NVRTC_ADDR ((uint)0xfa080000) 40 #define RPX_NVRTC_SIZE ((uint)(512 * 1024)) 41 42 /* The RPX6 has 16, byte wide control/status registers. 43 * Not all are used (yet). 44 */ 45 extern volatile u_char *rpx6_csr_addr; 46 47 /* Things of interest in the CSR. 48 */ 49 #define BCSR0_ID_MASK ((u_char)0xf0) /* Read only */ 50 #define BCSR0_SWITCH_MASK ((u_char)0x0f) /* Read only */ 51 #define BCSR1_XCVR_SMC1 ((u_char)0x80) 52 #define BCSR1_XCVR_SMC2 ((u_char)0x40) 53 #define BCSR2_FLASH_WENABLE ((u_char)0x20) 54 #define BCSR2_NVRAM_ENABLE ((u_char)0x10) 55 #define BCSR2_ALT_IRQ2 ((u_char)0x08) 56 #define BCSR2_ALT_IRQ3 ((u_char)0x04) 57 #define BCSR2_PRST ((u_char)0x02) /* Force reset */ 58 #define BCSR2_ENPRST ((u_char)0x01) /* Enable POR */ 59 #define BCSR3_MODCLK_MASK ((u_char)0xe0) 60 #define BCSR3_ENCLKHDR ((u_char)0x10) 61 #define BCSR3_LED5 ((u_char)0x04) /* 0 == on */ 62 #define BCSR3_LED6 ((u_char)0x02) /* 0 == on */ 63 #define BCSR3_LED7 ((u_char)0x01) /* 0 == on */ 64 #define BCSR4_EN_PHY ((u_char)0x80) /* Enable PHY */ 65 #define BCSR4_EN_MII ((u_char)0x40) /* Enable PHY */ 66 #define BCSR4_MII_READ ((u_char)0x04) 67 #define BCSR4_MII_MDC ((u_char)0x02) 68 #define BCSR4_MII_MDIO ((u_char)0x02) 69 #define BCSR13_FETH_IRQMASK ((u_char)0xf0) 70 #define BCSR15_FETH_IRQ ((u_char)0x20) 71 72 #endif 73 #endif /* __KERNEL__ */ 74