1 2 /* 3 * A collection of structures, addresses, and values associated with 4 * the Motorola MPC8260ADS/MPC8266ADS-PCI boards. 5 * Copied from the RPX-Classic and SBS8260 stuff. 6 * 7 * Copyright (c) 2001 Dan Malek (dan@mvista.com) 8 */ 9 #ifdef __KERNEL__ 10 #ifndef __MACH_ADS8260_DEFS 11 #define __MACH_ADS8260_DEFS 12 13 #include <linux/config.h> 14 15 #include <asm/ppcboot.h> 16 17 /* Memory map is configured by the PROM startup. 18 * We just map a few things we need. The CSR is actually 4 byte-wide 19 * registers that can be accessed as 8-, 16-, or 32-bit values. 20 */ 21 #define CPM_MAP_ADDR ((uint)0xf0000000) 22 #define BCSR_ADDR ((uint)0xf4500000) 23 #define BCSR_SIZE ((uint)(32 * 1024)) 24 25 /* The ADS8260 has 16, 32-bit wide control/status registers, accessed 26 * only on word boundaries. 27 * Not all are used (yet), or are interesting to us (yet). 28 */ 29 30 /* Things of interest in the CSR. 31 */ 32 #define BCSR0_LED0 ((uint)0x02000000) /* 0 == on */ 33 #define BCSR0_LED1 ((uint)0x01000000) /* 0 == on */ 34 #define BCSR1_FETHIEN ((uint)0x08000000) /* 0 == enable */ 35 #define BCSR1_FETH_RST ((uint)0x04000000) /* 0 == reset */ 36 #define BCSR1_RS232_EN1 ((uint)0x02000000) /* 0 == enable */ 37 #define BCSR1_RS232_EN2 ((uint)0x01000000) /* 0 == enable */ 38 39 #define PHY_INTERRUPT SIU_INT_IRQ7 40 41 #ifdef CONFIG_PCI 42 /* PCI interrupt controller */ 43 #define PCI_INT_STAT_REG 0xF8200000 44 #define PCI_INT_MASK_REG 0xF8200004 45 #define PIRQA (NR_SIU_INTS + 0) 46 #define PIRQB (NR_SIU_INTS + 1) 47 #define PIRQC (NR_SIU_INTS + 2) 48 #define PIRQD (NR_SIU_INTS + 3) 49 50 /* 51 * PCI memory map definitions for MPC8266ADS-PCI. 52 * 53 * processor view 54 * local address PCI address target 55 * 0x80000000-0x9FFFFFFF 0x80000000-0x9FFFFFFF PCI mem with prefetch 56 * 0xA0000000-0xBFFFFFFF 0xA0000000-0xBFFFFFFF PCI mem w/o prefetch 57 * 0xF4000000-0xF7FFFFFF 0x00000000-0x03FFFFFF PCI IO 58 * 59 * PCI master view 60 * local address PCI address target 61 * 0x00000000-0x1FFFFFFF 0x00000000-0x1FFFFFFF MPC8266 local memory 62 */ 63 64 /* window for a PCI master to access MPC8266 memory */ 65 #define PCI_SLV_MEM_LOCAL 0x00000000 /* Local base */ 66 #define PCI_SLV_MEM_BUS 0x00000000 /* PCI base */ 67 68 /* window for the processor to access PCI memory with prefetching */ 69 #define PCI_MSTR_MEM_LOCAL 0x80000000 /* Local base */ 70 #define PCI_MSTR_MEM_BUS 0x80000000 /* PCI base */ 71 #define PCI_MSTR_MEM_SIZE 0x20000000 /* 512MB */ 72 73 /* window for the processor to access PCI memory without prefetching */ 74 #define PCI_MSTR_MEMIO_LOCAL 0xA0000000 /* Local base */ 75 #define PCI_MSTR_MEMIO_BUS 0xA0000000 /* PCI base */ 76 #define PCI_MSTR_MEMIO_SIZE 0x20000000 /* 512MB */ 77 78 /* window for the processor to access PCI I/O */ 79 #define PCI_MSTR_IO_LOCAL 0xF4000000 /* Local base */ 80 #define PCI_MSTR_IO_BUS 0x00000000 /* PCI base */ 81 #define PCI_MSTR_IO_SIZE 0x04000000 /* 64MB */ 82 83 #define _IO_BASE PCI_MSTR_IO_LOCAL 84 #define _ISA_MEM_BASE PCI_MSTR_MEMIO_LOCAL 85 #define PCI_DRAM_OFFSET PCI_SLV_MEM_BUS 86 #endif /* CONFIG_PCI */ 87 88 #endif /* __MACH_ADS8260_DEFS */ 89 #endif /* __KERNEL__ */ 90