1 /*
2 * Support for PCI bridges found on Power Macintoshes.
3 * At present the "bandit" and "chaos" bridges are supported.
4 * Fortunately you access configuration space in the same
5 * way with either bridge.
6 *
7 * Copyright (C) 1997 Paul Mackerras (paulus@cs.anu.edu.au)
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version
12 * 2 of the License, or (at your option) any later version.
13 */
14
15 #include <linux/kernel.h>
16 #include <linux/pci.h>
17 #include <linux/delay.h>
18 #include <linux/string.h>
19 #include <linux/init.h>
20 #include <linux/bootmem.h>
21
22 #include <asm/sections.h>
23 #include <asm/io.h>
24 #include <asm/prom.h>
25 #include <asm/pci-bridge.h>
26 #include <asm/machdep.h>
27 #include <asm/pmac_feature.h>
28
29 #undef DEBUG
30
31 static void add_bridges(struct device_node *dev);
32
33 /* XXX Could be per-controller, but I don't think we risk anything by
34 * assuming we won't have both UniNorth and Bandit */
35 static int has_uninorth;
36
37 /*
38 * Magic constants for enabling cache coherency in the bandit/PSX bridge.
39 */
40 #define BANDIT_DEVID_2 8
41 #define BANDIT_REVID 3
42
43 #define BANDIT_DEVNUM 11
44 #define BANDIT_MAGIC 0x50
45 #define BANDIT_COHERENT 0x40
46
47 static int __init
fixup_one_level_bus_range(struct device_node * node,int higher)48 fixup_one_level_bus_range(struct device_node *node, int higher)
49 {
50 for (; node != 0;node = node->sibling) {
51 int * bus_range;
52 unsigned int *class_code;
53 int len;
54
55 /* For PCI<->PCI bridges or CardBus bridges, we go down */
56 class_code = (unsigned int *) get_property(node, "class-code", 0);
57 if (!class_code || ((*class_code >> 8) != PCI_CLASS_BRIDGE_PCI &&
58 (*class_code >> 8) != PCI_CLASS_BRIDGE_CARDBUS))
59 continue;
60 bus_range = (int *) get_property(node, "bus-range", &len);
61 if (bus_range != NULL && len > 2 * sizeof(int)) {
62 if (bus_range[1] > higher)
63 higher = bus_range[1];
64 }
65 higher = fixup_one_level_bus_range(node->child, higher);
66 }
67 return higher;
68 }
69
70 /* This routine fixes the "bus-range" property of all bridges in the
71 * system since they tend to have their "last" member wrong on macs
72 *
73 * Note that the bus numbers manipulated here are OF bus numbers, they
74 * are not Linux bus numbers.
75 */
76 static void __init
fixup_bus_range(struct device_node * bridge)77 fixup_bus_range(struct device_node *bridge)
78 {
79 int * bus_range;
80 int len;
81
82 /* Lookup the "bus-range" property for the hose */
83 bus_range = (int *) get_property(bridge, "bus-range", &len);
84 if (bus_range == NULL || len < 2 * sizeof(int)) {
85 printk(KERN_WARNING "Can't get bus-range for %s\n",
86 bridge->full_name);
87 return;
88 }
89 bus_range[1] = fixup_one_level_bus_range(bridge->child, bus_range[1]);
90 }
91
92 /*
93 * Apple MacRISC (UniNorth, Bandit, Chaos) PCI controllers.
94 *
95 * The "Bandit" version is present in all early PCI PowerMacs,
96 * and up to the first ones using Grackle. Some machines may
97 * have 2 bandit controllers (2 PCI busses).
98 *
99 * "Chaos" is used in some "Bandit"-type machines as a bridge
100 * for the separate display bus. It is accessed the same
101 * way as bandit, but cannot be probed for devices. It therefore
102 * has its own config access functions.
103 *
104 * The "UniNorth" version is present in all Core99 machines
105 * (iBook, G4, new IMacs, and all the recent Apple machines).
106 * It contains 3 controllers in one ASIC.
107 */
108
109 #define MACRISC_CFA0(devfn, off) \
110 ((1 << (unsigned long)PCI_SLOT(dev_fn)) \
111 | (((unsigned long)PCI_FUNC(dev_fn)) << 8) \
112 | (((unsigned long)(off)) & 0xFCUL))
113
114 #define MACRISC_CFA1(bus, devfn, off) \
115 ((((unsigned long)(bus)) << 16) \
116 |(((unsigned long)(devfn)) << 8) \
117 |(((unsigned long)(off)) & 0xFCUL) \
118 |1UL)
119
120 static unsigned int __pmac
macrisc_cfg_access(struct pci_controller * hose,u8 bus,u8 dev_fn,u8 offset)121 macrisc_cfg_access(struct pci_controller* hose, u8 bus, u8 dev_fn, u8 offset)
122 {
123 unsigned int caddr;
124
125 if (bus == hose->first_busno) {
126 if (dev_fn < (11 << 3))
127 return 0;
128 caddr = MACRISC_CFA0(dev_fn, offset);
129 } else
130 caddr = MACRISC_CFA1(bus, dev_fn, offset);
131
132 /* Uninorth will return garbage if we don't read back the value ! */
133 do {
134 out_le32(hose->cfg_addr, caddr);
135 } while(in_le32(hose->cfg_addr) != caddr);
136
137 offset &= has_uninorth ? 0x07 : 0x03;
138 return (unsigned int)(hose->cfg_data) + (unsigned int)offset;
139 }
140
141 #define cfg_read(val, addr, type, op, op2) \
142 *val = op((type)(addr))
143 #define cfg_write(val, addr, type, op, op2) \
144 op((type *)(addr), (val)); (void) op2((type *)(addr))
145
146 #define cfg_read_bad(val, size) *val = bad_##size;
147 #define cfg_write_bad(val, size)
148
149 #define bad_byte 0xff
150 #define bad_word 0xffff
151 #define bad_dword 0xffffffffU
152
153 #define MACRISC_PCI_OP(rw, size, type, op, op2) \
154 static int __pmac \
155 macrisc_##rw##_config_##size(struct pci_dev *dev, int off, type val) \
156 { \
157 struct pci_controller *hose = dev->sysdata; \
158 unsigned int addr; \
159 \
160 addr = macrisc_cfg_access(hose, dev->bus->number, dev->devfn, off); \
161 if (!addr) { \
162 cfg_##rw##_bad(val, size) \
163 return PCIBIOS_DEVICE_NOT_FOUND; \
164 } \
165 cfg_##rw(val, addr, type, op, op2); \
166 return PCIBIOS_SUCCESSFUL; \
167 }
168
169 MACRISC_PCI_OP(read, byte, u8 *, in_8, x)
170 MACRISC_PCI_OP(read, word, u16 *, in_le16, x)
171 MACRISC_PCI_OP(read, dword, u32 *, in_le32, x)
172 MACRISC_PCI_OP(write, byte, u8, out_8, in_8)
173 MACRISC_PCI_OP(write, word, u16, out_le16, in_le16)
174 MACRISC_PCI_OP(write, dword, u32, out_le32, in_le32)
175
176 static struct pci_ops macrisc_pci_ops =
177 {
178 macrisc_read_config_byte,
179 macrisc_read_config_word,
180 macrisc_read_config_dword,
181 macrisc_write_config_byte,
182 macrisc_write_config_word,
183 macrisc_write_config_dword
184 };
185
186 /*
187 * Verifiy that a specific (bus, dev_fn) exists on chaos
188 */
189 static int __pmac
chaos_validate_dev(struct pci_dev * dev,int offset)190 chaos_validate_dev(struct pci_dev *dev, int offset)
191 {
192 if(pci_device_to_OF_node(dev) == 0)
193 return PCIBIOS_DEVICE_NOT_FOUND;
194 if((dev->vendor == 0x106b) && (dev->device == 3) && (offset >= 0x10) &&
195 (offset != 0x14) && (offset != 0x18) && (offset <= 0x24)) {
196 return PCIBIOS_BAD_REGISTER_NUMBER;
197 }
198 return PCIBIOS_SUCCESSFUL;
199 }
200
201 #define CHAOS_PCI_OP(rw, size, type) \
202 static int __pmac \
203 chaos_##rw##_config_##size(struct pci_dev *dev, int off, type val) \
204 { \
205 int result = chaos_validate_dev(dev, off); \
206 if(result == PCIBIOS_BAD_REGISTER_NUMBER) { \
207 cfg_##rw##_bad(val, size) \
208 return PCIBIOS_BAD_REGISTER_NUMBER; \
209 } \
210 if(result == PCIBIOS_SUCCESSFUL) \
211 return macrisc_##rw##_config_##size(dev, off, val); \
212 return result; \
213 }
214
215 CHAOS_PCI_OP(read, byte, u8 *)
216 CHAOS_PCI_OP(read, word, u16 *)
217 CHAOS_PCI_OP(read, dword, u32 *)
218 CHAOS_PCI_OP(write, byte, u8)
219 CHAOS_PCI_OP(write, word, u16)
220 CHAOS_PCI_OP(write, dword, u32)
221
222 static struct pci_ops chaos_pci_ops =
223 {
224 chaos_read_config_byte,
225 chaos_read_config_word,
226 chaos_read_config_dword,
227 chaos_write_config_byte,
228 chaos_write_config_word,
229 chaos_write_config_dword
230 };
231
232
233 /*
234 * For a bandit bridge, turn on cache coherency if necessary.
235 * N.B. we could clean this up using the hose ops directly.
236 */
237 static void __init
init_bandit(struct pci_controller * bp)238 init_bandit(struct pci_controller *bp)
239 {
240 unsigned int vendev, magic;
241 int rev;
242
243 /* read the word at offset 0 in config space for device 11 */
244 out_le32(bp->cfg_addr, (1UL << BANDIT_DEVNUM) + PCI_VENDOR_ID);
245 udelay(2);
246 vendev = in_le32((volatile unsigned int *)bp->cfg_data);
247 if (vendev == (PCI_DEVICE_ID_APPLE_BANDIT << 16) +
248 PCI_VENDOR_ID_APPLE) {
249 /* read the revision id */
250 out_le32(bp->cfg_addr,
251 (1UL << BANDIT_DEVNUM) + PCI_REVISION_ID);
252 udelay(2);
253 rev = in_8(bp->cfg_data);
254 if (rev != BANDIT_REVID)
255 printk(KERN_WARNING
256 "Unknown revision %d for bandit\n", rev);
257 } else if (vendev != (BANDIT_DEVID_2 << 16) + PCI_VENDOR_ID_APPLE) {
258 printk(KERN_WARNING "bandit isn't? (%x)\n", vendev);
259 return;
260 }
261
262 /* read the word at offset 0x50 */
263 out_le32(bp->cfg_addr, (1UL << BANDIT_DEVNUM) + BANDIT_MAGIC);
264 udelay(2);
265 magic = in_le32((volatile unsigned int *)bp->cfg_data);
266 if ((magic & BANDIT_COHERENT) != 0)
267 return;
268 magic |= BANDIT_COHERENT;
269 udelay(2);
270 out_le32((volatile unsigned int *)bp->cfg_data, magic);
271 printk(KERN_INFO "Cache coherency enabled for bandit/PSX\n");
272 }
273
274
275 /*
276 * Tweak the PCI-PCI bridge chip on the blue & white G3s.
277 */
278 static void __init
init_p2pbridge(void)279 init_p2pbridge(void)
280 {
281 struct device_node *p2pbridge;
282 struct pci_controller* hose;
283 u8 bus, devfn;
284 u16 val;
285
286 /* XXX it would be better here to identify the specific
287 PCI-PCI bridge chip we have. */
288 if ((p2pbridge = find_devices("pci-bridge")) == 0
289 || p2pbridge->parent == NULL
290 || strcmp(p2pbridge->parent->name, "pci") != 0)
291 return;
292 if (pci_device_from_OF_node(p2pbridge, &bus, &devfn) < 0) {
293 #ifdef DEBUG
294 printk("Can't find PCI infos for PCI<->PCI bridge\n");
295 #endif
296 return;
297 }
298 /* Warning: At this point, we have not yet renumbered all busses.
299 * So we must use OF walking to find out hose
300 */
301 hose = pci_find_hose_for_OF_device(p2pbridge);
302 if (!hose) {
303 #ifdef DEBUG
304 printk("Can't find hose for PCI<->PCI bridge\n");
305 #endif
306 return;
307 }
308 if (early_read_config_word(hose, bus, devfn,
309 PCI_BRIDGE_CONTROL, &val) < 0) {
310 printk(KERN_ERR "init_p2pbridge: couldn't read bridge control\n");
311 return;
312 }
313 val &= ~PCI_BRIDGE_CTL_MASTER_ABORT;
314 early_write_config_word(hose, bus, devfn, PCI_BRIDGE_CONTROL, val);
315 }
316
317 /*
318 * Some Apple desktop machines have a NEC PD720100A USB2 controller
319 * on the motherboard. Open Firmware, on these, will disable the
320 * EHCI part of it so it behaves like a pair of OHCI's. This fixup
321 * code re-enables it ;)
322 */
323 static void __init
fixup_nec_usb2(void)324 fixup_nec_usb2(void)
325 {
326 struct device_node *nec;
327
328 for (nec = find_devices("usb"); nec != NULL; nec = nec->next) {
329 struct pci_controller *hose;
330 u32 data, *prop;
331 u8 bus, devfn;
332
333 prop = (u32 *)get_property(nec, "vendor-id", NULL);
334 if (prop == NULL)
335 continue;
336 if (0x1033 != *prop)
337 continue;
338 prop = (u32 *)get_property(nec, "device-id", NULL);
339 if (prop == NULL)
340 continue;
341 if (0x0035 != *prop)
342 continue;
343 prop = (u32 *)get_property(nec, "reg", 0);
344 if (prop == NULL)
345 continue;
346 devfn = (prop[0] >> 8) & 0xff;
347 bus = (prop[0] >> 16) & 0xff;
348 if (PCI_FUNC(devfn) != 0)
349 continue;
350 hose = pci_find_hose_for_OF_device(nec);
351 if (!hose)
352 continue;
353 printk("Found NEC PD720100A USB2 chip, enabling EHCI...\n");
354 early_read_config_dword(hose, bus, devfn, 0xe4, &data);
355 data &= ~1UL;
356 early_write_config_dword(hose, bus, devfn, 0xe4, data);
357 early_write_config_byte(hose, bus, devfn | 2, PCI_INTERRUPT_LINE,
358 nec->intrs[0].line);
359 }
360 }
361
362 void __init
pmac_find_bridges(void)363 pmac_find_bridges(void)
364 {
365 add_bridges(find_devices("bandit"));
366 add_bridges(find_devices("chaos"));
367 add_bridges(find_devices("pci"));
368 init_p2pbridge();
369 fixup_nec_usb2();
370 }
371
372 #define GRACKLE_CFA(b, d, o) (0x80 | ((b) << 8) | ((d) << 16) \
373 | (((o) & ~3) << 24))
374
375 #define GRACKLE_PICR1_STG 0x00000040
376 #define GRACKLE_PICR1_LOOPSNOOP 0x00000010
377
378 /* N.B. this is called before bridges is initialized, so we can't
379 use grackle_pcibios_{read,write}_config_dword. */
grackle_set_stg(struct pci_controller * bp,int enable)380 static inline void grackle_set_stg(struct pci_controller* bp, int enable)
381 {
382 unsigned int val;
383
384 out_be32(bp->cfg_addr, GRACKLE_CFA(0, 0, 0xa8));
385 val = in_le32((volatile unsigned int *)bp->cfg_data);
386 val = enable? (val | GRACKLE_PICR1_STG) :
387 (val & ~GRACKLE_PICR1_STG);
388 out_be32(bp->cfg_addr, GRACKLE_CFA(0, 0, 0xa8));
389 out_le32((volatile unsigned int *)bp->cfg_data, val);
390 (void)in_le32((volatile unsigned int *)bp->cfg_data);
391 }
392
grackle_set_loop_snoop(struct pci_controller * bp,int enable)393 static inline void grackle_set_loop_snoop(struct pci_controller *bp, int enable)
394 {
395 unsigned int val;
396
397 out_be32(bp->cfg_addr, GRACKLE_CFA(0, 0, 0xa8));
398 val = in_le32((volatile unsigned int *)bp->cfg_data);
399 val = enable? (val | GRACKLE_PICR1_LOOPSNOOP) :
400 (val & ~GRACKLE_PICR1_LOOPSNOOP);
401 out_be32(bp->cfg_addr, GRACKLE_CFA(0, 0, 0xa8));
402 out_le32((volatile unsigned int *)bp->cfg_data, val);
403 (void)in_le32((volatile unsigned int *)bp->cfg_data);
404 }
405
406 static int __init
setup_uninorth(struct pci_controller * hose,struct reg_property * addr)407 setup_uninorth(struct pci_controller* hose, struct reg_property* addr)
408 {
409 pci_assign_all_busses = 1;
410 has_uninorth = 1;
411 hose->ops = ¯isc_pci_ops;
412 hose->cfg_addr = ioremap(addr->address + 0x800000, 0x1000);
413 hose->cfg_data = ioremap(addr->address + 0xc00000, 0x1000);
414 /* We "know" that the bridge at f2000000 has the PCI slots. */
415 return addr->address == 0xf2000000;
416 }
417
418 static void __init
setup_bandit(struct pci_controller * hose,struct reg_property * addr)419 setup_bandit(struct pci_controller* hose, struct reg_property* addr)
420 {
421 hose->ops = ¯isc_pci_ops;
422 hose->cfg_addr = (volatile unsigned int *)
423 ioremap(addr->address + 0x800000, 0x1000);
424 hose->cfg_data = (volatile unsigned char *)
425 ioremap(addr->address + 0xc00000, 0x1000);
426 init_bandit(hose);
427 }
428
429 static void __init
setup_chaos(struct pci_controller * hose,struct reg_property * addr)430 setup_chaos(struct pci_controller* hose, struct reg_property* addr)
431 {
432 /* assume a `chaos' bridge */
433 hose->ops = &chaos_pci_ops;
434 hose->cfg_addr = (volatile unsigned int *)
435 ioremap(addr->address + 0x800000, 0x1000);
436 hose->cfg_data = (volatile unsigned char *)
437 ioremap(addr->address + 0xc00000, 0x1000);
438 }
439
440 void __init
setup_grackle(struct pci_controller * hose)441 setup_grackle(struct pci_controller *hose)
442 {
443 setup_indirect_pci(hose, 0xfec00000, 0xfee00000);
444 if (machine_is_compatible("AAPL,PowerBook1998"))
445 grackle_set_loop_snoop(hose, 1);
446 #if 0 /* Disabled for now, HW problems ??? */
447 grackle_set_stg(hose, 1);
448 #endif
449 }
450
451 /*
452 * We assume that if we have a G3 powermac, we have one bridge called
453 * "pci" (a MPC106) and no bandit or chaos bridges, and contrariwise,
454 * if we have one or more bandit or chaos bridges, we don't have a MPC106.
455 */
456 static void __init
add_bridges(struct device_node * dev)457 add_bridges(struct device_node *dev)
458 {
459 int len;
460 struct pci_controller *hose;
461 struct reg_property *addr;
462 char* disp_name;
463 int *bus_range;
464 int first = 1, primary;
465
466 for (; dev != NULL; dev = dev->next) {
467 addr = (struct reg_property *) get_property(dev, "reg", &len);
468 if (addr == NULL || len < sizeof(*addr)) {
469 printk(KERN_WARNING "Can't use %s: no address\n",
470 dev->full_name);
471 continue;
472 }
473 bus_range = (int *) get_property(dev, "bus-range", &len);
474 if (bus_range == NULL || len < 2 * sizeof(int)) {
475 printk(KERN_WARNING "Can't get bus-range for %s, assume bus 0\n",
476 dev->full_name);
477 }
478
479 hose = pcibios_alloc_controller();
480 if (!hose)
481 continue;
482 hose->arch_data = dev;
483 hose->first_busno = bus_range ? bus_range[0] : 0;
484 hose->last_busno = bus_range ? bus_range[1] : 0xff;
485
486 disp_name = NULL;
487 primary = first;
488 if (device_is_compatible(dev, "uni-north")) {
489 primary = setup_uninorth(hose, addr);
490 disp_name = "UniNorth";
491 } else if (strcmp(dev->name, "pci") == 0) {
492 /* XXX assume this is a mpc106 (grackle) */
493 setup_grackle(hose);
494 disp_name = "Grackle (MPC106)";
495 } else if (strcmp(dev->name, "bandit") == 0) {
496 setup_bandit(hose, addr);
497 disp_name = "Bandit";
498 } else if (strcmp(dev->name, "chaos") == 0) {
499 setup_chaos(hose, addr);
500 disp_name = "Chaos";
501 primary = 0;
502 }
503 printk(KERN_INFO "Found %s PCI host bridge at 0x%08x. Firmware bus number: %d->%d\n",
504 disp_name, addr->address, hose->first_busno, hose->last_busno);
505 #ifdef DEBUG
506 printk(" ->Hose at 0x%08lx, cfg_addr=0x%08lx,cfg_data=0x%08lx\n",
507 hose, hose->cfg_addr, hose->cfg_data);
508 #endif
509
510 /* Interpret the "ranges" property */
511 /* This also maps the I/O region and sets isa_io/mem_base */
512 pci_process_bridge_OF_ranges(hose, dev, primary);
513
514 /* Fixup "bus-range" OF property */
515 fixup_bus_range(dev);
516
517 first &= !primary;
518 }
519 }
520
521 static void __init
pcibios_fixup_OF_interrupts(void)522 pcibios_fixup_OF_interrupts(void)
523 {
524 struct pci_dev* dev;
525
526 /*
527 * Open Firmware often doesn't initialize the
528 * PCI_INTERRUPT_LINE config register properly, so we
529 * should find the device node and apply the interrupt
530 * obtained from the OF device-tree
531 */
532 pci_for_each_dev(dev) {
533 struct device_node* node = pci_device_to_OF_node(dev);
534 /* this is the node, see if it has interrupts */
535 if (node && node->n_intrs > 0)
536 dev->irq = node->intrs[0].line;
537 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
538 }
539 }
540
541 void __init
pmac_pcibios_fixup(void)542 pmac_pcibios_fixup(void)
543 {
544 /* Fixup interrupts according to OF tree */
545 pcibios_fixup_OF_interrupts();
546 }
547
548 int __pmac
pmac_pci_enable_device_hook(struct pci_dev * dev,int initial)549 pmac_pci_enable_device_hook(struct pci_dev *dev, int initial)
550 {
551 struct device_node* node;
552 int updatecfg = 0;
553 int uninorth_child;
554
555 node = pci_device_to_OF_node(dev);
556
557 /* We don't want to enable USB controllers absent from the OF tree
558 * (iBook second controller)
559 */
560 if (dev->vendor == PCI_VENDOR_ID_APPLE
561 && dev->device == PCI_DEVICE_ID_APPLE_KL_USB && !node)
562 return -EINVAL;
563
564 if (!node)
565 return 0;
566
567 uninorth_child = node->parent &&
568 device_is_compatible(node->parent, "uni-north");
569
570 /* Firewire & GMAC were disabled after PCI probe, the driver is
571 * claiming them, we must re-enable them now.
572 */
573 if (uninorth_child && !strcmp(node->name, "firewire") &&
574 (device_is_compatible(node, "pci106b,18") ||
575 device_is_compatible(node, "pci106b,30") ||
576 device_is_compatible(node, "pci11c1,5811"))) {
577 pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, node, 0, 1);
578 pmac_call_feature(PMAC_FTR_1394_ENABLE, node, 0, 1);
579 updatecfg = 1;
580 }
581 if (uninorth_child && !strcmp(node->name, "ethernet") &&
582 device_is_compatible(node, "gmac")) {
583 pmac_call_feature(PMAC_FTR_GMAC_ENABLE, node, 0, 1);
584 updatecfg = 1;
585 }
586
587 if (updatecfg) {
588 u16 cmd;
589
590 /*
591 * Make sure PCI is correctly configured
592 *
593 * We use old pci_bios versions of the function since, by
594 * default, gmac is not powered up, and so will be absent
595 * from the kernel initial PCI lookup.
596 *
597 * Should be replaced by 2.4 new PCI mecanisms and really
598 * regiser the device.
599 */
600 pci_read_config_word(dev, PCI_COMMAND, &cmd);
601 cmd |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE;
602 pci_write_config_word(dev, PCI_COMMAND, cmd);
603 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 16);
604 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 8);
605 }
606
607 return 0;
608 }
609
610 /* We power down some devices after they have been probed. They'll
611 * be powered back on later on
612 */
613 void __init
pmac_pcibios_after_init(void)614 pmac_pcibios_after_init(void)
615 {
616 struct device_node* nd;
617
618 #ifdef CONFIG_BLK_DEV_IDE
619 struct pci_dev *dev;
620
621 /* OF fails to initialize IDE controllers on macs
622 * (and maybe other machines)
623 *
624 * Ideally, this should be moved to the IDE layer, but we need
625 * to check specifically with Andre Hedrick how to do it cleanly
626 * since the common IDE code seem to care about the fact that the
627 * BIOS may have disabled a controller.
628 *
629 * -- BenH
630 */
631 pci_for_each_dev(dev) {
632 if ((dev->class >> 16) == PCI_BASE_CLASS_STORAGE)
633 pci_enable_device(dev);
634 }
635 #endif /* CONFIG_BLK_DEV_IDE */
636
637 nd = find_devices("firewire");
638 while (nd) {
639 if (nd->parent && (device_is_compatible(nd, "pci106b,18") ||
640 device_is_compatible(nd, "pci106b,30") ||
641 device_is_compatible(nd, "pci11c1,5811"))
642 && device_is_compatible(nd->parent, "uni-north")) {
643 pmac_call_feature(PMAC_FTR_1394_ENABLE, nd, 0, 0);
644 pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, nd, 0, 0);
645 }
646 nd = nd->next;
647 }
648 nd = find_devices("ethernet");
649 while (nd) {
650 if (nd->parent && device_is_compatible(nd, "gmac")
651 && device_is_compatible(nd->parent, "uni-north"))
652 pmac_call_feature(PMAC_FTR_GMAC_ENABLE, nd, 0, 0);
653 nd = nd->next;
654 }
655 }
656
657